CY7C1021CV33 1-Mbit (64K x 16) Static RAM Functional Description[1] Features • Temperature Ranges The CY7C1021CV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C — Automotive-E: –40°C to 125°C • Pin- and function-compatible with CY7C1021BV33 • High speed — tAA = 8 ns (Commercial & Industrial) — tAA = 12 ns (Automotive) • CMOS for optimum speed/power • Low active power: 345 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in Pb-free and non Pb-free 44-pin 400-Mil SOJ 44-pin TSOP II and 48-ball FBGA packages Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021CV33 is available in 44-pin 400-Mil wide SOJ, 44-pin TSOP II and 48-ball FBGA packages. Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05132 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 6, 2006 [+] Feedback CY7C1021CV33 Selection Guide Maximum Access Time Maximum Operating Current Comm’l/Ind’l -8 -10 -12 -15 Unit 8 10 12 15 ns 95 90 85 80 mA 80 mA Automotive-A Automotive-E Maximum CMOS Standby Current Comm’l/Ind’l 90 5 5 mA 5 5 Automotive-A 5 Automotive-E 10 mA mA mA Pin Configurations[2] SOJ/TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 48-ball FBGA Top View A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O2 I/O1 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Note: 2. NC pins are not connected on the die. Document #: 38-05132 Rev. *G Page 2 of 13 [+] Feedback CY7C1021CV33 Pin Definitions Pin Name A0–A15 I/O0–I/O15[3] SOJ, TSOP Pin Number BGA Pin Number 1–5, 18–21, A3, A4, A5, 24–27, 42–44 B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4 I/O Type Input Description Address Inputs used to select one of the address locations. 7–10, 13–16, B6, C6, C5, Input/Output Bidirectional Data I/O lines. Used as input or output lines 29–32, 35–38 D5, E5, F5, depending on operation. F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 No Connect No Connects. Not connected to the die. NC 22, 23, 28 A6, D3, E3, E4, G2, H1, H6 WE 17 G5 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. CE 6 B5 Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 B2, A1 OE 41 A2 VSS 12,34 D1, E6 VCC 11,33 D6, E1 Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9, BLE controls I/O8–I/O1. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power Supply inputs to the device. Note: 3. I/O1–I/O16 for SOJ/TSOP and I/O0–I/O15 for BGA packages. Document #: 38-05132 Rev. *G Page 3 of 13 [+] Feedback CY7C1021CV33 Maximum Ratings Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current...................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Range Supply Voltage on VCC Relative to GND[4] .... –0.5V to +4.6V Commercial DC Voltage Applied to Outputs in High-Z State[4] ......................................–0.5V to VCC+0.5V DC Input Voltage[4] ...................................–0.5V to VCC+0.5V Current into Outputs (LOW) .........................................20 mA Ambient Temperature (TA) VCC 0°C to +70°C 3.3V ± 10% Industrial –40°C to +85°C Automotive-A –40°C to +85°C Automotive -E –40°C to +125°C Electrical Characteristics Over the Operating Range -8 Parameter Description Test Conditions Min. -10 Max. 2.4 Min. -12 Max. 2.4 Min. -15 Max. 2.4 Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW Voltage[4] –0.3 0.8 −0.3 0.8 –0.3 IIX Input Leakage Current −1 +1 −1 +1 0.4 GND < VI < VCC Com’l/Ind’l 0.4 IOZ Output Leakage Current GND < VI < VCC, Com’l/Ind’l Output Disabled Auto-A VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com’l/Ind’l Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Com’l/Ind’l Automatic CE Power-Down Current —CMOS Inputs Max. VCC, Com’l/Ind’l CE > VCC – 0.3V, Auto-A VIN > VCC – 0.3V, Auto-E or VIN < 0.3V, f=0 −1 +1 −1 +1 Auto-E ICC ISB1 ISB2 0.4 90 2.0 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –12 +12 –1 +1 –1 +1 –1 +1 µA +12 85 Auto-A Auto-E V V –12 95 Max. Unit 0.4 Auto-A Auto-E Min. 2.4 VOH 80 mA 80 mA 15 mA 90 15 15 15 Auto-A 15 Auto-E 20 5 5 5 5 mA 5 10 Note: 4. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. Document #: 38-05132 Rev. *G Page 4 of 13 [+] Feedback CY7C1021CV33 Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Thermal Resistance[5] Parameter ΘJA Description Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions SOJ TSOP II FBGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 65.06 76.92 95.32 °C/W 34.21 15.86 10.68 °C/W AC Test Loads and Waveforms[6] 8-ns devices: 10-, 12-, 15-ns devices: Z = 50Ω 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317Ω 3.3V OUTPUT 30 pF* OUTPUT R2 351Ω 30 pF* 1.5V (b) (a) High-Z characteristics: R 317Ω 90% GND 3.3V ALL INPUT PULSES 3.0V 90% 10% 10% Rise Time: 1 V/ns (c) Fall Time: 1 V/ns OUTPUT R2 351Ω 5 pF (d) Notes: 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). Document #: 38-05132 Rev. *G Page 5 of 13 [+] Feedback CY7C1021CV33 Switching Characteristics Over the Operating Range[7] -8 Parameter Description Min. -10 Max. Min. -12 Max. Min. -15 Max. Min. Max. Unit Read Cycle 100 100 100 100 µs 8 10 12 15 ns tpower[8] VCC(typical) to the first access tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 8 10 12 15 ns tDOE OE LOW to Data Valid 5 5 6 7 ns tLZOE OE LOW to Low-Z [9] 8 3 tHZOE OE HIGH to High-Z tLZCE CE LOW to Low-Z[9] 3 0 [9, 10] 10 4 High-Z[9, 10] 3 0 3 12 5 6 ns 7 3 ns CE HIGH to CE LOW to Power-Up CE HIGH to Power-Down 8 10 12 15 ns tDBE Byte Enable to Data Valid 5 5 6 7 ns tLZBE Byte Enable to Low-Z Write Cycle 0 0 Byte Disable to High-Z 0 0 4 6 ns tPU[11] tPD[11] 0 5 ns 0 3 ns tHZCE tHZBE 4 3 0 3 15 0 0 5 7 ns 0 6 ns ns 7 ns [12] tWC Write Cycle Time 8 10 12 15 ns tSCE CE LOW to Write End 7 8 9 10 ns tAW Address Set-up to Write End 7 8 9 10 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 6 7 8 10 ns tSD Data Set-up to Write End 5 5 6 8 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low-Z[9] 3 3 3 3 ns tHZWE WE LOW to High-Z[9, 10] tBW Byte Enable to End of Write 4 6 5 7 6 8 7 9 ns ns Notes: 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05132 Rev. *G Page 6 of 13 [+] Feedback CY7C1021CV33 Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 13. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05132 Rev. *G Page 7 of 13 [+] Feedback CY7C1021CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 16. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05132 Rev. *G Page 8 of 13 [+] Feedback CY7C1021CV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table WE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High-Z Read – Lower bits only Active (ICC) H L High-Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High-Z Write – Lower bits only Active (ICC) H L High-Z Data In Write – Upper bits only Active (ICC) X L BHE I/O9–I/O16[3] OE L BLE I/O1–I/O8[3] CE Mode Power L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Document #: 38-05132 Rev. *G Page 9 of 13 [+] Feedback CY7C1021CV33 Ordering Information Speed (ns) 8 Ordering Code Package Diagram CY7C1021CV33-8VXC 51-85082 CY7C1021CV33-8ZXC 10 CY7C1021CV33-8BAXC 51-85096 48-ball FBGA (Pb-free) CY7C1021CV33-10VC 51-85082 44-pin (400-Mil) Molded SOJ CY7C1021CV33-10ZXC 51-85087 44-pin TSOP Type II CY7C1021CV33-10ZXI 44-pin TSOP Type II (Pb-free) CY7C1021CV33-10BAXI 51-85096 48-ball FBGA (Pb-free) CY7C1021CV33-12VC 51-85082 44-pin (400-Mil) Molded SOJ CY7C1021CV33-12VXC 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12VI 44-pin (400-Mil) Molded SOJ Industrial 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II (Pb-free) Industrial 51-85096 48-ball FBGA Industrial 51-85087 44-pin TSOP Type II Commercial 51-85082 44-pin (400-Mil) Molded SOJ 48-ball FBGA (Pb-free) CY7C1021CV33-12ZSXE CY7C1021CV33-12VE Commercial 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12BAXI CY7C1021CV33-12ZSE Industrial 51-85087 CY7C1021CV33-12ZXI CY7C1021CV33-12BAI Commercial 44-pin TSOP Type II (Pb-free) CY7C1021CV33-10ZI CY7C1021CV33-12ZXC Commercial 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12VXI Automotive-E 44-pin TSOP Type II (Pb-free) CY7C1021CV33-12VXE 15 44-pin (400-Mil) Molded SOJ (Pb-free) Operating Range 44-pin TSOP Type II (Pb-free) CY7C1021CV33-10VXC 12 Package Type 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021CV33-12BAE 51-85096 48-ball FBGA CY7C1021CV33-15VXC 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) Commercial CY7C1021CV33-15ZXC 51-85087 44-pin TSOP Type II (Pb-free) Commercial CY7C1021CV33-15ZI 44-pin TSOP Type II CY7C1021CV33-15ZXI 44-pin TSOP Type II (Pb-free) CY7C1021CV33-15BAXI 51-85096 48-ball FBGA (Pb-free) CY7C1021CV33-15ZSXA 51-85087 44-pin TSOP Type II (Pb-free) Industrial Automotive-A Please contact local sales representative regarding availability of these parts Document #: 38-05132 Rev. *G Page 10 of 13 [+] Feedback CY7C1021CV33 Package Diagrams 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-pin Thin Small Outline Package Type II (51-85087) 51-85087-*A Document #: 38-05132 Rev. *G Page 11 of 13 [+] Feedback CY7C1021CV33 Package Diagrams (continued) 48-ball FBGA (7 x 7 x 1.2 mm) (51-85096) BOTTOM VIEW TOP VIEW PIN 1 CORNER Ø0.05 M C PIN 1 CORNER (LASER MARK) Ø0.25 M C A B Ø0.30±0.05(48X) 1 2 3 4 5 6 6 4 3 2 1 C F G D E F 2.625 E 0.75 C 5.25 B 7.00±0.10 A B D 7.00±0.10 5 A G H H A A 1.875 0.75 B 7.00±0.10 3.75 7.00±0.10 0.10 C 0.21±0.05 0.53±0.05 0.25 C B 0.15(4X) 51-85096-*F 0.36 SEATING PLANE C 1.20 MAX. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05132 Rev. *G Page 12 of 13 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1021CV33 Document History Page Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109472 12/06/01 HGK New Data Sheet *A 115044 05/08/02 HGK Ram7 version C4K x 16 Async Remove “Preliminary” *B 115808 06/25/02 HGK ISB1 and ICC values changed *C 120413 10/31/02 DFP Updated BGA pin E4 to NC *D 238454 See ECN RKF 1) Added Automotive Specs to Data sheet 2) Added Pb-free devices in the Ordering Information *E 334398 See ECN SYT Added Pb-free on page# 9 and 10 *F 493565 See ECN NXR Added Automotive-A operating range Corrected typo in the Pin Definition table Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table *G 563963 See ECN VKN Added tPOWER spec in the AC Switching Characteristics table Added footnote #8 Document #: 38-05132 Rev. *G Page 13 of 13 [+] Feedback