CYPRESS CY7C1020DV33

CY7C1020DV33
512K (32K x 16) Static RAM
Features
• Pin-and function-compatible with CY7C1020CV33
• High speed
— tAA = 10 ns
• Low active power
— ICC = 60 mA @ 10 ns
• Low CMOS standby power
•
•
•
•
•
— ISB2 = 3 mA
2.0V Data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Independent control of upper and lower bits
Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description[1]
The CY7C1020DV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ and 44-pin TSOP II packages.
Logic Block Diagram
Pin Configuration[2]
SOJ/TSOP II
Top View
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
32K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
A14
A12
A13
A8
A9
A10
A11
COLUMN DECODER
NC
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A4
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Notes
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
2. NC pins are not connected on the die.
Cypress Semiconductor Corporation
Document #: 38-05461 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 14, 2010
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CY7C1020DV33
Selection Guide
–10 (Industrial)
–12 (Automotive)[3]
Unit
Maximum Access Time
10
12
ns
Maximum Operating Current
60
100
mA
Maximum CMOS Standby Current
3
15
mA
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65C to +150C
Ambient Temperature with
Power Applied............................................. –55C to +125C
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Supply Voltage on VCC to Relative GND[4] .... –0.5V to +4.6V
Range
VCC
Speed
DC Voltage Applied to Outputs
in High-Z State[4] ....................................–0.5V to VCC + 0.5V
Ambient
Temperature
Industrial
–40 C to +85 C
3.3V  0.3V
10 ns
Automotive
–40 C to +125 C
DC Input Voltage[4] .................................–0.5V to VCC + 0.5V
12 ns
Electrical Characteristics Over the Operating Range
Parameter
Description
–10 (Industrial)
Test Conditions
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.4
Voltage[4]
Input LOW
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
ISB2
Min.
Max.
2.4
0.4
VIL
ISB1
Max.
–12 (Automotive)
Unit
V
0.4
V
2.0
VCC + 0.3
2.0
VCC + 0.3
V
0.3
0.8
0.3
0.8
V
1
+1
1
+1
A
1
+1
1
+1
A
100 MHz
60
-
mA
83 MHz
55
100
mA
66 MHz
45
90
mA
40 MHz
30
60
mA
Automatic CE Power-down Max. VCC, CE > VIH
Current—TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
Automatic CE Power-down Max. VCC, CE > VCC – 0.3V,
Current—CMOS Inputs
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
10
50
mA
3
15
mA
Notes
3. Automotive Product Information is Preliminary.
4. VIL (min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
Document #: 38-05461 Rev. *F
Page 2 of 12
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CY7C1020DV33
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
8
pF
8
pF
TA = 25C, f = 1 MHz, VCC = 3.3V
Thermal Resistance[5]
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
SOJ
TSOP II
Unit
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
53.91
C/W
36.75
21.24
C/W
AC Test Loads and Waveforms[6]
ALL INPUT PULSES
3.0V
Z = 50
90%
OUTPUT
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
10%
10%
GND
30 pF*
90%
1.5V
Rise Time: 1 V/ns
(a)
(b)
Fall Time: 1 V/ns
High-Z characteristics: R 317
3.3V
OUTPUT
R2
351
5 pF
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05461 Rev. *F
Page 3 of 12
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CY7C1020DV33
Switching Characteristics Over the Operating Range [7]
Parameter
Description
–10 (Industrial)
Min.
Max.
–12 (Automotive)
Min.
Max.
Unit
Read Cycle
tpower[8]
VCC(typical) to the first access
100
100
s
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
6
ns
OE LOW to
Low-Z[9]
OE HIGH to
High-Z[9, 10]
CE LOW to
Low-Z[9]
tHZCE
CE HIGH to
High-Z[9, 10]
tPU[11]
tPD[11]
CE LOW to Power-up
CE HIGH to Power-down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
tLZOE
tHZOE
tLZCE
12
3
0
3
ns
6
3
5
ns
ns
0
5
ns
ns
6
ns
10
12
ns
5
6
ns
0
0
0
Byte Disable to High-Z
tHZBE
Write
10
3
ns
0
5
ns
6
ns
Cycle[12]
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
8
9
ns
tAW
Address Set-up to Write End
8
9
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-up to Write End
5
6
ns
tHD
Data Hold from Write End
0
0
ns
3
3
ns
WE HIGH to
Low-Z[9]
tHZWE
WE LOW to
High-Z[9, 10]
tBW
Byte Enable to End of Write
tLZWE
5
7
6
8
ns
ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed
9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. This parameter is guaranteed by design and is not tested.
12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and
the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05461 Rev. *F
Page 4 of 12
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CY7C1020DV33
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC
ICCDR
Data Retention Current
tCDR
[5]
Conditions
Min.
Unit
2.0
V
VCC = VDR = 2.0V, CE > VCC – 0.3V, Industrial
VIN > VCC – 0.3V or VIN < 0.3V
Automotive
Chip Deselect to Data Retention Time
tR[13]
Max.
Operation Recovery Time
3
mA
15
mA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
tCDR
3.0V
tR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tHZBE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes:
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05461 Rev. *F
Page 5 of 12
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CY7C1020DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes:
17. Data I/O is high impedance if OE or BHE and/or BLE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05461 Rev. *F
Page 6 of 12
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CY7C1020DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read—All bits
Active (ICC)
L
H
Data Out
High-Z
Read—Lower bits only
Active (ICC)
H
L
High-Z
Data Out
Read—Upper bits only
Active (ICC)
L
L
Data In
Data In
Write—All bits
Active (ICC)
L
H
Data In
High-Z
Write—Lower bits only
Active (ICC)
H
L
High-Z
Data In
Write—Upper bits only
Active (ICC)
L
X
L
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05461 Rev. *F
Page 7 of 12
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CY7C1020DV33
Ordering Information
Speed
(ns)
10
12
Ordering Code
Package
Name
CY7C1020DV33-10VXI
51-85082
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1020DV33-10ZSXI
51-85087
44-pin TSOP Type II (Pb-free)
CY7C1020DV33-12ZSXE
51-85087
44-pin TSOP Type II (Pb-free)
Package Type
Operating Range
Industrial
Automotive
Ordering Code Definitions
CY 7 C 1 02 0 D V33 - XX XX X
Temperature Range: X = I or E
I = Industrial; E = Automotive
Package Type: XX = VX or ZSX
VX = 44-pin Molded SOJ (Pb-free)
ZSX = 44-pin TSOP Type II (Pb-free)
Speed: XX = 10 ns or 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
0 = Data width × 16-bits
02 = 512-Kbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05461 Rev. *F
Page 8 of 12
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CY7C1020DV33
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082)
51-85082 *C
Document #: 38-05461 Rev. *F
Page 9 of 12
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CY7C1020DV33
Package Diagrams (continued)
Figure 2. 44-Pin Thin Small Outline Package Type II (51-85087)
51-85087 *C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05461 Rev. *F
Page 10 of 12
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CY7C1020DV33
Document History Page
Document Title: CY7C1020DV33, 512K (32K x 16) Static RAM
Document Number: 38-05461
REV.
ECN NO.
Issue Date
Orig. of
Change
**
201560
See ECN
SWI
Advance Information data sheet for C9 IPP
*A
233695
See ECN
RKF
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in Ordering Information
*B
262950
See ECN
RKF
Changed I/O1 – I/O16 to I/O0 – I/O15
Added Data Retention Characteristics table
Added Tpower spec in Switching Characteristics table
Added 44-SOJ package diagram
Shaded Ordering Information
*C
307596
See ECN
RKF
Reduced Speed bins to –8 and –10 ns
*D
560995
See ECN
VKN
Converted from Preliminary to Final
Removed Commercial operating range
Removed 8 ns speed bin
Added Automotive information
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
2898399
03/24/2010
AJU
Updated Package Diagrams
*F
3109992
12/14/2010
AJU
Added Ordering Code Definitions.
Document #: 38-05461 Rev. *F
Description of Change
Page 11 of 12
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CY7C1020DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at cypress.com/sales.
Products
Automotive
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Interface
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cypress.com/go/automotive
PSoC Solutions
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
Document #: 38-05461 Rev. *F
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
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© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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