ESMT F49B002UA-70N

EFST
F49B002UA
2 Mbit (256K x 8)
5V Only CMOS Flash Memory
1. FEATURES
Single supply voltage 5V ±10%
Fast access time: 70/90 ns
z Compatible with JEDEC standard
- Pin-out, packages and software commands
compatible with single-power supply Flash
z Low power consumption
- 25mA maximum active current
- 25uA typical standby current 
z 100,000 program/erase cycles typically
z Command register architecture
- Byte programming (10us typical)
- Sector Erase( sector structure: 16KB, 8KB, 8KB,
96KB, 128KB )
z Auto Erase (chip & sector) and Auto Program
- Sector erase and Chip erase.
- Automatically program and verify data at specified
address
z
z
z
z
z
End of program or erase detection
- Data polling
- Toggle bits
Boot Sector Architecture
- U = Upper Boot Sector
Packages available:
- 32-pin PDIP
- 32-pin PLCC
2. ORDERING INFORMATION
Part No
Boot
Speed
Package
Part No
Boot
Speed
Package
F49B002UA-70D
Upper
70 ns
PDIP
F49B002UA-90D
Upper
90 ns
PDIP
F49B002UA-70N
Upper
70 ns
PLCC
F49B002UA-90N
Upper
90 ns
PLCC
3. GENERAL DESCRIPTION
The F49B002UA is a 2 Megabit, 5V only CMOS Flash
memory device organized as 256K bytes of 8 bits. This
device is packaged in standard 32-pin PDIP and 32-pin
PLCC. It is designed to be programmed and erased both
in system and can in standard EPROM programmers.
With access times of 70 ns and 90 ns, the F49B002UA
allows the operation of high-speed microprocessors. The
device has separate chip enable CE , write enable WE ,
and output enable OE controls. EFST's memory devices
reliably store memory data even after 10,000 program and
erase cycles.
The F49B002UA features a sector erase architecture.
The device memory array is divided into 16 Kbytes, 8K
bytes, 8Kbytes, 96Kbytes, 128Kbytes. Erase capabilities
provide the flexibility to revise the data in the device.
A low VCC detector inhibits write operations on loss of
power. End of program or erase is detected by the Data
Polling of DQ7, or by the Toggle Bit feature on DQ6. Once
the program or erase cycle has been successfully
completed, the device internally resets to the Read mode.
The F49B002UA is entirely pin and command set
compatible with the JEDEC standard for 2 Megabit Flash
memory devices. Commands are written to the command
register using standard microprocessor write timings.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
1/33
EFST
F49B002UA
4. PIN CONFIGURATIONS
4.1
32-pin PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
4.2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3 2 - P in
DIP
VD D
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
32-pin PLCC
A0
DQ 0
A17
A1
WE
A2
2
VCC
A3
3
NC
A4
A16
A5
A12
A6
A15
A7
4
1 32 31 30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
14 15 16 1 7 18 19 2 0
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
4.3 Pin Description
Symbol
Pin Name
Functions
A0~A17
Address Input
DQ0~DQ7
Data Input/Output
CE
Chip Enable
To activate the device when CE is low.
OE
Output Enable
To gate the data output buffers.
WE
Write Enable
To control the Write operations.
NC
No connection
Power Supply
Ground
Unconnected pin
To provide power
VCC
GND
Elite Flash Storage Technology Inc.
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
Publication Date : Sep. 2006
Revision: 1.4
2/33
EFST
F49B002UA
5. SECTOR STRUCTURE
Table 1: F49B002UA Sector Address Table
Sector
Sector Size
(Kbytes)
Address range
SA4
16
SA3
Sector Address
A17
A16
A15
A14
A13
3C000H-3FFFFH
1
1
1
1
X
8
3A000H-3BFFFH
1
1
1
0
1
SA2
8
38000H-39FFFH
1
1
1
0
0
SA1
96
20000H-37FFFH
1
X
X
X
X
SA0
128
00000H-1FFFFH
0
X
X
X
X
6. FUNCTIONAL BLOCK DIAGRAM
CE
OE
St at e
co nt ro l
B4 (Boot) 16K
WE
B3 (Param.1) 8K
GND
VDD
A[17:0]
I/O
buffe r s
B2 (Param.2) 8K
Decorder
B1 (Main1) 96K
B0 (Main2) 128K
Elite Flash Storage Technology Inc.
DQ[7 :0]
3FFFF
3C000
3BFFF
3A000
39FFF
38000
37FFF
20000
1FFFF
00000
Publication Date : Sep. 2006
Revision: 1.4
3/33
EFST
F49B002UA
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function of the device. The F49B002UA features
various bus operations as Table 2.
Table 2. F49B002UA Operation Modes Selection
ADDRESS
DESCRIPTION
A17 A12
|
|
A13 A10
A8
|
A7
A5
|
A2
DQ0~DQ7
CE
OE
WE
Read
L
L
H
AIN
Dout
Write
L
H
L
AIN
DIN
Output Disable
L
H
H
X
High Z
Standby
H
X
X
X
High Z
Auto-select
A9
A6
A1 A0
See Table 3
Notes:
1. L= Logic Low = VIL, H= Logic High = VIH, X= Don't Care, SA= Sector Address, AIN= Address In, DIN = Data In,
Dout = Data Out.
Table 3. F49B002UA Auto-Select Mode (High Voltage Method)
ADDRESS
DESCRIPTION
(Manufacturer ID:EFST)
(Device ID: F49B002UA)
DQ0~DQ7
CE
OE
WE
A17
|
A13
A12
|
A10
A9
A8
|
A4
A6
A3
A2
A1
A0
L
L
H
X
X
VID
X
X
L
H
L
L
7FH
L
L
H
X
X
VID
X
X
H
L
L
L
7FH
L
L
H
X
X
VID
X
X
H
H
L
L
7FH
L
L
H
X
X
VID
X
X
L
L
L
L
8CH
L
L
H
X
X
VID
X
X
L
L
L
H
00H
Notes :
1.Manufacturer and device codes may also be accessed via the software command sequence in Table 4.
2. VID=11.5V to 12.5V.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
4/33
EFST
F49B002UA
Read Mode
Resetting the device
To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power
control and selects the device. OE is the output control
and gates array data to the output pins. WE should
remain at VIH. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power
transition.
The reset command returns the device to Read mode.
This is a necessary step after reading the device or
manufacturer ID. Note: In these cases, if VID is
removed from the A9 pin, the device automatically
returns to Read mode and an explicit is not required.
No command is necessary in this mode to obtain array
data. Standard microprocessor’s read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Read Command” section for more information.
Refer to the AC Read Operations Table 9 for timing
specifications and to Figure 5 for the timing diagram. ICC1
in the DC Characteristics Table 8 represents the active
current specification for reading array data.
Write Mode
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE and CE
to VIL, and OE to VIH. The “Program Command” section
has details on programming data to the device using
standard command sequences.
An erase operation can erase one sector, or the entire
device. Table 1 indicate the address space that each
sector occupies. A “sector address” consists of the address
bits required to uniquely select a sector. The “Software
Command Definitions” section has details on erasing a
sector or the entire chip.
When the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Auto-select Mode and Auto-select
Command sections for more information. ICC2 in the DC
Characteristics Table 8 represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification Table 10 and timing
diagrams for write operations.
Elite Flash Storage Technology Inc.
Boot block looking
To keep any system kernel code secure in the boot
block, the F49B002UA provides a command to lock
the boot block and prevent any accidental erasure or
reprogramming. The command sequence is similar to
the chip erase sequence except for the last cycle,
where 40H must be written into DQ0~DQ7 instead of
10H. The boot block is the only block that can be
locked in this way.
Whether or not the boot block has been locked can be
detected by the command sequence shown in Table 4.
This command sequence returns a “1” on DQ0 if the
boot block is locked; a “0” if the boot block has not
been locked and it is open to erasing and
programming.
Output Disable Mode
With the OE is at a logic high level (VIH), outputs from
the devices are disabled. This will cause the output pins
in a high impedance state
Standby Mode
When CE held at VCC ± 0.3V, the device enter
CMOS Standby mode. If CE held at VIH, but not within
the range of VCC ± 0.3V, the device will still be in the
standby mode, but the standby current will be larger.
If the device is deselected during auto algorithm of
erasure or programming, the device draws active
current ICC2 until the operation is completed. ICC3 in
the DC Characteristics Table 8 represents the standby
current specification.
The device requires standard access time (tCE) for
read access from either of these standby modes,
before it is ready to read data.
Publication Date : Sep. 2006
Revision: 1.4
5/33
EFST
F49B002UA
Auto-select Mode
The auto-select mode provides manufacturer and
device identification and sector protection verification,
through outputs on DQ7–DQ0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its
corresponding programming algorithm. However, the
auto-select codes can also be accessed in-system
through the command register.
When using programming equipment, this mode
requires VID (11.5 V to 12.5 V) on address pin A9.
While address pins A3, A2, A1, and A0 must be as
shown in Table 3.
To verify sector protection, all necessary pins have to
be set as required in Table 3, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in Table 4. This method
does not require VID. See “ Software Command
Definitions” for details on using the auto-select mode.
7.2 Software Command Definitions
Writing specific address and data commands or
sequences into the command register initiates the
device operations. Table 4 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE
or CE , whichever happens later. All data is latched on
the rising edge of WE or CE , whichever happens
first. Refer to the corresponding timing diagrams in
the AC Characteristics section.
Table 4. F49B002UA Software Command Definitions
Command
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
RA
RD
-
-
-
-
-
-
-
-
-
-
PA
PD
Read (4)
1
Program
4
5555H AAH 2AAAH 55H 5555H A0H
Chip Erase
6
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase
6
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
Boot block lock
6
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 40H
Reset 1(5)
1
XXXH
Reset 2(5)
3
5555H AAH 2AAAH 55H 5555H F0H
F0H
Auto-select
-
-
-
-
SA
30H
-
-
-
-
-
-
-
-
-
-
-
-
See Table 5.
Notes:
1.
X = don’t care
RA = Address of memory location to be read.
RD = Data to be read at location RA.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
2. Except Read command and Auto-select command, all command bus cycles are write operations.
3. Address bits A17–A16 are don’t cares.
4. No command cycles required when reading array data.
5. The two Reset command sequences have exactly the same effect, two are provided to meet the
requirements of difference companies and a range of applications.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
6/33
EFST
F49B002UA
Table 5. F49B002UA Auto-Select Command
Command
Manufacture ID
Device ID, Upper
boot
Bus
Cycles
1st Bus
Cycle
Addr
Data
2nd Bus
Cycle
Addr
3rd Bus
Cycle
Data Addr
4th Bus
Cycle
Data
Addr
Data
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
4
5555H AAH 2AAAH 55H 5555H 90H
XX04H 7FH
-
-
-
-
4
5555H AAH 2AAAH 55H 5555H 90H
XX08H 7FH
-
-
-
-
4
5555H AAH 2AAAH 55H 5555H 90H
XX0CH 7FH
-
-
-
-
4
5555H AAH 2AAAH 55H 5555H 90H
XX00H 8CH
-
-
-
-
4
5555H AAH 2AAAH 55H 5555H 90H
XX01H 00H
-
-
-
-
Notes :
1. The fourth cycle of the auto-select command sequence is a read cycle.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
7/33
EFST
F49B002UA
Read Command
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase.
See the “Read Mode” in the “Read Operations” section
for more information. Refer to AC Read Operation Table
9. & Figure 5 for the timing diagram.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation
immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
the data integrity.
Program Command
The program command sequence programs one byte
into the device. Programming is a four-bus-cycle
operation. The program command sequence is initiated
by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verifies the programmed cell
margin.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 and DQ6. See “Write Operation Status” section for
more information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. The
Program command sequence should be reinitiated once
the device has reset to reading array data, to ensure
data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit can’t be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation
or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read
will show that the data is still “0”. Only erase operations
can convert a “0” to a “1”.
Chip Erase Command
Chip erase is a six-bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm.
Elite Flash Storage Technology Inc.
The system can determine the status of the erase
operation by using DQ7 or DQ6, See “Programming &
Erasing Operation Status” section for more information
on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. See the Erase/Program
Operations Table 10,11 in “AC Characteristics” for
parameters.
Sector Erase Command
Sector erase is a six-bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the
sector for an all zero data pattern prior to electrical
erase. The system is not required to provide any
controls or timings during these operations.
The Sector Erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure the data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6
(Refer to “Programming & Erasing Operation Status”
section for more information on these status bits.)
Refer to the Erase/Program Operations Table 10,11 in
the “AC Characteristics” section for parameters.
Publication Date : Sep. 2006
Revision: 1.4
8/33
EFST
F49B002UA
Auto-select Command
The auto-select command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires
VID on address bit A9.
The auto-select command sequence is initiated by
writing two unlock cycles, followed by the auto-select
command. The device then enters the auto-select
mode, and the system may read at any address any
number of times, without initiating another command
sequence. The read cycles at address 04H, 08H, 0CH,
and 00H retrieves the EFST manufacturer ID. A read
cycle at address 01H retrieves the device ID. .
7.3 Programming & Erasing Operation Status
The device provides several bits to determine the
status of a programming & Erasing operation: DQ7,
DQ6, Table 6 and the following subsections
describe the functions of these bits. DQ7, and DQ6
each offer a method for determining whether a
program or erase operation is complete or in
progress.
Table 6. Write Operation Status
DQ7
(Note1)
Operation
Standard
Mode
Embedded Program Algorithm
Sector erase
Embedded Erase Algorithm
Chip erase
DQ6
Toggle
Toggle
Toggle
DQ7
0
0
Notes:
1.
DQ7 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
DQ7: Data Polling
During a programming operation, DQ7 returns the
complement of the programmed value. During an
erase operation, a “0” is produced on DQ7, with this
switching to a “1” following the operation. On
completion of a programming operation, reading the
device after the rising edge of the last – the sixth write enable ( WE ) pulse, returns the value just
programmed (“0”) on DQ7.
If OE is asserted low before the operation is
completed, the value of DQ7 many change and it may
not represent the correct value. The correct value will
be return on the next read cycle, after the system has
detected that the value has changed from its
complement to the actual value.
DQ6:Toggle BIT I
During program and erase operations, the toggle bit on
DQ6 switches between “0” and “1” on successive bus
read attempts at any address. The toggling can be
detected after the last rising edge of the write enable
___
( WE ) pulse of an erase or program command
sequence and is terminated when the operation is
completed. In the case of programming, the last write
enable pulse is the fourth; for both the sector erase and
chip erase commands, it is the sixth. Figure 15 shows
an example use of this function. Relevant signal pulse
timings are given in Figure 17: Toggle Bit timing
diagram.
Figure 14: Data polling flow chart opposite illustrates
the actual process. Relevant signal pulse timings are
given in Figure 16 : Data polling timing diagram.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
9/33
EFST
F49B002UA
7.4 More Device Operations
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =
VIL, CE = VIH or WE = VIH. To initiate a write cycle,
CE and WE must be a logical zero while OE is a
logical one.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between
its VCC and GND.
Power-Up Sequence
The device powers up in the Read Mode. In addition,
the memory contents may only be altered after
successful completion of the predefined command
sequences.
Write Pulse "Glitch" Protection
Power-Up Write Inhibit
Noise pulses of less than 15 ns (typical) on CE or
WE do not initiate a write cycle.
If WE = CE = VIL and OE = VIH during power up,
the device does not accept commands on the rising
edge of WE . The internal state machine is
automatically reset to reading array data on power-up.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
10/33
EFST
F49B002UA
8. ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . .. . . . . . . . . . . 0°C to +70°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to +6.5 V
A9 (Note 2) …. . . .. . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) .. . .. 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot
VSS to –2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure
2.
2. Minimum DC input voltage on pins A9 is -0.5 V. During voltage transitions, A9 may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 1. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to
14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
Figure 1. Maximum Negative Overshoot Waveform
20 n s
20 n s
+0.8V
-0.5V
-2.0V
20 n s
Figure 2. Maximum Positive Overshoot Waveform
20 n s
Vc c
+2.0V
Vc c
+0.5V
2.0V
20 n s
Elite Flash Storage Technology Inc.
20 n s
Publication Date : Sep. 2006
Revision: 1.4
11/33
EFST
F49B002UA
9. OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . . . . . .4.5 V to 5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Table 7. Capacitance TA = 25°C , f = 1.0 MHz
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
CIN1
Input Capacitance
VIN = 0V
6
pF
CIN2
Control Pin
Capacitance
VIN = 0V
12
pF
COUT
Output Capacitance
VOUT = 0V
12
pF
10. DC CHARACTERISTICS
Table 8. DC Characteristics TA = 0C to 70C, VCC = 4.5V to 5.5V
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS or VCC, VCC = VCC max.
-
-
10
uA
ILO
Output Leakage Current
VOUT = VSS or VCC, VCC = VCC max
-
-
10
uA
ICC1
VCC Active Read Current
CE = VIL, OE = VIH, f = 5MHz
-
-
25
mA
ICC2
VCC Active Write Current
CE = VIL ± OE = VIH
-
15
30
mA
ICC3
CMOS Standby Current
CE = VCC ± 0.3V
-
25
50
uA
ICC4
TTL Standby Current
CE = VIH
-
0.2
5
mA
VIL
Input Low Voltage(Note 1)
-
-0.3
-
0.8
V
VIH
Input High Voltage
-
2.0
-
VDD + 0.5
V
VID
Voltage for Auto-Select
and Temporary Sector
Unprotect
VCC =5.0V
11.5
-
12.5
V
VOL
Output Low Voltage
IOL = 2.1mA
-
-
0.45
V
VOH1
Output High Voltage(TTL)
IOH = 0.4mA
2.4
-
-
V
VLKO
Low VCC Lock-out Voltage
-
3.2
-
-
V
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
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EFST
F49B002UA
11. AC CHARACTERISTICS
TEST CONDITIONS
Figure 3. Test Setup
1.8KΩ
DEVICE UNDER
TEST
+3 .3V
CL
DIODE S = I N30 6 4
OR E QU IV AL EN T
1.3KΩ
CL = 1 0 0 pF In c ludi ng jig c apacit an c e
CL = 3 0pF f or F 4 9B0 02 UA
Figure 4. Input Waveforms and Measurement Levels
3.0V
0V
1.5V
1.5V
Test Poin t s
In p u t
Out pu t
A C TE S TIN G : In p u t s a r e d ri v e n a t 3 . 0 V f o r a l o g i c " 1 " a n d 0 V f o r a l o g i c " 0 "
In p u t p u l s e r i s e a n d f a l l t i m e s a r e < 5 n s .
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
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EFST
F49B002UA
11.1 Read Operation
TA = 0C to 70C, VCC = 4.5V~5.5V
Table 9. Read Operations
Conditions
-70
-90
Symbol
Description
tRC
Read Cycle Time (Note 1)
tACC
Address to Output Delay
CE = OE = VIL
70
90
ns
tCE
CE to Output Delay
OE = VIL
70
90
ns
tOE
OE to Output Delay
CE = VIL
30
35
ns
tDF
OE High to Output Float
CE = VIL
25
30
ns
(Note1)
tOEH
tOH
Min.
70
Max.
Min.
90
Max.
Unit
ns
Output Enable
Read
0
0
ns
Hold Time
Toggle and
Data Polling
10
10
ns
0
0
ns
Address to Output hold
CE = OE = VIL
Notes :
1.
2.
Not 100% tested.
tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
Figure 5. Read Timing Waveform
tRC
Addresses Stabl e
Ad dr es s
tAC C
CE
tDF
tOE
OE
tO EH
WE
tCE
tOH
Ou t pu t s
High-Z
Elite Flash Storage Technology Inc.
High-Z
Output Vali d
Publication Date : Sep. 2006
Revision: 1.4
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F49B002UA
11.2 Program/Erase Operation
Table 10. WE Controlled Program/Erase Operations( TA = 0C to 70C, VCC = 4.5V~5.5V )
Symbol
Description
-70
Min.
-90
Max.
Min.
Max.
Unit
tWC
Write Cycle Time (Note 1)
70
90
ns
tAS
Address Setup Time
0
0
ns
tAH
Address Hold Time
45
45
ns
tDS
Data Setup Time
30
30
ns
tDH
Data Hold Time
0
0
ns
tOES
Output Enable Setup Time
0
0
ns
Read Recovery Time Before
Write ( OE High to WE low)
0
0
ns
tCS
CE Setup Time
0
0
ns
tCH
CE Hold Time
0
0
ns
tWP
Write Pulse Width
35
35
ns
Write Pulse Width High
20
20
ns
tGHWL
tWPH
Notes :
1. Not 100% tested.
2. See the "Programming & Erasing Operation Performance" section for more information.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
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EFST
F49B002UA
Table 11. CE Controlled Program/Erase Operations(TA = 0C to 70C, VCC = 4.5V~5.5V)
-70
-90
Symbol
Description
tWC
Write Cycle Time (Note 1)
70
90
ns
tAS
Address Setup Time
0
0
ns
tAH
Address Hold Time
45
45
ns
tDS
Data Setup Time
35
35
ns
tDH
Data Hold Time
0
0
ns
tOES
Output Enable Setup Time
0
0
ns
tGHEL
Read Recovery Time Before Write
0
0
ns
tWS
WE Setup Time
0
0
ns
tWH
WE Hold Time
0
0
ns
tCP
CE Pulse Width
35
35
ns
tCPH
CE Pulse Width High
30
30
ns
tWHWH1
Programming Operation(note2)
10(typ.)
10(typ.)
us
tWHWH2
Sector Erase Operation (note2)
1.5(typ.)
1.5(typ.)
sec
Min.
Max.
Min.
Max.
Unit
Notes :
1. Not 100% tested.
2. See the "Programming & Erasing operation performance" section for more information.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
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EFST
F49B002UA
Figure 6. CE Controlled Program Timing Waveform
5555 for prog ram PA f or p rog ram
2AAA for erase
SA for sector erase
5555 f or chip erase
Data Pol li n g
PD
Addr es s
tWC
tAS
tAH
tWH
WE
tG HEL
OE
tCP
tWHWH1
or 2
CE
tCPH
tWS
tBUSY
tDS
tDH
Dat a
DQ7 DOUT
A0 f o r p r og r a m PD f o r p r o g r a m
30 f or sect or erase
55 for erase
10 f or ch ip erase
Notes :
1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device
2. Figure indicates the last two bus cycles of the command sequence..
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
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EFST
F49B002UA
Figure 7. Write Command Timing Waveform
VCC
Addr es s
5V
VIH
ADD Valid
VIL
tAH
tAS
VIH
WE
VIL
tOES
tWP
tWPH
tCW C
CE
VIH
VIL
tCS
OE
tCH
VIH
VIL
tDS
Dat a
VIH
VIL
Elite Flash Storage Technology Inc.
tDH
DIN
Publication Date : Sep. 2006
Revision: 1.4
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EFST
F49B002UA
Figure 8. Embedded Programming Timing Waveform
5555 for pr og ram PA f or p rog r am
SA for sector erase
2AAA for erase
5555 f or chip erase
Data Pol li n g
PD
Addr es s
tWC
tAS
tAH
tCH
CE
tGHWL
OE
tWP
tWHWH1
or 2
WE
tWPH
tCS
tB US Y
tDS
tDH
Dat a
DQ7 DOUT
A0 f o r p r og r a m PD f o r p r o g r a m
55 for erase
30 f or sect or erase
10 f or c h ip eras e
Notes :
1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device
2. Figure indicates the last two bus cycles of the command sequence..
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
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EFST
F49B002UA
Figure 9. Embedded Programming Algorithm Flowchart
Start
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data A0H Address 5555H
In c r e m e n t
address
W rite Data PD Address PA
Data Poll
from system
No
Verify W ork OK?
Ye s
No
Last address?
Ye s
Embedded Program Completed
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
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F49B002UA
12. PROGRAMMING & ERASING OPERATION PERFORMANCE
Table 12. Erase And Programming Performance (Note.1)
Parameter
Limits
Unit
Typ.(2)
Max.(3)
1.5
5
sec
Chip Erase Time
3
35
sec
Byte Programming Time
10
200
Us
Chip Programming Time
2
5
Sec
100,000
-
Cycles
Sector Erase Time
Erase/Program Cycles (1)
Notes:
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C, 5V.
3.Maximum values measured at 85°C, 4.5V.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
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F49B002UA
Figure 10. Embedded Chip Erase Timing Waveform
Er as e Co m m a n d S e qu en ce ( last t w o cycl e )
tAS
tWC
2AAA h
Addr es s
Read St at u s Dat a
VA
5 5 55 h
VA
tAH
CE
tCH
tGHWL
OE
tW HW H2
tWP
WE
tWPH
tCS
tDS tDH
55 h
Dat a
1 0h
In
Progr ess Complete
tVCS
VC C
Notes :
SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data
(see "Write Operation Status")
Elite Flash Storage Technology Inc.
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F49B002UA
Figure 11. Embedded Chip Erase Algorithm Flowchart
Start
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 80H Address 5555H
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 10H Address 5555H
Data Polling from System
No
Data = FFh?
Ye s
Embedded Chip Erease Completed
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
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EFST
F49B002UA
Figure 12. Embedded Sector Erase Timing Waveform
Er as e Co m m a n d S e qu en ce ( last t w o cycl e )
tAS
tWC
VA
SA
2AAAh
Addr es s
Read Statu s Dat a
VA
tAH
CE
tCH
tGHWL
OE
tW HW H1
tWP
WE
tWPH
tCS
tDS tDH
5 5h
Dat a
30 h
In
Progress Complete
tVCS
VCC
Notes :
SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data
(see "Programming & Erasing Operation Status")
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F49B002UA
Figure 13. Embedded Sector Erase Algorithm Flowchart
Start
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 80H Address 5555H
W rite Data AAH Address 5555H
W rite Data 55H Address 2AAAH
W rite Data 30H Address SA
Ye s
Data Poll from System
No
Data = FFh?
Embedded Sector Erease Completed
Elite Flash Storage Technology Inc.
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F49B002UA
PROGRAMMING & ERASING OPERATION STATUS
Figure 14. Data Polling Algorithm
Start
Read DQ7~DQ0
Add. = VA(1)
No
DQ7 = Data?
Yes
Pass
Notes :
1. VA =Valid address for programming.
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F49B002UA
Figure 15. Toggle Bit Algorithm
Start
Read DQ7~DQ0
Read DQ7~DQ0
Ye s
(N ote1 )
Toggle B it = D Q6
Toggle?
No
Pass
Note :
1. Read toggle bit twice to determine whether or not it is toggle.
Elite Flash Storage Technology Inc.
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F49B002UA
Figure 16. Data Polling Timings (During Embedded Algorithms)
tRC
VA
VA
Addr es s
tAC C
tCE
CE
tCH
tOE
OE
tOEH
tDF
WE
tOH
High-Z
DQ7
Complement
Complement
Tr u e
Vai l d Dat a
Stat u s Data
Tr u e
Vai l d Dat a
High-Z
DQ0~DQ6
Stat u s Data
tWHWH1
or
tWHWH2
Notes :
VA = Valid Address. Figure shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
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F49B002UA
Figure 17. Toggle Bit Timing Waveforms (During Embedded Algorithms)
tRC
Addr es s
VA
VA
VA
VA
tAC C
tCE
CE
tCH
tOE
OE
tOEH
tDF
WE
tOH
DQ6
High-Z
Vai ld
Status
tWHWH1
or
Vai ld
Status
(sec ond read )
(fi rst re ad )
Vai ld D ata
Vaild D ata
(stops tog gling)
tWHWH2
Notes :
VA = Valid Address; not required for DQ6. Figure shows first status cycle after command sequence, last status
read cycle, and array data read cycle.
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F49B002UA
Figure 18. ID Code Read Timing Waveform
VC C
5V
VID
VIH
VIL
ADD
A9
ADD
A0
VIH
VIL
t AC C
tAC C
A1
ADD
A2 ~ A8
A1 0~ A1 8
CE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
WE
tCE
VIL
tOE
OE
VIH
tDF
VIL
tOH
tOH
Dat a
DQ0~DQ7
VIH
VIL
Elite Flash Storage Technology Inc.
Data Out
Data Out
7FH
00H
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F49B002UA
12. PACKAGE DIMENSION
32-LEAD
PDIP
D
17
1
16
E1
32
L
A1
A
A2
C
E
e
B
α
B1
Dimension in inch
A
A1
A2
B
B1
C
E
E1
eA
L
e
Min
------0.015
0.149
------0.590
0.530
0.600 BSC
0.120
Dimension in mm
Norm
------------0.154
0.018 TYP
0.050 TYP
0.010
------------15.240 BSC
------0.100 TYP
Max
0.210
------0.159
Min
------0.381
3.785
------0.625
0.560
------14.986
13.462
0.150
3.048
-------
15
α
Elite Flash Storage Technology Inc.
eA
O
Norm
------------3.912
0.457 TYP
1.270 TYP
0.254
-------------
Max
5.33
------4.039
------15.875
14.224
------2.540 TYP
3.810
-------
15
O
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EFST
32-LEAD
F49B002UA
PLCC
D
D1
1
4
c
30
32
29
5
E2
E1
E3
E
E2
21
13
14
20
A1
-C-
A2
A
Seating Plane
-C-
0.020" MIN
b
e
O
b2
D3
D2
Symbol
A
A1
A2
b
b2
c
Min
3.18
1.53
0.33
0.66
0.20
1.27
e
θ
E
E1
E2
E3
D
D1
D2
D3
Dimension in mm
Norm
------------2.79 REF
-------------------
0O
14.86
13.90
6.05
12.32
11.36
4.78
0.004
D2
Max
3.55
2.41
0.54
0.82
0.36
Dimension in inch
Norm
------------0.110 REF
0.013
------0.026
------0.008
------Min
0.125
0.060
BSC
------14.99
13.97
------10.16 BSC
12.45
11.43
------7.62 BSC
0.050
O
10
15.11
14.04
6.93
0O
0.585
0.547
0.238
12.57
11.50
5.66
0.485
0.447
0.188
Elite Flash Storage Technology Inc.
Max
0.140
0.095
0.021
0.032
0.014
BSC
------0.590
0.550
------0.400 BSC
0.490
0.450
------0.300 BSC
O
10
0.595
0.553
0.273
0.495
0.453
0.223
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F49B002UA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form
or by any means without the prior permission of EFST.
The contents contained in this document are believed to be accurate at
the time of publication. EFST assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by EFST for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of EFST or
others.
Any semiconductor devices may have inherently a certain rate of
failure. To minimize risks associated with customer's application,
adequate design and operating safeguards against injury, damage, or
loss from such failure, should be provided by the customer when
making application designs.
EFST 's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Flash Storage Technology Inc.
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Revision: 1.4
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