SONY CXD1179

CXD1179Q
8-bit 35MSPS Video A/D Converter with Clamp Function
Description
The CXD1179Q is an 8-bit CMOS A/D converter
for video with synchronizing clamp function. The
adoption of 2 step-parallel method achieves ultra-low
power consumption and a maximum conversion
speed of 35MSPS.
Features
• Resolution: 8-bit ± 1/2LSB (DL)
• Maximum sampling frequency: 35MSPS
• Low power consumption: 80 mW (at 35MSPS typ.)
(reference current excluded)
• Synchronizing clamp function
• Clamp ON/OFF function
•
•
•
•
•
•
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD
7
• Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5
• Input voltage VIN
VDD + 0.5 to VSS – 0.5
(Analog)
• Input voltage VI
VDD + 0.5 to VSS – 0.5
Reference voltage self bias circuit
Input CMOS compatible
3-state TTL compatible output
Single 5V power supply
Low input capacitance: 8 pF
Reference impedance: 330 Ω (typ.)
Applications
Wide range of applications that require high-speed
A/D conversion such as TV and VCR.
Structure
Silicon gate CMOS IC
32 pin QFP (Plastic)
(Digital)
• Output voltage VO
(Digital)
• Storage temperature
Tstg
V
V
V
V
VDD + 0.5 to VSS – 0.5 V
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25
V
DVDD, DVSS
| DVSS – AVSS | 0 to 100
mV
• Reference input voltage
VRB
0 and above
V
VRT
2.7 and below
V
• Analog input VIN
1.8 Vp-p above
• Clock pulse width
Tpw1, Tpw0 13 ns (min) to 1.1 µs (max)
• Operating ambient temperature
Topr
–40 to +85
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E91Z07G86-TE
CXD1179Q
Block Diagram
DVss
28
OE 30
Reference supply
DVss 31
D0 (LSB)
25 VRBS
24 VRB
1
23 AVss
D1
2
D2
3
Lower
data
latch
Lower encoder
(4 BIT)
Lower sampling
comparator (4 BIT)
22 AVss
21 VIN
D3
4
D4
5
D5
6
D6
7
D7 (MSB)
8
Lower encoder
(4 BIT)
Lower sampling
comparator (4 BIT)
20 AVDD
19 AVDD
Upper
data
latch
Upper encoder
(4 BIT)
Upper sampling
comparator (4 BIT)
18 VRT
17 VRTS
16 AVDD
DVDD 10
TEST (DVDD) 11
CLK 12
TEST (OPEN)
Clock generator
9
15 CLP
14 TEST
(VDD or Vss)
NC 32
29
27
26
CLE
CCP
VREF
—2—
13 TEST
(VDD or Vss)
CXD1179Q
Pin Description
Pin No.
Symbol
1 to 8
D0 to D7
Equivalent circuit
Di
Description
D0 (LSB) to D7 (MSB) output
DVDD
9
TEST
9
Leave open during normal usage.
DVSS
10
DVDD
Digital +5 V
DVDD
12
CLK
Clock input
12
DVSS
DVDD
11
11, 13, 14
TEST
Fix Pin 11 to VDD, Pins 13 and 14 to
VDD or VSS during normal usage.
13
14
DVSS
—3—
CXD1179Q
Pin No.
Symbol
Equivalent circuit
Description
DVDD
15
CLP
Inputs clamp pulse to Pin 15 (CLP).
Clamps the signal voltage during Low
interval.
15
DVSS
16, 19, 20
AVDD
Analog +5 V
AVDD
17
Generates about +2.6 V when shorted
with VRT.
VRTS
17
18
AVDD
VRT
Reference voltage (top)
18
24
24
VRB
Reference voltage (bottom)
AVSS
AVDD
21
VIN
Analog input
21
AVSS
22, 23
Analog ground
AVSS
AVSS
25
Generates about +0.6 V when shorted
with VRB.
VRBS
25
—4—
CXD1179Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD
26
VREF
Clamp reference voltage input.
Clamps so that the reference voltage
and the input signal during clamp
interval are equal.
26
AVSS
AVDD
27
CCP
Integrates the clamp control voltage.
The relationship between the changes
in CCP voltage and in VIN voltage is
positive phase.
27
AVSS
28, 31
DVSS
Digital ground
DVDD
29
CLE
29
CLAMP
PULSE
DVSS
The clamp function is enabled when
CLE = Low.
The clamp function is set to off and
the converter functions as a normal
A/D converter when CLE = High.
The clamp pulse can be measured by
connecting CLE to DVDD through a
several hundred Ω resistor.
DVDD
30
OE
Data is output when OE = Low.
Pins D0 to D7 are at high impedance
when OE = High.
30
DVSS
32
NC
NC pin
—5—
CXD1179Q
Digital Output
The following table shows the relationship between analog input voltage and digital output code.
TPW1
Input signal
voltage
Step
Digital output code
MSB
LSB
VRT
:
:
:
:
VRB
0
:
127
128
:
255
1 1 1 1 1
:
1 0 0 0 0
0 1 1 1 1
:
0 0 0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
TPW0
Clock 2V
Analog input
Data output 2V
N
N+1
N–3
N–2
N+2
N+3
N–1
N
Td = 13ns
: Analog signal sampling point
Timing Chart I.
tr = 4.5ns
tf = 4.5ns
5V
90%
OE input
2.5V
10%
0V
tPZL
tPLZ
VOH
output 1
1.3V
10%
VOL (≠ DVSS)
tPHZ
tPZH
VOH (≠ DVDD)
90%
output 2
1.3V
VOL
Timing Chart II.
—6—
N+4
N+1
CXD1179Q
Electrical Characteristics
Analog characteristics
(Fc = 35MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C)
Item
Symbol
Conditions
Min.
0.5
Typ.
Max.
Unit
35
MSPS
Conversion speed
Fc
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
VIN = 0.5 to 2.5 V
fIN = 1 kHz ramp
Analog input band width
(–1 dB)
BW
Envelope
Offset voltage∗1
EOT
Potential difference to VRT
–60
–40
–20
EOB
Potential difference to VRB
+55
+75
+95
Integral non-linearity error
EL
+0.5
+1.3
–1.0
±0.3
±0.5
End point
Differential non-linearity error ED
Differential gain error
DG
Differential phase error
DP
Aperture jitter
Sampling delay
taj
tsd
Clamp offset voltage∗2
Eoc
Clamp pulse delay
tcpd
NTSC 40 IRE mod ramp
Fc = 14.3MSPS
VIN = DC,
PWS = 3 µs
MHz
25
mV
LSB
1
%
0.5
deg
30
ps
2
ns
VREF = 0.5 V
–20
0
+20
VREF = 2.5 V
–30
–10
+10
25
mV
ns
∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”.
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2LSB of the voltage when the output data changes from “11111111” to “11111110”.
∗2 Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be
generated.
—7—
CXD1179Q
DC characteristics
(Fc = 35MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C)
Item
Symbol
Supply current
IDD
Reference pin current
IREF
Analog input capacitance
CIN
Reference resistance
(VRT to VRB)
RREF
VRB1
Self-bias I
VRT1 – VRB1
Self-bias II
VRT2
Digital input voltage
Digital input current
VIH
VIL
IIH
IIL
IOL
IOZH
IOZL
Timing
Min.
Fc = 35MSPS
NTSC ramp wave input
4.5
Shorts VRB and VRBS
Shorts VRT and VRTS
VRB = AGND
Shorts VRT and VRTS
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
OE = VSS
VDD = min
OE = VDD
VDD = max
Typ.
Max.
Unit
16
22
mA
6.1
8.7
mA
pF
8
VIN = 1.5 V + 0.07 Vrms
VDD = max
IOH
Digital output current
Conditions
230
330
440
0.52
0.56
0.60
1.96
2.10
2.24
2.13
2.33
2.53
3.5
0.5
VIH = VDD
5
VIL = 0 V
5
VOH = VDD – 0.5 V –1.1
–2.5
VOL = 0.4 V
6.5
3.7
Ω
V
V
V
µA
mA
VOH = VDD
16
VOL = 0 V
16
µA
(Fc = 35MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Output data delay
TDL
With TTL 1 gate and 10 pF load
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
7
13
18
ns
Tri-state output
enable time
tPZH
tPZL
RL = 1 kΩ, CL = 15 pF
OE = 5 V → 0 V
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
5
8
14
ns
Tri-state output
disable time
tPHZ
tPLZ
RL = 1 kΩ, CL = 15 pF
OE = 0V → 5 V
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
4
6.5
11
ns
Clamp pulse width∗1
tcpw
Fc = 14MSPS, CIN = 10 µF
for NTSC wave
1.75
2.75
3.75
µs
∗1 The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75 kHz
for NTSC) for other processing systems to equal the values for NTSC.
—8—
CXD1179Q
Electrical Characteristics Measurement Circuit
Integral non-linearity error
Differential non-linearity error
Offset voltage
Tri-state output measurement circuit
}
measurement circuit
+V
Measurement
point
S2
S1: ON IF A < B
S2: ON IF B > A
DVDD
S1
RL
–V
VIN
8
DUT
CXD1179Q
“0”
DVM
To output pin
A<B A>B
COMPARATOR
A8
B8
to
to
A1
B1
A0
B0
8
BUFFER
8
CONTROLLER
}
000 · · · 00
to
111 · · · 10
Note) CL includes capacitance of the probe and others.
measurement circuit
2.5V
ERROR RATE
Fc – 1kHz
CX20202A-1
S.G.
COUNTER
H.P.F
0.5V
1
VIN CXD
1179Q
AMP
100
NTSC
TTL
8
ECL
1
10bit
D/A
2
620
2.5V
–5.2V
BURST
IAE
SIGNAL
SOURCE
8
2
40 IRE
MODULATION
VECTOR
SCOPE
CLK
0
0.5V
–40
S.G.
(CW)
SYNC
620
D.G
D.P.
TTL
FC
–5.2V
ECL
Digital output current measurement circuit
2.5V
0.5V
VDD
VRT
VIN
VRB
CLK
OE
GND
2.5V
IOL
0.5V
VOL
RL
“1”
CLK (35MHz)
Maximum operational speed
Differential gain error
Differential phase error
CL
VDD
VRT
VIN
VRB
CLK
OE
GND
+
–
—9—
IOH
VOH
+
–
CXD1179Q
Vi (1)
Vi (2)
Vi (3)
Vi (4)
Analog input
External clock
Upper comparators block
S (1)
Upper data
Lower data B
Digital output
C (2)
S (3)
MD (1)
RV (0)
H (1)
C (3)
C (1)
C (0)
RV (3)
S (3)
H (3)
C (3)
LD (1)
S (2)
LD (–2)
H (2)
C (2)
LD (0)
Out (–2)
C (4)
MD (3)
RV (2)
LD (–1)
H (0)
S (4)
MD (2)
RV (1)
S (1)
Lower data A
Lower comparators B block
S (2)
MD (0)
Lower reference voltage
Lower comparators A block
C (1)
Out (–1)
S (4)
H (4)
LD (2)
Out (0)
Out (1)
Timing Chart 3
Operation (See Block Diagram and Timing Chart 3)
1. The CXD1179Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2
lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT –
VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper
data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self
generation of VRT (Reference voltage top) and VRB (Reference voltage bottom).
—10—
CXD1179Q
2. This IC uses an offset cancel type comparator and the comparator operates synchronously with an
external clock. These modes are respectively indicated on the timing chart with S, H, C symbols. That is,
the comparator performs input sampling (auto zero) mode, input hold mode and comparison mode using
the external clock.
3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled
with the falling edge of the first clock by means of the upper comparator block and the lower comparator A
block.
The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to
the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the
second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes
1. Power supply and ground
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital
and analog power supply pins, use a ceramic capacitor of about 0.1 µF set as close as possible to the pin
to bypass to the respective grounds.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be
prevented by inserting a resistance of about 100 Ω in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to analog ground, by means of a capacitor about 0.1 µF, the stable characteristics of the
reference voltage are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that
generates VRT = about 2.6 V and VRB = about 0.6 V, is activated.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks
and with the following rising edge. The delay from the clock rising edge to the data output is about 13ns.
6. OE pin
By connecting OE to DVSS output mode is obtained. By connecting OE to DVDD high impedance is
obtained.
—11—
CXD1179Q
Application Circuit
(1) When clamp is used (self bias used)
+5V (Digital)
ACO4
0.1µ
CLOCK IN
OPEN
CLAMP PULSE IN
CK
∗ LATCH Q
16
0.01µ
+5V (Analog)
VIDEO IN
10µ
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
75Ω
0.1µ
10P
0.01µ
+5V (Analog)
25
26
VREF
20k
27
28
29
30
31
32
0.01µ
GND (Digital)
GND (Analog)
∗ The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operation.
However, slight small beat may be generated as vertical sag according to the relationship between the
sampling frequency and the clamp pulse frequency. At such time, the latch circuit is effective in this case.
—12—
CXD1179Q
(2) Digital clamp (self bias used)
+5V (Digital)
ACO4
0.1µ
CLOCK IN
CLAMP
PULSE IN
15
16
0.01µ
+5V (Analog)
VIDEO IN
10µ
14
13
12
10
11
9
OPEN
17
8
18
7
19
6
20
5
21
4
22
3
23
2
24
1
75Ω
0.1µ
10P
0.01µ
25
26
27
28
29
30
31
Latch,
Subtracter,
Comparator,
etc.
Clamp Level
setting data
32
DAC,
PWM,
etc.
GND (Digital)
GND (Analog)
(3) When clamp is not used (self bias used)
+5V (Digital)
ACO4
0.1µ
CLOCK IN
OPEN
16
0.01µ
+5V (Analog)
VIDEO IN
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
75Ω
0.1µ
10P
0.01µ
25
26
27
28
29
30
31
32
GND (Digital)
+5V (Digital)
GND (Analog)
—13—
CXD1179Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
24
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
17
16
32
9
(8.0)
25
1
+ 0.2
0.1 – 0.1
0.8
+ 0.15
0.3 – 0.1
0.24
M
+ 0.1
0.127 – 0.05
0° to 10°
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP032-P-0707
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
—14—
0.50
8