PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87946-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87946-01 has one LVPECL clock input pair. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. • 10 single ended LVCMOS outputs, 7Ω typical output impedance ,&6 • LVPECL clock input pair • PCLK, nPCLK supports the following input levels: LVPECL, CML, SSTL • Maximum input frequency: 250MHz • Output skew: 200ps (maximum) • Part-to-part skew: 500ps (typical) The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. • Multiple frequency skew: 350ps (maximum) • 3.3V input, outputs may be either 3.3V or 2.5V supply modes • 0°C to 70°C ambient operating temperature The ICS87946-01 is characterized at 3.3V core/3.3V output and 3.3V core/2.5V output. Guaranteed bank, output and partto-part skew characteristics make the ICS87946-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VDDA QA2 GND QA1 1 VDDA ÷2 QA0 0 GND ÷1 MR/nOE PCLK nPCLK QA0 - QA2 32 31 30 29 28 27 26 25 DIV_SELA 0 QB0 - QB2 1 DIV_SELB 0 QC0 - QC3 1 DIV_SELC nc 1 24 GND VDD 2 23 QB0 PCLK 3 22 VDDB nPCLK 4 21 QB1 DIV_SELA 5 20 GND DIV_SELB 6 19 QB2 DIV_SELC 7 18 VDDB GND 8 17 VDDC ICS87946-01 9 10 11 12 13 14 15 16 MR/nOE QC3 GND QC2 VDDC QC1 GND QC0 VDDC 32-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87946AY-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 2, 2002 1 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 nc Unused 2 VDD Power Description No connect. Positive supply pins. Connect to 3.3V. 3 PCLK Input 4 nPCLK Input Pulldown Non-inver ting differential LVPECL clock input. 5 DIV_SELA Input 6 DIV_SELB Input 7 DIV_SELC Input 8, 11, 15, 20, 24, 27, 31 GND Power Power supply ground. Connect to ground. 9, 13, 17 VDDC Power Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V. 10, 12, 14, 16 18, 22 QC0, QC1, QC2, QC3 VDDB QB2, QB1, QB0 VDDA QA2, QA1, QA02, Pullup Inver ting differential LVPECL clock input. Controls frequency division for Bank A outputs. Pulldown LVCMOS interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS interface levels. Bank C outputs. LVCMOS interface levels. 7Ω typical output impedance. Power Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V. Bank B outputs. LVCMOS interface levels. 19, 21, 23 Output 7Ω typical output impedance. 25, 29 Power Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V. 26, 28, Bank A outputs. LVCMOS interface levels. Output 30 7Ω typical output impedance. Master reset and output enable. Resets outputs to tristate. 32 MR/nOE Input Pulldown Enables and disables all outputs. LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Output TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CPD Power Dissipation Capacitance (per output) TBD pF ROUT Output Impedance 7 Ω VDD, *VDDx = 3.465V *NOTE: VDDx denotes VDDA, VDDB, VDDC. TABLE 3. FUNCTION TABLE MR/nOE 1 0 0 0 0 0 0 87946AY-01 DIV_SELA X 0 1 X X X X Inputs DIV_SELB X X X 0 1 X X DIV_SELC X X X X X 0 1 QA0 - QA2 Hi Z fIN/1 fIN/2 Active Active Active Active www.icst.com/products/hiperclocks.html 2 Outputs QB0 - QB2 Hi Z Active Active fIN/1 fIN/2 Active Active QC0 - QC3 Hi Z Active Active Active Active fIN/1 fIN/2 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDDx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θ JA Storage Temperature, TSTG -0.5V to VDD + 0.5V -0.5V to VDDx + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC. **IDDx denotes IDDA, IDDB, IDDC. Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 41 8 Maximum 3.465 3.465 Units V V mA mA Typical Maximum Units VDD + 0.3 0.8 V V 150 µA TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter VIH VIL VOH Input High Voltage Input Low Voltage Input DIV_SELA, DIV_SELB, High Current DIV_SELC, MR/nOE Input DIV_SELA, DIV_SELB, Low Current DIV_SELC, MR/nOE Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 IIH IIL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 µA 2.6 V 0.5 V IOZL Output Tristate Current Low TBD V IOZH Output Tristate Current High TBD V Maximum Units 150 µA 5 µA NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 7, Figure 1A, 3.3V Output Load Test Circuit. TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter IIH Input High Current Test Conditions PCLK Minimum Typical VDD = VIN = 3.465V nPCLK VDD = VIN = 3.465V PCLK VDD = 3.465V, VIN = 0V -5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 87946AY-01 www.icst.com/products/hiperclocks.html 3 1 V VDD V REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5A. AC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter fMAX Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 tpLH tpHL tsk(b) tsk(o) Test Conditions Minimum Typical Maximum Units 250 MHz f ≤ 250MHz 3.2 ns f ≤ 250MHz 3.2 ns Measured on rising edge at VDDx/2 100 ps Measured on rising edge at VDDx/2 200 ps Measured on rising edge at VDDx/2 350 ps tsk(pp) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge at VDDx/2 500 ps tR Output Rise Time; NOTE 6 20% to 80% 700 ps tF Output Fall Time; NOTE 6 20% to 80% 700 ps tsk(w) odc Output Duty Cycle 50 Output Enable Time; f = 10MHz tEN NOTE 6 Output Disable Time; f = 10MHz tDIS NOTE 6 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87946AY-01 www.icst.com/products/hiperclocks.html 4 % ns ns REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC. **IDDx denotes IDDA, IDDB, IDDC. Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 41 8 Maximum 3.465 2.625 Units V V mA mA Maximum Units VDD + 0.3 0.8 V V 150 µA TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol Parameter VIH VIL Input High Voltage Input Low Voltage DIV_SELA, DIV_SELB, Input DIV_SELC, CLK_SEL, High Current nMR/OE DIV_SELA, DIV_SELB, Input DIV_SELC, CLK_SEL, Low Current nMR/OE Output High Voltage; NOTE 1 IIH IIL VOH Test Conditions Minimum Typical 2 -0.3 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 µA 1.8 V VOL Output Low Voltage; NOTE 1 0.5 V IOZL Output Tristate Current Low TBD V IOZH Output Tristate Current High TBD V Maximum Units 150 µA 5 µA NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 7, Figure 1B, 3.3V/2.5V Output Load Test Circuit. TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter IIH Input High Current Test Conditions PCLK Minimum Typical VDD = VIN = 3.465V nPCLK VDD = VIN = 3.465V PCLK VDD = 3.465V, VIN = 0V -5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 87946AY-01 www.icst.com/products/hiperclocks.html 5 1 V VDD V REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. ICS87946-01 LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol Parameter fMAX Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 tpLH tpHL tsk(b) tsk(o) Test Conditions Minimum Typical Maximum Units 250 MHz f ≤ 250MHz 3.2 ns f ≤ 250MHz 3.2 ns Measured on rising edge at VDDx/2 100 ps Measured on rising edge at VDDx/2 200 ps Measured on rising edge at VDDx/2 350 ps tsk(pp) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge at VDDx/2 500 ps tR Output Rise Time; NOTE 6 20% to 80% 600 ps tF Output Fall Time; NOTE 6 20% to 80% 600 ps tsk(w) odc Output Duty Cycle 50 Output Enable Time; f = 10MHz tEN NOTE 6 Output Disable Time; f = 10MHz tDIS NOTE 6 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87946AY-01 www.icst.com/products/hiperclocks.html 6 % ns ns REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% SCOPE V DD VDDx Qx LVCMOS GND -1.65V±5% FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT 2.05V±5% 1.25V±5% SCOPE VDD VDDx Qx LVCMOS GND -1.25V±5% FIGURE 1B - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT 87946AY-01 www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR VDD nPCLK V Cross Points PP V CMR PCLK GND FIGURE 2 - DIFFERENTIAL INPUT LEVEL V x DD 2 Qx V DD x 2 Qy tsk(o) FIGURE 3 - OUTPUT SKEW PART 1 Qx PART 2 Qy V DD x 2 V DD x 2 tsk(pp) FIGURE 4 - PART-TO-PART SKEW 87946AY-01 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 5 - INPUT AND OUTPUT RISE AND F FALL TIME nPCLK PCLK V DDx QAx, QBx, QCx 2 t PD FIGURE 6 - PROPAGATION DELAY V x DD 2 QAx, QBx, QCx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD 87946AY-01 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87946AY-01 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87946-01 is: 1204 87946AY-01 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 87946AY-01 www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 2, 2002 PRELIMINARY ICS87946-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87946AY-01 ICS87946AY-01 32 Lead LQFP 250 per tray 0°C to 70°C ICS87946AY-01T ICS87946AY-01 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87946AY-01 www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 2, 2002