Genesys Logic, Inc. GL811USB USB 2.0 to ATA / ATAPI Bridge Controller Specification 1.3 May 10, 2002 Genesys Logic, Inc. 10F, No.11, Ln.155, Sec.3, Peishen Rd., Shenkeng, Taipei, Taiwan Tel: 886-2-2664-6655 Fax: 886-2-2664-5757 http://www.genesyslogic.com GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller Contents 1. General Description ......................................................................................... 2 2. Features ............................................................................................................ 3 3. Function Block ................................................................................................. 4 3.1 Block Diagram .............................................................................................. 4 3.2 Functional Overview ..................................................................................... 5 4. Pinning Information ......................................................................................... 7 4.1 Pin Assignment............................................................................................. 7 4.2 Pin Description ............................................................................................. 8 5. Functional Description .................................................................................. 10 5.1 ATA/ ATAPI ................................................................................................. 10 5.2 USB 2.0 ...................................................................................................... 10 6. Electrical Characteristics .............................................................................. 11 6.1 Absolute Maximum Ratings ........................................................................ 11 6.2 Temperature Conditions ............................................................................. 11 6.3 DC Characteristics...................................................................................... 11 6.4 AC Characteristics- ATA/ ATAPI.................................................................. 13 6.5 AC Characteristics- USB 2.0 ...................................................................... 33 7. Package Dimension ....................................................................................... 34 8. Revision History............................................................................................. 35 ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 1 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 1. General Description The GL811USB is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6 specification rev 1.0, the GL811USB can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811USB controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811USB can support not only plug and play but also Windows XP/ 2000/ ME default driver. The GL811USB uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (9mmX9mm) package, the GL811USB is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 2 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 2. Features Complies with Universal Serial Bus specification rev. 2.0. Complies with ATA/ATAPI-6 specification rev 1.0. Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) Operating system supported: Win XP/ 2000/ ME/ 98/ 98SE; Mac OS 9.X/ X. Supports 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. Supports 8-bit/16-bit Standard PIO mode interface. Supports 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66 / 100). Embedded USB 2.0 UTMI transceiver. Embedded 7.5 MIPS RISC CPU. ROM size: 4k words; RAM size: 128 bytes. Supports Power Down mode and USB suspend indicator. Supports USB 2.0 TEST mode features. 12MHz external clock to provide better EMI3.3V power input. 5V tolerance pad for IDE interface. Supports Wakeup ability. Available in 48-pin LQFP (9 mm * 9mm) package. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 3 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 3. Function Block 3.1 Block Diagram DMACK_ DIOR_ DIOW_ CS1_, CS0_ DA2 DA1 DA0 CLK15 CPU Control Register GPIO7 RPU 8 CONTROL FIFO CLK30 DPF 8/16-Bit IODD15-0 INTRQ CBLID_ DMARQ IORDY GPIO1 TXFIFO0 DPH SIE IDE 4 Engine RXSTS TXCTL TXFIFO1 UTMI USB2.0 LOGIC TXCVR RXFIFO0 DMH DATA 12-96MHz RXFIFO1 X10 12MHz DMF 16 RREF Clkgen X40 ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 4 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 3.2 Functional Overview 3.2.1 USB 2.0 TXCVR The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling. 3.2.2 UTMI (USB 2.0 Transceiver Macrocell Interface) Logic The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles the low level USB protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion. 3.2.3 SIE (Serial Interface Engine) The SIE contains the USB packet ID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. 3.2.4 PLL 10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in 120MHz for USB HS data processing. 40XPLL block will provide 480MHz for USB HS data transmission. 3.2.5 CLKGEN CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller, 12MHz for PIO mode, 48MHz for MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO. 3.2.6 CPU The CPU is the control center of GL811USB. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response proper data/status to USB host. 3.2.7 IDE Engine The IDE engine is extended from standard ATA / ATAPI protocol. It supports PIO mode, multiword DMA mode, and ultra DMA mode data transfers. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 5 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 3.2.8 FIFOs Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from IDE engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to IDE engine. 3.2.9 Control Registers Control Register configures GL811USB to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 6 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 4. Pinning Information DMARQ 37 IODD[0] 38 IODD[1] 39 IODD[2] 40 IODD[3] 41 DGND2 42 DVCC2 43 IODD[4] 44 IODD[5] 45 IODD[6] 46 IODD[7] DMACK_ IODD[11] 5 32 INTRQ DVCC1 6 GL811USB 31 DA1 DGND1 7 30 DA0 IODD[12] 8 48 LQFP 29 CS0_ IODD[13] 9 28 TEST IODD[14] 10 27 AGND1 IODD[15] 11 26 X1 CBLID_ 12 25 X2 AVCC1 RREF AGND0 DMH DMF DPH DPF AVCC0 RPU CS1_ ©2000-2002 Genesys Logic Inc.—All rights reserved. 24 33 23 4 22 IODD[10] 21 IORDY 20 34 19 3 18 IODD[9] 17 DIOR_ 16 35 15 2 RESET# IODD[8] 47 DIOW_ 14 36 DA2/ SK 1 13 GPIO7 48 GPIO1 4.1 Pin Assignment Page 7 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 4.2 Pin Description Pin # I/O Pad Type GPIO7 IODD [8:11] B B I/O 8(*) GPIO7 (**) tri I/O 16(*) IDE data bus 8~11 tri 6 DVCC1 P Power Digital VCC 7 DGND1 P Power Digital ground IODD [12:15] B I/O 16 IDE data bus 12~15 tri 12 CBLID_ I I/O 8 Cable select input tri 13 CS1_ O I/O 16 Chip select 1 tri 14 15 DA2 RESET# O I I/O 16 I/O 8 IDE address 2 Reset pin (***) tri 16 RPU A U20mia 3.3v output 17 AVCC0 P Power Analog VCC 18 DPF B U20mia Full speed DP 19 DPH B U20mia High speed DP 20 DMF B U20mia Full speed DM 21 DMH B U20mia High speed DM 22 AGND0 P Power Analog ground 23 RREF A U20mia 24 AVCC1 P Power Analog VCC 25 X2 B Clock Crystal output 26 X1 I Clock Crystal input, 12Mhz 27 AGND1 P Power Analog ground 28 TEST I I/O 8 TEST mode input pd 29 CS0_ O I/O 16 Chip select 0 tri 30 DA0 O I/O 16 IDE address 0 tri 31 DA1 O I/O 16 IDE address 1 tri 32 INTRQ I I/O 8 IDE interrupt input tri 33 DMACK_ O I/O 16 IDE acknowledge tri 34 IORDY I I/O 16 IDE ready pu 35 DIOR_ O I/O 16 IDE read signal tri 36 DIOW_ O I/O 16 IDE write signal tri 37 DMARQ I I/O 8 IDE request pd 1 2~5 8~11 Name ©2000-2002 Genesys Logic Inc.—All rights reserved. Description Note pu Reference resister connect (****) Page 8 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller Pin # I/O Pad Type IODD[0:3] B I/O 16 IDE data bus 0~3 42 DGND2 P Power Digital ground 43 DVCC2 P Power Digital VCC IODD[4:7] B I/O 16 IDE data bus 4~7 tri GPIO1 B I/O 8 GPIO1 pd 38~41 44~47 48 Name Description Note tri (*) The different of I/O 8 type from I/O 16 type is the typical drive current. The typical drive current of I/O 8 type is 8 mA, and for I/O pad 16 is 16 mA. (**) When operating in default mode: GPIO7 is the ATA/ ATAPI reset input, (***) When Reset pin is pulled low, the IDE bus will be in tri-state. (****) RREF must be connected with a 510 ohm resister to ground. Notation: Description O I B P A Output Input Bi-directional Power Analog Note pu pd tri Internal pull up Internal pull down Tri-state ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 9 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 5. Functional Description 5.1 ATA/ ATAPI The GL811USB complies with ATA/ATAPI-6 specification rev. 1.0. Please refer to the specifications for more information. 5.2 USB 2.0 The GL811USB complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI) specification rev. 1.01. Please refer to the specifications for more information. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 10 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol Min Max Unit DC supply voltage +3.0 +3.6 V DC input voltage -0.3 VCC + 0.3 V VI/O DC input voltage range for I/O -0.3 VCC + 0.3 V VAI/O DC input voltage for USB D+/D- pins -0.3 VCC + 0.3 V VESD Static discharge voltage 4000 VCC VI TA Description Ambient Temperature V 0 100 o C 6.2 Temperature Conditions Item Value Storage Temperature -50oC ~ 150 oC Operating Temperature 0 oC ~ 70 oC 6.3 DC Characteristics 6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V) Parameter Min Typ Max Unit Current sink @ VOL = 0.4V 7.79 10.83 14.09 mA Current output @ VOH = 2.4V (TTL high) 16.36 19.87 23.39 mA Falling slew rate at 30 pF loading capacitance 0.26 0.50 0.80 V/ns Rising slew rate at 30 pF loading capacitance 0.30 0.57 0.91 V/ns 1.64 V Input high threshold voltage Input low threshold voltage ©2000-2002 Genesys Logic Inc.—All rights reserved. 1.36 V Page 11 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller Parameter Hysteresis voltage Min Typ Max Unit - 0 - V 46 µA Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister 51K 105K 152K Ohms Pad internal pull up resister 85K 168K 251K Ohms 109 mA Supply current 6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V) Parameter Min Typ Max Unit Current sink @ VOL = 0.4V 16.20 21.90 27.68 mA Current output @ VOH = 2.4V (TTL high) 24.13 29.46 34.80 mA Falling slew rate at 30 pF loading capacitance 0.51 0.93 1.35 V/ns Rising slew rate at 30 pF loading capacitance 0.46 0.83 1.27 V/ns 2.15 V Input high threshold voltage Input low threshold voltage 0.89 Pad internal pull down resister 51K V 105K 152K Ohms 6.3.3 D+/ D- (For pad type u20mia @ VCC=3.6V) Parameter Min Typ Max Unit D+/D- static output LOW (RL of 1.5K to VCC ) 0 0.3 V D+/D- static output HIGH (RL of 15K to GND ) 2.8 3.6 V Differential input sensitivity 0.2 Single-ended receiver threshold 0.8 Transceiver capacitance V 2.0 V 20 pF Hi-Z state data line leakage -10 +10 µA Driver output resistance 28 43 Ohms ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 12 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.3.4 Switching Characteristics Parameter X1 crystal frequency Min Typ Max Unit 11.97 12 12.03 MHz X1 cycle time 83.3 ns D+/D- rise time with 50pF loading 4 20 ns D+/D- fall time with 50pF loading 4 20 ns 6.4 AC Characteristics- ATA/ ATAPI The GL811USB complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. PIO (Programmed Input/ Output) data transfer: PIO data transfers are performed by the host processor utilizing PIO register accesses to the Data register. 2. DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) Following listed the symbols and their respective definitions that are used in the timing diagram: ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 13 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller - Signal transition (asserted or negated) - Data transition (asserted or negated) - Data valid - Undefined but not necessarily released - Asserted, negated or released - Released - The “other” condition if a signal is shown with no change All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal. Test Assert Negate Assert Negate > VIH < VIL Test_ < VIL > VIH ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 14 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.1 Register transfers t0 ADDR valid (Note1) t1 t2 t9 t2i DIOR_/DIOW_ WRITE IODD(7:0) (Note2) t3 t4 t5 t6 Read IODD(7:0) (Note2) t6z IORDY (Note3.1) tA IORDY (Note3.2) tC tRD IORDY (Note3.3) tB tC Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as following: ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 15 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for tRD before asserting IORDY. 4. DMACK_ shall remain negated during a register transfer. Register transfer timing parameters Timing (ns) t0 Cycle time 2000 t1 Address valid to DIOR_/ DIOW_ setup 1000 t2 DIOR_/ DIOW_ pulse width 8-bit 300 t2i DIOR_/ DIOW_ recovery time 900 t3 DIOW_ data setup 80 t4 DIOW_ data hold 40 t5 DIOR_ data setup - t6 DIOR_ data hold - t6Z DIOR_ data tristate - t9 DIOR_/ DIOW_ to address valid hold 900 Read Data Valid to IORDY active tRD (if IORDY initially low after tA) tA IORDY Setup time - tB IORDY Pulse Width - tC IORDY assertion to release (max) - ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 16 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2 Multiword DMA data transfer Multiword DMA timing parameters Timing (ns) t0 Cycle time 120 tD DIOR_/ DIOW_ asserted pulse width 80 tE DIOR_ data access - tF DIOR_ data hold - tG DIOR_/ DIOW_ data setup 40 tH DIOW_ data hold 18 tI DMACK to DIOR_/ DIOW_ setup 18 tJ DIOR_/ DIOW_ to DMACK hold 20 tKR DIOR_ negated pulse width 36 tKW DIOW_ negated pulse width 36 tLR DIOR_ to DMARQ delay - tLW DIOW_ to DMARQ delay - tM CS(1:0) (max) valid to DIOR_/ DIOW_ 36 tN CS(1:0) hold 18 tZ DMACK_ to read data released ©2000-2002 Genesys Logic Inc.—All rights reserved. - Page 17 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.1 Initiating a Multiword DMA data burst CS0_/ CS1_ (Note) tM DMARQ (Note) DMACK_ tI tD DIOR_/DIOW_ tE Read DD(15:0) tG tF Write DD(15:0) tG tH Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 18 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.2 Sustaining a Multiword DMA data burst CS0_/ CS1_ t0 DMARQ DMACK_ tD tK DIOR_/DIOW_ tE tE Read DD(15:0) tG tF tG tG tH tG tF Write DD(15:0) ©2000-2002 Genesys Logic Inc.—All rights reserved. tH Page 19 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.3 Device terminating a Multiword DMA data burst CS0_/ CS1_ tN t0 DMARQ (Note) tL DMACK_ tK tD tJ DIOR_/DIOW_ tE tZ Read DD(15:0) tG tF Write DD(15:0) tG tH Note: To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 20 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.2.4 Host terminating a Multiword DMA data burst CS0_/ CS1_ tN t0 DMARQ (Note2) DMACK_ (Note1) tK tD tJ DIOR_/DIOW_ tE tZ Read DD(15:0) tG tF Write DD(15:0) tG tH Note: 1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst. 2.If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 21 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3 Ultra DMA data transfer 6.4.3.1 Ultra DMA data burst timing requirements Name Mode 0 (in ns) min max Mode 1 (in ns) min max Mode 2 (in ns) min max Mode 3 (in ns) min max Mode 4 (in ns) Min Comment max Typical sustained average two t2CYCTYP 240 160 120 90 60 tCYC 112 73 54 39 25 t2CYC 230 154 115 86 57 tDS 15 10 7 7 5 Data setup time at recipient tDH 5 5 5 5 5 Data hold time at recipient tDVS 70 48 30 20 6 Data valid setup time at sender tDVH 6 6 6 6 6 Data valid hold time at sender cycle time Cycle time allowing for asymmetry and clock variations Two cycle time allowing for clock variations tFS 0 230 0 200 0 170 0 130 0 120 tLI 0 150 0 150 0 150 0 100 0 100 tMLI 20 20 20 20 20 tUI 0 0 0 0 0 tAZ 10 10 10 10 20 20 20 20 20 tZAD 0 0 0 0 0 tENV 20 55 Envelope time NA STROBE to DMARDY_ time tRFS 75 70 60 60 60 Ready to final STROBE time 100 20 20 55 100 20 20 Drivers to assert or negate NA 20 70 output 20 125 20 Minimum delay time required for 30 tIORDYZ 70 output drivers to release 50 160 20 Unlimited interlock time Maximum time allowed for tSR tRP 70 Limited interlock time Interlock time with minimum 10 tZAH First STORBE time Minimum time to assert STOP or 100 20 negate DMARQ 20 tZIORDY 0 0 0 0 0 tACK 20 20 20 20 20 Maximum time before releasing IORDY Minimum time before driving STROBE Setup and hold times for DMACK_ Time from STROBE edge to tSS 50 50 50 50 50 negation of DMARQ or assertion of STOP ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 22 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.2 Initiating an Ultra DMA data-in burst DMARQ (device) tUI DMACK_ (host) tACK tENV tFS tZAD STOP (host) tACK HDMARDY_ (host) DSTROBE tFS tENV tZAD tZIORDY (device) tAZ tDVS tDVH IODD (15:0) DA0, DA1, tACK DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 23 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.3 Sustained Ultra DMA data-in burst t2CYC tCYC tCYC t2CYC DSTROBE at device tDVH tDVS tDVH tDVS tDVH IODD(15:0) at device DSTROBE at host IODD(15:0) tDH tDS tDH tDS tDH at host Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 24 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.4 Host pausing an Ultra DMA data-in burst DMARQ (device) DMACK_ (host) tRP STOP (host) HDMARDY_ tSR (host) DSTROBE tRFS (device) IODD(15:0) (device) Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY_ is negated. 2.If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 25 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.5 Device terminating an Ultra DMA data-in burst DMARQ (device) DMACK_ tMLI (host) tLI tLI tACK STOP (host) tLI tACK HDMARDY_ (host) DSTROBE tSS tIORDYZ (device) tZAH tAZ tDVS tDVH IODD(15:0) tACK DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 26 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.6 Host terminating an Ultra DMA data-in burst DMARQ (device) tLI tMLI DMACK_ (host) STOP tZAH tRP tAZ tACK (host) tACK HDMARDY_ (host) tRFS tLI tMLI tIORDYZ DSTROBE (device) tDVS tDVH IODD(15:0) tACK DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 27 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.7 Initiating an Ultra DMA data-out burst DMARQ (device) tUI DMACK_ (host) tACK tENV STOP (host) tZIORDY DDMARDY_ tENV tLI tUI (device) tACK HSTROBE (host) tDVS IODD (15:0) tDVH (host) tACK DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 28 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.8 Sustained Ultra DMA data-out burst t2CYC tCYC tCYC t2CYC HSTROBE at host tDVH tDVS tDVH tDVS tDVH IODD(15:0) at host HSTROBE at device IODD(15:0) tDH tDS tDH tDS tDH at device Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 29 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.9 Device pausing an Ultra DMA data-out burst tRP DMARQ (device) DMACK_ (host) STOP (host) DDMARDY_ tSR (device) HSTROBE tRFS (host) IODD(15:0) (host) Notes: 1.The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY_ is negated. 2.If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 30 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.10 Host terminating an Ultra DMA data-out burst tLI DMARQ (device) tMLI DMACK_ (host) tLI tSS tACK STOP (host) DDMARDY_ tLI tIORDYZ (device) tACK HSTROBE (host) tDVS tDVH IODD(15:0) (host) tACK DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 31 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.4.3.11 Device terminating an Ultra DMA data-out burst DMARQ (device) DMACK_ (host) tLI STOP tMLI tACK (host) tRP tIORDYZ DDMARDY_ (device) tRFS HSTROBE tLI tMLI tACK (host) tDVS tDVH IODD(15:0) (host) tACK DA0, DA1, DA2, CS0_, CS1_ Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 32 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 6.5 AC Characteristics- USB 2.0 The GL811USB conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 33 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 7. Package Dimension SYMBOL MIN MAX A 1.6 A1 0.05 0.15 A2 1.35 1.45 C1 0.09 0.16 D 9.00BSC D1 7.00BSC E 9.00BSC E1 7.00BSC e 0.5BSC b 0.17 0.27 L 0.45 0.75 L1 ©2000-2002 Genesys Logic Inc.—All rights reserved. 1 REF Page 34 GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller 8. Revision History Version Description Date 1.0 First draft 2001/08/31 1.1 Correct the pin assignment GPIO1/ CPIO7 for 48-pin package 2002/02/06 1.2 1.3 Electrical Characteristics data supplement, and eliminate the 100-pin LQFP package. 2002/04/12 AC Characteristics (ATA/ ATAPI) data supplement in Chapter 6. 2002/05/10 ©2000-2002 Genesys Logic Inc.—All rights reserved. Page 35