FUJITSU MB90390

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13723-6E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90390 Series
MB90394HA/F394H/F394HA/
MB90V390H/V390HA/V390HB
■ DESCRIPTION
The MB90390-series with up to five FULL-CAN* interfaces and Flash ROM is especially designed for automotive
and industrial applications. Its main feature are up to five on board CAN Interfaces, which conform to V2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash-ROM
program memory up to 512 Kbytes. An internal voltage booster removes the necessity for a second programming
voltage.
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features 6 Stepper Motor Controllers with slew rate controlled high current outputs.
Furthermore it features an 8-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate
16-bit free running timers. Up to 4 UARTs constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
MB90390 Series
■ FEATURES
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16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instruction execution time)
New 0.35 µm CMOS Process Technology
Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures
Up to five FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, flexible message buffering
(mailbox and FIFO buffering can be mixed)
Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)
EI2OS - Automatic transfer function indep.of CPU; 16 channels of intelligent I/O Services
18-bit Time-base counter
Watchdog Timer
2 full duplex UARTs; support 10.4 Kbps (USA standard )
Up to 2 full duplex UARTs (LIN/SCI)
Serial I/O : 1 channel for synchronous data transfer
Optional I2C* with 400 Kbps
A/D Converter : 15 channels analog inputs (Resolution 10 bits or 8 bits)
16-bit reload timer × 2 channels
ICU (Input capture) 16-bit × 6 channels (2 input pins are shared with OCU outputs)
OCU (Output capture) 16-bit × 8 channels (2 output pins are shared with ICU input pins)
16-bit free running timer × 2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5, OCU 4/5/6/7)
8/16-bit Programmable Pulse Generator 6 channels × 16-bit/12 channels × 8-bit
Stepping Motor Controller 6 channels with slew rate controlled high current outputs
Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
4-byte instruction execution queue
signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
Program Patch Function
Fast Interrupt processing
Low Power Consumption mode
Sleep mode
Timebase timer mode
Stop mode
CPU intermittent mode
Sound Generator
Real Time Watch Timer
Built-In Clock Modulation circuit
Programmable input levels (Automotive Hysteresis / CMOS Hysteresis, initial level is Automotive Hysteresis)
Package : 120-pin plastic LQFP
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
2
MB90390 Series
■ PRODUCT LINEUP
Part Number
Parameter
MB90F394H
MB90F394HA
MB90394HA
F2MC-16LX CPU
CPU
System clock
ROM
On-chip PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
ROM memory 384
Kbytes
RAM
Operating
voltage range
Temperature range
I C (400 Kbps)
30 Kbytes
Yes
0.35 µm CMOS with onchip
0.35 µm CMOS with
voltage regulator for inon-chip
ternal power supply +
0.35 µm CMOS with on-chip
voltage regulator for
Flash memory with
voltage regulator for internal power supply
internal
On-chip charge pump
power supply
for
programming voltage
3.5 V to 5.5 V
(4.0 V to 5.5 V: during Flash programming
and erasing,
4.5 V to 5.5 V: if A/D Converter is used)
5 V ± 10%
−40 °C to +85 °C
⎯
LQFP-120
PGA-299
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock = 24 MHz
UART (LIN/SCI)
2
External
16 Kbytes
⎯
Package
UART
(2 channels)
Boot-block
Flash memory 384
Kbytes
Hard-wired reset vector,
points to address
FFA000H
10 Kbytes
Emulator-specific
power supply*1
Technology
MB90V390HA/
MB90V390HB
MB90V390H
1 channel
1 channel
⎯
2 channels
1 channel
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 24 MHz
A/D Converter
15 input channels
10-bit or 8-bit resolution
Conversion time : Min 4.9 µs include sample time (per one channel, depends on machine
clock frequency)
16-bit Reload Timer
(2 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
(Continued)
3
MB90390 Series
Part Number
Parameter
MB90394HA
MB90F394H
MB90F394HA
MB90V390H
MB90V390HA/
MB90V390HB
Watch Timer
Directly operates with the oscillation clock
Read/Write accessible Second/Minute/Hour registers
Signals interrupts
16-bit
I/O Timer
(2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = System clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5, OCU 4/5/6/7
16-bit
Output Compare
(8 channels)
Signals an interrupt when a match with 16-bit I/O Timer
Eight 16-bit compare registers.
A pair of compare registers can be used to generate an output signal.
OCU 6/7 outputs are shared with ICU 3/5 inputs
16-bit
Input Capture
(6 channels)
Rising edge, falling edge or rising & falling edge sensitive
Six 16-bit Capture registers
Signals an interrupt upon external event
ICU 3/5 inputs are shared with OCU 6/7 outputs
Supports 8-bit and 16-bit operation modes
Twelve 8-bit reload counters
8/16-bit
Twelve 8-bit reload registers for L pulse width
Programmable Pulse Twelve 8-bit reload registers for H pulse width
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
(6 channels)
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs at fosc = 5 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
2 channels
CAN Interface
(up to 5 channels)
5 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full-bit compare/Full-bit mask/Two partial bit masks
Supports up to 1 Mbps
MB90F394H, MB90V390H, MB90V390HA :
Do not use CAN message buffer RAM and clock modulator at the same time.
Stepping Motor
Controller
(6 channels)
Four high current outputs with controlled slew rate for each channel
Synchronized two 8-bit PWM’s for each channel
External Interrupt
(8 channels)
Can be programmed edge sensitive or level sensitive
Sound Generator
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz at System clock = 16 MHz
Tone frequency : PWM frequency/2/ (reload value + 1)
(Continued)
4
MB90390 Series
(Continued)
Part Number
Parameter
MB90394HA
MB90F394H
MB90F394HA
MB90V390HA/
MB90V390HB
MB90V390H
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
Port-wise programmable as CMOS Hysteresis or automotive Hysteresis inputs (default)
Clock Modulator
Spread spectrum clock modulator for reducing electromagnetic emissions.
Frequency and Phase Modulation modes.
MB90F394H :
Do not use frequency modulation.
MB90F394H, MB90V390H, MB90V390HA :
Do not use CAN message buffer RAM and clock modulator at the same time.
Flash
Memory
⎯
Supports automatic
programming,
Embedded AlgorithmTM*2
Write/Erase/EraseSuspend/Resume
commands
A flag indicating completion of the algorithm
Number of erase cycles
: 10,000 times
Data retention time : 20
years*3
Hard-wired reset vector
available in order to
point to a fixed boot
sector in Flash Memory
Boot block configuration
Erase can be performed on each block
Block protection with
external programming
voltage
⎯
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*3 : This value comes from the technology qualification (using Arrehenius equation to translate high temperature
measurements into normalized value at +85 °C)
5
MB90390 Series
■ PIN ASSIGNMENTS
• MB90V390H
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/INT7
P26/INT6
P25/INT5
P24/INT4
P23/INT3
P22/INT2
P21/RX1
P20/TX1
P17/SGA
P16/SGO
P15/TOT0
P14/TIN0
X0
X1
VSS
VCC
P13/OUT5
P12/OUT4
P11/OUT3
P10/OUT2
P07/OUT1
P06/OUT0
P05/IN5/OUT7
P04/IN4
P03/IN3/OUT6
P02/IN2
P01/IN1
P00/IN0
P97/FRCK1/HCLK
PB7/FRCK0/HCLK
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P93/SIN3
P94/SCK3
P95/SOT3
P96/WOT
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PB0/PPG02/TX3*/AN8
PB1/PPG03/RX3*/AN9
PB2/PPG04/TX4*/AN10
PB3/PPG05/RX4*/AN11
PB4/SIN4/AN12
PB5/SCK4/AN13
PB6/SOT4/AN14
DVCC
DVSS
P70/PWM1P0
P71/PWM1M0
P72/PWM2P0
P73/PWM2M0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA
P43/SCL
P44
P45/ADTG
VCC
VSS
C
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2*
P57/PPG01/TX2*
P90
P91
P92
(FPT-120P-M21)
* : MB90V390H/HA/HB only
6
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
MB90390 Series
• MB90V390HA/MB90V390HB
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/INT7
P26/INT6
P25/INT5
P24/INT4
P23/INT3
P22/INT2
P21/RX1
P20/TX1
P17/SGA
P16/SGO
P15/TOT0
P14/TIN0
X0
X1
VSS
VCC
P13/OUT5
P12/OUT4
P11/OUT3
P10/OUT2
P07/OUT1
P06/OUT0
P05/IN5/OUT7
P04/IN4
P03/IN3/OUT6
P02/IN2
P01/IN1
P00/IN0
P97/FRCK1/HCLK
PB7/FRCK0/HCLK
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P93/SIN3
P94/SCK3
P95/SOT3
P96/WOT
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PB0/PPG02/TX3*1/AN8
1
PB1/PPG03/RX3* /AN9
PB2/PPG04/TX4*1/AN10
PB3/PPG05/RX4*1/AN11
PB4/SIN4/AN12
PB5/SCK4/AN13
PB6/SOT4/AN14
DVCC
DVSS
P70/PWM1P0
P71/PWM1M0
P72/PWM2P0
P73/PWM2M0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA
P43/SCL
P44
P45/ADTG
VCC
VSS
C
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2*1
P57/PPG01/TX2*1
P90/SIN2*2
P91/SCK2*2
P92/SOT2*2
(FPT-120P-M21)
*1 : MB90V390H/HA/HB only
*2 : MB90V390HA/HB only
7
MB90390 Series
• MB90394HA/MB90F394H/MB90F394HA
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/INT7
P26/INT6
P25/INT5
P24/INT4
P23/INT3
P22/INT2
P21/RX1
P20/TX1
P17/SGA
P16/SGO
P15/TOT0
P14/TIN0
X0
X1
VSS
VCC
P13/OUT5
P12/OUT4
P11/OUT3
P10/OUT2
P07/OUT1
P06/OUT0
P05/IN5/OUT7
P04/IN4
P03/IN3/OUT6
P02/IN2
P01/IN1
P00/IN0
P97/FRCK1/HCLK
PB7/FRCK0/HCLK
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P93/SIN3
P94/SCK3
P95/SOT3
P96/WOT
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PB0/PPG02/AN8
PB1/PPG03/AN9
PB2/PPG04/AN10
PB3/PPG05/AN11
PB4/SIN4/AN12
PB5/SCK4/AN13
PB6/SOT4/AN14
DVCC
DVSS
P70/PWM1P0
P71/PWM1M0
P72/PWM2P0
P73/PWM2M0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA*
P43/SCL*
P44
P45/ADTG
VCC
VSS
C
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00
P57/PPG01
P90
P91
P92
(FPT-120P-M21)
* : These pins are not available in MB90F394H/MB90F394HA.
8
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
MB90390 Series
■ PIN DESCRIPTION
Pin no.
Pin name
107
X1
108
X0
90
RST
93 to 95
P00 to P02
IN0 to IN2
Circuit type*
A
B
D
P03
96
IN3
P04
IN4
D
IN5
D
P06, P07,
P10 to P13
D
110
111
112
113
114
115 to 120
1
2
P14
TIN0
P15
TOT0
P16
SGO
P17
SGA
P20
TX1
P21
RX1
P22 to P27
INT2 to INT7
P30
RX0
P31
TX0
General purpose I/O
Inputs for the Input Captures 0 to 2
Input for the Input Capture 3
General purpose I/O
Input for the Input Capture 4
Input for the Input Capture 5
Output for the Output Compare 7
D
OUT0 to OUT5
109
Reset input
General purpose I/O
OUT7
99 to 104
Oscillation input
Output for the Output Compare 6
P05
98
Oscillation output
General purpose I/O
OUT6
97
Function
General purpose I/O
Outputs for the Output Compares 0 to 5
D
D
D
D
D
D
D
D
D
General purpose I/O
TIN0 input for the 16-bit Reload Timer 0
General purpose I/O
TOT0 output for the 16-bit Reload Timer 0
General purpose I/O
SGO output for the Sound Generator
General purpose I/O
SGA output for the Sound Generator
General purpose I/O
TX output for CAN Interface 1
General purpose I/O
RX input for CAN Interface 1
General purpose I/O
External interrupt inputs for INT2 to INT7
General purpose I/O
RX input for CAN Interface 0
General purpose I/O
TX output for CAN Interface 0
(Continued)
9
MB90390 Series
Pin no.
3
4
5
6
7
8
9
10
11
12
13
14
18, 19
20 to 25
Pin name
P32
TIN1
P33
TOT1
P34
SOT0
P35
SCK0
P36
SIN0
P37
SIN1
P40
SCK1
P41
SOT1
P42
SDA
P43
SCL
P44
P45
ADTG
P46, P47
INT0, INT1
P50 to P55
PPG10 to PPG15
Circuit type*
D
D
D
D
D
D
D
D
D
D
D
D
D
D
P56
26
27
PPG00
General purpose I/O
TIN1 input for the 16-bit Reload Timer 1
General purpose I/O
TOT1 output for the 16-bit Reload Timer 1
General purpose I/O
SOT output for UART 0
General purpose I/O
SCK I/O for UART 0
General purpose I/O
SIN input for UART 0
General purpose I/O
SIN input for UART 1
General purpose I/O
SCK I/O for UART 1
General purpose I/O
SOT output for UART 1
General purpose I/O
Serial data for I2C interface (except MB90F394H(A))
General purpose I/O
Serial clock for I2C interface (except MB90F394H(A))
General purpose I/O
General purpose I/O
External trigger input of the A/D Converter
General purpose I/O
External interrupt inputs for INT0 to INT1
General purpose I/O
Outputs for the Programmable Pulse Generators 10 to 15
General purpose I/O
D
Output for the Programmable Pulse Generator 0
RX2
RX input for CAN Interface 2 (only MB90V390H/HA/HB)
P57
General purpose I/O
PPG01
D
TX2
28
Function
P90
SIN2
Output for the Programmable Pulse Generator 1
TX output for CAN Interface 2 (only MB90V390H/HA/HB)
D
General purpose I/O
SIN input for UART 2 (only MB90V390HA/HB)
(Continued)
10
MB90390 Series
Pin no.
29
30
31
32
33
34
39 to 46
Pin name
P91
SCK2
P92
SOT2
P93
SIN3
P94
SCK3
P95
SOT3
P96
WOT
P60 to P67
AN0 to AN7
Circuit type*
D
D
D
D
D
D
E
PB0
48
49
50
PPG02
TX3
E
SCK input/output for UART 2 (only MB90V390HA/HB)
General purpose I/O
SOT output for UART 2 (only MB90V390HA/HB)
General purpose I/O
SIN input for UART 3 (LIN/SCI)
General purpose I/O
SCK input/output for UART 3 (LIN/SCI)
General purpose I/O
SOT output for UART 3 (LIN/SCI)
General purpose I/O
WOT output for the Watch Timer
General purpose I/O
Inputs for the A/D Converter
Output for the Programmable Pulse Generator 2
TX output for CAN Interface 3 (only MB90V390H/HA/HB)
AN8
Input for the A/D Converter
PB1
General purpose I/O
PPG03
RX3
E
Output for the Programmable Pulse Generator 3
RX input for CAN Interface 3 (only MB90V390H/HA/HB)
AN9
Input for the A/D Converter
PB2
General purpose I/O
PPG04
TX4
E
PPG05
RX4
E
Output for the Programmable Pulse Generator 5
RX input for CAN Interface 4 (only MB90V390H/HA/HB)
Input for the A/D Converter
PB4
AN12
TX output for CAN Interface 4 (only MB90V390H/HA/HB)
General purpose I/O
AN11
SIN4
Output for the Programmable Pulse Generator 4
Input for the A/D Converter
PB3
52
General purpose I/O
General purpose I/O
AN10
51
Function
General purpose I/O
E
SIN input for the Serial I/O
Input for the A/D Converter
(Continued)
11
MB90390 Series
Pin no.
Pin name
Circuit type*
PB5
53
SCK4
General purpose I/O
E
AN13
SOT4
General purpose I/O
E
AN14
PWM1P0
PWM1M0
PWM2P0
PWM2M0
General purpose I/O
F
P74 to P77
61 to 64
PWM1P1
PWM1M1
PWM2P1
PWM2M1
PWM1P2
PWM1M2
PWM2P2
PWM2M2
F
PWM1P3
PWM1M3
PWM2P3
PWM2M3
F
PWM1P4
PWM1M4
PWM2P4
PWM2M4
F
PWM1P5
PWM1M5
PWM2P5
PWM2M5
F
FRCK0
HCLK
Output for Stepping Motor Controller channel 4
General purpose I/O
F
PB7
91
Output for Stepping Motor Controller channel 3
General purpose I/O
PA4 to PA7
81 to 84
Output for Stepping Motor Controller channel 2
General purpose I/O
PA0 to PA3
77 to 80
Output for Stepping Motor Controller channel 1
General purpose I/O
P84 to P87
71 to 74
Output for Stepping Motor Controller channel 0
General purpose I/O
P80 to P83
67 to 70
SOT output for the Serial I/O
Input for the A/D Converter
P70 to P73
57 to 60
SCK input/output for the Serial I/O
Input for the A/D Converter
PB6
54
Function
Output for Stepping Motor Controller channel 5
General purpose I/O
D
FRCK0 input for the 16-bit I/O Timer 0
Oscillation Clock output
(Continued)
12
MB90390 Series
(Continued)
Pin no.
Pin name
Circuit type*
P97
92
FRCK1
Function
General purpose I/O
D
HCLK
FRCK1 input for the 16-bit I/O Timer 1
Inverted Oscillation Clock output
55
65
75
85
DVcc
⎯
Dedicated power supply pins for the high current output buffers
(Pin No. 57 to 84)
56
66
76
86
DVss
⎯
Dedicated ground pins for the high current output buffers
(Pin No. 57 to 84)
35
AVCC
⎯
Dedicated power supply pin (5 V) for the A/D converter
36
AVRH
⎯
Dedicated pos. reference voltage pin for the A/D converter
37
AVRL
⎯
Dedicated neg. reference voltage pin for the A/D converter
38
AVss
⎯
Dedicated power supply pin (0 V) for the A/D converter
88, 89
MD1, MD0
C
These are input pins used to designate the operating mode. They
should be connected directly to VCC or VSS.
87
MD2
G
This is an input pin used to designate the operating mode. It
should be connected directly to VCC or VSS.
15
105
Vcc
⎯
These are power supply (5 V) input pins
16
47
106
Vss
⎯
These are power supply (0 V) input pins
⎯
This is the power supply stabilization capacitor pin. It should be
connected to higher than or equal to 0.1 µF (MB90394HA/
MB90F394H(A)/MB90V390H)/0.22 µF (MB90V390HA/HB) ceramic capacitor.
17
C
* : Refer to “■ I/O CIRCUIT TYPE” for I/O circuit type.
13
MB90390 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation feedback resistor :
1 MΩ approx.
X1
Clock input
P-ch
N-ch
X0
A
Standby control signal
• CMOS Hysteresis input with pull-up
Resistor :
50 kΩ approx.
VCC
B
R (pull-up)
R
CMOS HYS
R
C
CMOS HYS
• CMOS output
• CMOS Hysteresis input
• Automotive Hysteresis input
VCC
P-ch
N-ch
D
R
• EVA/ROM device :
CMOS Hysteresis input
• Flash device :
CMOS input.
CMOS HYS
Note : The input characteristic may be
different for different pins/devices.
Refer to VIHS in “■ ELECTRICAL
CHARACTERISTICS 3.DC
Characteristics”
R
Automotive
HYS
(Continued)
14
MB90390 Series
(Continued)
Type
Circuit
Remarks
•
•
•
•
VCC
P-ch
N-ch
P-ch
E
Analog input
CMOS output
CMOS Hysteresis input
Automotive Hysteresis input
Analog input
Note : The input characteristic may be
different for different pins/devices.
Refer to VIHS in “■ ELECTRICAL
CHARACTERISTICS 3.DC
Characteristics”
N-ch
R
CMOS HYS
R
Automotive
HYS
• CMOS high current output
• CMOS Hysteresis input
• Automotive Hysteresis input
DVcc
P-ch
High current
N-ch
F
R
CMOS HYS
R
Automotive
HYS
R
G
R (pull-down)
CMOS HYS
• EVA/ROM device :
CMOS Hysteresis input with pulldown Resistor : 50 kΩ approx.
• Flash device :
CMOS input without pull-down.
15
MB90390 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Stabilization of supply voltage
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter if A/D Converter is unused.
• Notes on Energization
• Caution on Operations during PLL Clock Mode
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at
commercial frequencies (50/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of
fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
4. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90390 Series
X0
X1
16
MB90390 Series
5. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90390
Series
VCC
VSS
VSS
VCC
6. Pull-up/down resistors
The MB90390 Series does not support internal pull-up/down resistors. Use external components where needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
9. Connection of Unused Pins of A/D Converter if A/D Converter is unused
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V) .
11. Notes on During Operation of PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
17
MB90390 Series
■ BLOCK DIAGRAMS
• MB90394HA
X0, X1
RST
Clock
Controller
F2MC-16LX
CPU
RAM
10 Kbytes
ROM
384 Kbytes
Prescaler x 3
SCK3, SCK1, SCK0
SIN3, SIN1, SIN0
UART
3 channels
(1channel
LIN/SCI)
Prescaler
SOT4
SCK4
Serial I/O
Internal Data Bus
SOT3, SOT1, SOT0
I/O Timer 0
FRCK0
Input
Capture
6 channels
IN5 to IN0
Output
Compare
8 channels
OUT7 to OUT0
I/O Timer 1
FRCK1
8/16-bit
PPG
6 channels
PPG05 to PPG00
CAN
2 channels
SIN4
PPG15 to PPG10
RX1, RX0
TX1, TX0
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
AVcc
AVss
AN14 to AN0
AVRH
8/10-bit
A/D converter
15 channels
SMC
6 channels
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVcc
DVss
AVRL
ADTG
TIN1, TIN0
TOT1, TOT0
WOT
18
16-bit
Reload Timer
2 channels
External
Interrupt
8 channels
INT7 to INT0
Sound
Generator
SGO
I 2C
Interface
SDA
SGA
Watch
Timer
SCL
MB90390 Series
• MB90F394H/MB90F394HA
X0, X1
RST
Clock
Controller
F2MC-16LX
CPU
RAM
10 Kbytes
Flash
384 Kbytes
Prescaler x 3
SCK3, SCK1, SCK0
SIN3, SIN1, SIN0
UART
3 channels
(1channel
LIN/SCI)
Prescaler
SOT4
SCK4
Serial I/O
Internal Data Bus
SOT3, SOT1, SOT0
I/O Timer 0
FRCK0
Input
Capture
6 channels
IN5 to IN0
Output
Compare
8 channels
OUT7 to OUT0
I/O Timer 1
FRCK1
8/16-bit
PPG
6 channels
PPG05 to PPG00
CAN
2 channels
SIN4
PPG15 to PPG10
RX1, RX0
TX1, TX0
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
AVcc
AVss
AN14 to AN0
AVRH
8/10-bit
A/D converter
15 channels
SMC
6 channels
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVcc
DVss
AVRL
ADTG
TIN1, TIN0
TOT1, TOT0
16-bit
Reload Timer
2 channels
External
Interrupt
8 channels
Sound
Generator
WOT
INT7 to INT0
SGO
SGA
Watch
Timer
19
MB90390 Series
• MB90V390H
X0, X1
RST
Clock
Controller
F2MC-16LX
CPU
RAM
16 Kbytes
Prescaler x 3
SCK3,SCK1,SCK0
SIN3,SIN1,SIN0
UART
3 channels
(1 channel
LIN/SCI)
Prescaler
SOT4
SCK4
Serial I/O
SIN4
Internal Data Bus
SOT3,SOT1,SOT0
I/O Timer 0
FRCK0
Input
Capture
6 channels
IN5 to IN0
Output
Compare
8 channels
OUT7 to OUT0
I/O Timer 1
FRCK1
8/16-bit
PPG
6 channels
PPG05 to PPG00
CAN
5 channels
RX4 to RX0
PPG15 to PPG10
TX4 to TX0
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
AVCC
SMC
6 channels
AVSS
AN14 to AN0
AVRH
8/10-bit
A/D converter
15 channels
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVCC
DVSS
AVRL
ADTG
TIN1, TIN0
TOT1, TOT0
WOT
20
16-bit
Reload Timer
2 channels
External
Interrupt
8 channels
INT7 to INT0
Sound
Generator
SGO
I 2C
Interface
SDA
SGA
Watch
Timer
SCL
MB90390 Series
• MB90V390HA/MB90V390HB
X0, X1
RST
Clock
Controller
F2MC-16LX
CPU
RAM
30 Kbytes
Prescaler x 4
SCK3 to SCK0
SIN3 to SIN0
UART
4 channels
(2 channels
LIN/SCI)
Prescaler
SOT4
SCK4
Serial I/O
FRCK0
Input
Capture
6 channels
IN5 to IN0
Output
Compare
8 channels
OUT7 to OUT0
I/O Timer 1
8/16-bit
PPG
6 channels
Internal Data Bus
SOT3 to SOT0
I/O Timer 0
CAN
5 channels
SIN4
FRCK1
PPG05 to PPG00
PPG15 to PPG10
RX4 to RX0
TX4 to TX0
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
AVcc
PWM2M5 to PWM2M0
AVss
AN14 to AN0
AVRH
8/10-bit
A/D converter
15 channels
SMC
6 channels
PWM2P5 to PWM2P0
DVcc
DVss
AVRL
ADTG
TIN1, TIN0
TOT1, TOT0
WOT
16-bit
Reload Timer
2 channels
External
Interrupt
8 channels
INT7 to INT0
Sound
Generator
SGO
I 2C
Interface
SDA
SGA
Watch
Timer
SCL
21
MB90390 Series
■ MEMORY MAP
MB90394HA/
F394H(A)
FFFFFFH
MB90V390HA/HB
FFFFFFH
FFFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FE bank)
FE0000H
FDFFFF H
FD0000H
FCFFFF H
FD0000H
FCFFFF H
FC0000H
FBFFFFH
FC0000H
FBFFFFH
ROM (FB bank)
FB0000H
FA F F F F H
ROM (FD bank)
ROM (FC bank)
ROM (FD bank)
FD0000H
FCFFFF H
ROM (FB bank)
FB0000H
FA F F F F H
ROM (FA bank)
ROM (FA bank)
FA 0 0 0 0 H
F9FFFFH
FA 0 0 0 0 H
F9FFFFH
ROM (F9 bank)
ROM (F9 bank)
ROM (F9 bank)
F90000H
F8FFFFH
F90000H
F8FFFFH
ROM (F8 bank)
F80000H
8017FFH
800000H
00FFFFH
004000H
or
008000H
ROM (Image of
FF bank)
003FFFH
00FFFFH
008000H
0070FFH
004100H
ROM (F8 bank)
F80000H
RAM 6 Kbytes
ROM (Image of
FF bank)
RAM 12 Kbytes
00FFFFH
008000H
0050FFH
004100H
Periperal
003500H
003500H
0028FFH
0030FFH
0030FFH
000100H
0000BFH
000000H
RAM 12 Kbytes
RAM 12 Kbytes
000100H
000100H
Periperal
0000BFH
000000H
RAM 4 Kbytes
Periperal
003500H
RAM 10 Kbytes
ROM (Image of
FF bank)
003FFFH
003FFFH
Periperal
ROM (FC bank)
FC0000H
FBFFFFH
ROM (FB bank)
ROM (FA bank)
F90000H
ROM (FE bank)
FE0000H
FDFFFF H
FB0000H
FA F F F F H
FA 0 0 0 0 H
F9FFFFH
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFF H
MB90V390H
Periperal
0000BFH
000000H
Periperal
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32/48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H
and FF3FFFH/FF7FFFH is visible only in bank FF.
In MB90V390H/HA/HB, the image for only ROM data between FF8000H to FFFFFFH is visible in bank 00.
As for MB90F394H(A) and MB90394HA, it is possible to set the FF bank area which looks the 00 bank image
in the ROM mirror function select register (ROMM) .
22
MB90390 Series
■ I/O MAP
Address
Register
AbbreviaAccess
tion
Resource name
Initial value
00H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
05H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 Data Register
PDR7
R/W
Port 7
XXXXXXXXB
08H
Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
09H
Port 9 Data Register
PDR9
R/W
Port 9
XXXXXXXXB
0AH
Port A Data Register
PDRA
R/W
Port A
XXXXXXXXB
0BH
Port B Data Register
PDRB
R/W
Port B
XXXXXXXXB
0CH
Analog Input Enable 0
ADER0
R/W
Port 6, A/D
11111111B
0DH
Analog Input Enable 1/ ADC Select
ADER1
R/W
Port B, A/D
01111111B
0EH
Input Level Select Register
ILSR
R/W
Ports
00000000B
0FH
Input Level Select Register
ILSR
R/W
Ports
00000000B
10H
Port 0 Direction Register
DDR0
R/W
Port 0
00000000B
11H
Port 1 Direction Register
DDR1
R/W
Port 1
00000000B
12H
Port 2 Direction Register
DDR2
R/W
Port 2
00000000B
13H
Port 3 Direction Register
DDR3
R/W
Port 3
00000000B
14H
Port 4 Direction Register
DDR4
R/W
Port 4
00000000B
15H
Port 5 Direction Register
DDR5
R/W
Port 5
00000000B
16H
Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
17H
Port 7 Direction Register
DDR7
R/W
Port 7
00000000B
18H
Port 8 Direction Register
DDR8
R/W
Port 8
00000000B
19H
Port 9 Direction Register
DDR9
R/W
Port 9
00000000B
1AH
Port A Direction Register
DDRA
R/W
Port A
00000000B
1BH
Port B Direction Register
DDRB
R/W
Port B
00000000B
1CH to 1FH
Reserved
20H
Serial Mode Control 0
UMC0
R/W
21H
Status 0
USR0
R/W
22H
Input/Output Data 0
23H
Rate and Data 0
UIDR0/
UODR0
R/W
URD0
R/W
00000100B
00010000B
UART0
XXXXXXXXB
0000000XB
(Continued)
23
MB90390 Series
Address
Register
AbbreviaAccess
tion
Resource name
Initial value
24H
Serial Mode Control 1
UMC1
R/W
00000100B
25H
Status 1
USR1
R/W
00010000B
26H
Input/Output Data 1
UIDR1/
UODR1
R/W
27H
Rate and Data 1
URD1
R/W
0000000XB
XXXX0000B
28H to 2BH
UART1
XXXXXXXXB
Reserved
2CH
Serial Mode Control 4
SMCS4
R/W
2DH
Serial Mode Control 4
SMCS4
R/W
2EH
Serial Data 4
SDR4
R/W
2FH
Serial I/O Prescaler/Edge Selector 4
CDCR4
R/W
0 X 0 X 0000B
30H
External Interrupt Enable
ENIR
R/W
00000000B
31H
External Interrupt Request
EIRR
R/W
32H
External Interrupt Level
ELVR
R/W
33H
External Interrupt Level
ELVR
R/W
00000000B
34H
A/D Control Status 0
ADCS0
R/W
00000000B
35H
A/D Control Status 1
ADCS1
R/W
36H
A/D Data 0
ADCR0
R
37H
A/D Data 1
ADCR1
R/W
38H
PPG0 Operation Mode Control Register
PPGC0
R/W
39H
PPG1 Operation Mode Control Register
PPGC1
R/W
3AH
PPG0 and PPG1 Clock Select Register
PPG01
R/W
3BH
Address Detection Control Register 1
PACSR1
R/W
3CH
PPG2 Operation Mode Control Register
PPGC2
R/W
3DH
PPG3 Operation Mode Control Register
PPGC3
R/W
3EH
PPG2 and PPG3 Clock Select Register
PPG23
R/W
3FH
Clock Output Enable Register
CKOE
R/W
40H
PPG4 Operation Mode Control Register
PPGC4
R/W
41H
PPG5 Operation Mode Control Register
PPGC5
R/W
42H
PPG4 and PPG5 Clock Select Register
PPG45
R/W
43H
Serial I/O
External Interrupt
A/D Converter
00000010B
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
XXXXXXXXB
000010XXB
16-bit Programmable
Pulse
Generator 0/1
Address Match
Detection Function 1
0X000XX1B
0X000001B
000000XXB
00000000B
16-bit Programmable
Pulse
Generator 2/3
0X000XX1B
Clock Output
XXXXXX00B
16-bit Programmable
Pulse
Generator 4/5
0X000001B
000000XXB
0X000XX1B
0X000001B
000000XXB
Reserved
44H
PPG6 Operation Mode Control Register
PPGC6
R/W
45H
PPG7 Operation Mode Control Register
PPGC7
R/W
46H
PPG6 and PPG7 Clock Select Register
PPG67
R/W
16-bit Programmable
Pulse
Generator 6/7
0X000XX1B
0X000001B
000000XXB
(Continued)
24
MB90390 Series
Address
Register
47H
AbbreviaAccess
tion
Resource name
Initial value
Reserved
48H
PPG8 Operation Mode Control Register
PPGC8
R/W
49H
PPG9 Operation Mode Control Register
PPGC9
R/W
4AH
PPG8 and PPG9 Clock Select Register
PPG89
R/W
4BH
16-bit Programmable
Pulse
Generator 8/9
0X000XX1B
0X000001B
000000XXB
Reserved
4CH
PPGA Operation Mode Control Register
PPGCA
R/W
4DH
PPGB Operation Mode Control Register
PPGCB
R/W
4EH
PPGA and PPGB Clock Select Register
PPGAB
R/W
4FH
16-bit Programmable
Pulse
Generator A/B
0X000XX1B
16-bit Reload Timer
0
00000000B
0X000001B
000000XXB
Reserved
50H
Timer Control Status 0
TMCSR0
R/W
51H
Timer Control Status 0
TMCSR0
R/W
52H
Timer Control Status 1
TMCSR1
R/W
53H
Timer Control Status 1
TMCSR1
54H
Input Capture Control Status 0/1
55H
56H
XXXX0000B
00000000B
R/W
16-bit Reload Timer
1
XXXX0000B
ICS01
R/W
Input Capture 0/1
00000000B
Input Capture Control Status 2/3
ICS23
R/W
Input Capture 2/3
00000000B
Input Capture Control Status 4/5
ICS45
R/W
Input Capture 4/5
00000000B
57H
Reserved
58H
Output Compare Control Status 0
OCS0
R/W
59H
Output Compare Control Status 1
OCS1
R/W
5AH
Output Compare Control Status 2
OCS2
R/W
5BH
Output Compare Control Status 3
OCS3
R/W
5CH
Output Compare Control Status 4
OCS4
R/W
5DH
Output Compare Control Status 5
OCS5
R/W
5EH
Sound Control
SGCR
R/W
5FH
Sound Control
SGCR
R/W
60H
Watch Timer Control
WTCR
R/W
61H
Watch Timer Control
WTCR
R/W
62H
PWM Control 0
PWC0
R/W
Stepping Motor
Controller 0
00000XX0B
R/W
Stepping Motor
Controller 1
00000XX0B
R/W
Stepping Motor
Controller 2
00000XX0B
63H
64H
67H
Output Compare 2/3
Output Compare 4/5
Sound Generator
Watch Timer
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
00000000B
0XXXXXX0B
000XX000B
00000000B
Reserved
PWM Control 1
65H
66H
Output Compare 0/1
PWC1
Reserved
PWM Control 2
PWC2
Reserved
(Continued)
25
MB90390 Series
Address
68H
Register
PWM Control 3
69H
6AH
PWC3
PWM Control 4
PWC4
Initial value
R/W
Stepping Motor
Controller 3
00000XX0B
R/W
Stepping Motor
Controller 4
00000XX0B
R/W
Stepping Motor
Controller 5
00000XX0B
W
ROM Mirror
XXXXXXX1B
Reserved
PWM Control 5
PWC5
6DH
Reserved
6EH
Reserved
6FH
Resource name
Reserved
6BH
6CH
AbbreviaAccess
tion
ROM Mirror
ROMM
70H to 8FH Reserved for CAN Interface 0/1. Refer to “■ CAN CONTROLLERS”
90H to 9DH
Reserved
PACSR0
R/W
Address Match
Detection Function 0
00000000B
DIRR
R/W
Delayed Interrupt
XXXXXXX0B
Low-power Mode
LPMCR
R/W
Low Power
Controller
00011000B
Clock Selector
CKSCR
R/W
Low Power
Controller
11111100B
9EH
Address Detection Control Register 0
9FH
Delayed Interrupt/Release
A0H
A1H
A2H to A7H
Reserved
A8H
Watchdog Control
WDTC
R/W
Watchdog Timer
XXXXX111B
A9H
Time Base Timer Control
TBTC
R/W
Time Base Timer
1XX00100B
R/W
Flash Memory
000X0XX0B
AAH to ADH
AEH
Reserved
Flash Control Status
(Flash devices only. Otherwise reserved)
AFH
FMCS
Reserved
B0H
Interrupt Control Register 00
ICR00
R/W
00000111B
B1H
Interrupt Control Register 01
ICR01
R/W
00000111B
B2H
Interrupt Control Register 02
ICR02
R/W
00000111B
B3H
Interrupt Control Register 03
ICR03
R/W
00000111B
B4H
Interrupt Control Register 04
ICR04
R/W
B5H
Interrupt Control Register 05
ICR05
R/W
B6H
Interrupt Control Register 06
ICR06
R/W
00000111B
B7H
Interrupt Control Register 07
ICR07
R/W
00000111B
B8H
Interrupt Control Register 08
ICR08
R/W
00000111B
B9H
Interrupt Control Register 09
ICR09
R/W
00000111B
Interrupt Controller
00000111B
00000111B
(Continued)
26
MB90390 Series
Address
Register
AbbreviaAccess
tion
Resource name
Initial value
BAH
Interrupt Control Register 10
ICR10
R/W
00000111B
BBH
Interrupt Control Register 11
ICR11
R/W
00000111B
BCH
Interrupt Control Register 12
ICR12
R/W
BDH
Interrupt Control Register 13
ICR13
R/W
BEH
Interrupt Control Register 14
ICR14
R/W
00000111B
BFH
Interrupt Control Register 15
ICR15
R/W
00000111B
C0H to FFH
Interrupt Controller
00000111B
00000111B
Reserved
3500H
Reload L
PRLL0
R/W
3501H
Reload H
PRLH0
R/W
3502H
Reload L
PRLL1
R/W
3503H
Reload H
PRLH1
R/W
3504H
Reload L
PRLL2
R/W
3505H
Reload H
PRLH2
R/W
3506H
Reload L
PRLL3
R/W
3507H
Reload H
PRLH3
R/W
3508H
Reload L
PRLL4
R/W
3509H
Reload H
PRLH4
R/W
350AH
Reload L
PRLL5
R/W
350BH
Reload H
PRLH5
R/W
350CH
Reload L
PRLL6
R/W
350DH
Reload H
PRLH6
R/W
350EH
Reload L
PRLL7
R/W
350FH
Reload H
PRLH7
R/W
3510H
Reload L
PRLL8
R/W
3511H
Reload H
PRLH8
R/W
3512H
Reload L
PRLL9
R/W
3513H
Reload H
PRLH9
R/W
3514H
Reload L
PRLLA
R/W
3515H
Reload H
PRLHA
R/W
3516H
Reload L
PRLLB
R/W
3517H
Reload H
PRLHB
R/W
3518H
Serial Mode Register
SMR3
R/W
3519H
Serial Control Register
SCR3
R/W
351AH
Reception/Transmission Data Register
RDR3/
TDR3
R/W
XXXXXXXXB
16-bit Programmable XXXXXXXXB
Pulse
XXXXXXXXB
Generator 0/1
XXXXXXXXB
XXXXXXXXB
16-bit Programmable XXXXXXXXB
Pulse
XXXXXXXXB
Generator 2/3
XXXXXXXXB
XXXXXXXXB
16-bit Programmable XXXXXXXXB
Pulse
XXXXXXXXB
Generator 4/5
XXXXXXXXB
XXXXXXXXB
16-bit Programmable XXXXXXXXB
Pulse
XXXXXXXXB
Generator 6/7
XXXXXXXXB
XXXXXXXXB
16-bit Programmable XXXXXXXXB
Pulse
XXXXXXXXB
Generator 8/9
XXXXXXXXB
XXXXXXXXB
16-bit Programmable XXXXXXXXB
Pulse
XXXXXXXXB
Generator A/B
XXXXXXXXB
00000000B
UART3
(LIN/SCI)
00000000B
00000000B
(Continued)
27
MB90390 Series
Address
Register
351BH
Serial Status Register
351CH
Extended Communication Control Reg.
AbbreviaAccess
tion
SSR3
R/W
ECCR3
R/W
Resource name
Initial value
00001000B
000000XXB
UART3
(LIN/SCI)
351DH
Extended Status/Control Register
ESCR3
R/W
351EH
Baud Rate Register 0
BGR03
R/W
00000000B
351FH
Baud Rate Register 1
BGR13
R/W
00000000B
3520H
Input Capture 0
IPCP0
R
XXXXXXXXB
3521H
Input Capture 0
IPCP0
R
3522H
Input Capture 1
IPCP1
R
3523H
Input Capture 1
IPCP1
R
XXXXXXXXB
3524H
Input Capture 2
IPCP2
R
XXXXXXXXB
3525H
Input Capture 2
IPCP2
R
3526H
Input Capture 3
IPCP3
R
3527H
Input Capture 3
IPCP3
R
XXXXXXXXB
3528H
Input Capture 4
IPCP4
R
XXXXXXXXB
3529H
Input Capture 4
IPCP4
R
352AH
Input Capture 5
IPCP5
R
352BH
Input Capture 5
IPCP5
R
XXXXXXXXB
352CH
Timer Data 0
TCDT0
R/W
00000000B
352DH
Timer Data 0
TCDT0
R/W
352EH
Timer Control 0
TCCS0
R/W
352FH
Timer Control 0
TCCS0
R/W
0XXXXXXXB
3530H
Output Compare 0
OCCP0
R/W
XXXXXXXXB
3531H
Output Compare 0
OCCP0
R/W
3532H
Output Compare 1
OCCP1
R/W
3533H
Output Compare 1
OCCP1
R/W
XXXXXXXXB
3534H
Output Compare 2
OCCP2
R/W
XXXXXXXXB
3535H
Output Compare 2
OCCP2
R/W
3536H
Output Compare 3
OCCP3
R/W
3537H
Output Compare 3
OCCP3
R/W
XXXXXXXXB
3538H
Output Compare 4
OCCP4
R/W
XXXXXXXXB
3539H
Output Compare 4
OCCP4
R/W
353AH
Output Compare 5
OCCP5
R/W
353BH
Output Compare 5
OCCP5
R/W
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
I/O Timer 0
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
00000X00B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
28
MB90390 Series
Address
Register
AbbreviaAccess
tion
353CH
Timer Data 1
TCDT1
R/W
353DH
Timer Data 1
TCDT1
R/W
353EH
Timer Control 1
TCCS1
R/W
353FH
Timer Control 1
TCCS1
R/W
3540H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
3541H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
3542H
Timer 1/Reload 1
TMR1/
TMRLR1
R/W
3543H
Timer 1/Reload 1
TMR1/
TMRLR1
R/W
3544H ,
3545H
Resource name
Initial value
00000000B
I/O Timer 1
00000000B
00000000B
0XXXXXXXB
16-bit Reload
Timer 0
16-bit Reload
Timer 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
3546H
Frequency Data
SGFR
R/W
3547H
Amplitude Data
SGAR
R/W
3548H
Decrement Grade
SGDR
R/W
3549H
Tone Count
SGTR
R/W
XXXXXXXXB
354AH
Sub-second Data
WTBR
R/W
XXXXXXXXB
354BH
Sub-second Data
WTBR
R/W
XXXXXXXXB
354CH
Sub-second Data
WTBR
R/W
354DH
Second Data
WTSR
R/W
354EH
Minute Data
WTMR
R/W
XX000000B
354FH
Hour Data
WTHR
R/W
XXX00000B
3550H
PWM1 Compare 0
PWC10
R/W
XXXXXXXXB
3551H
PWM2 Compare 0
PWC20
R/W
3552H
PWM1 Select 0
PWS10
R/W
3553H
PWM2 Select 0
PWS20
R/W
X0000000B
3554H
PWM1 Compare 1
PWC11
R/W
XXXXXXXXB
3555H
PWM2 Compare 1
PWC21
R/W
3556H
PWM1 Select 1
PWS11
R/W
3557H
PWM2 Select 1
PWS21
R/W
X0000000B
3558H
PWM1 Compare 2
PWC12
R/W
XXXXXXXXB
3559H
PWM2 Compare 2
PWC22
R/W
355AH
PWM1 Select 2
PWS12
R/W
355BH
PWM2 Select 2
PWS22
R/W
XXXXXXXXB
Sound Generator
Watch Timer
Stepping Motor
Controller 0
Stepping Motor
Controller 1
Stepping Motor
Controller 2
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
X0000000B
(Continued)
29
MB90390 Series
Address
AbbreviaAccess
tion
Register
Resource name
Initial value
355CH
PWM1 Compare 3
PWC13
R/W
355DH
PWM2 Compare 3
PWC23
R/W
355EH
PWM1 Select 3
PWS13
R/W
355FH
PWM2 Select 3
PWS23
R/W
X0000000B
3560H
PWM1 Compare 4
PWC14
R/W
XXXXXXXXB
3561H
PWM2 Compare 4
PWC24
R/W
3562H
PWM1 Select 4
PWS14
R/W
3563H
PWM2 Select 4
PWS24
R/W
X0000000B
3564H
PWM1 Compare 5
PWC15
R/W
XXXXXXXXB
3565H
PWM2 Compare 5
PWC25
R/W
3566H
PWM1 Select 5
PWS15
R/W
3567H
PWM2 Select 5
PWS25
R/W
X0000000B
3568H
Output Compare Control Status 6
OCS6
R/W
0000XX00B
3569H
Output Compare Control Status 7
OCS7
R/W
XXX00000B
356AH
Output Compare 6
OCCP6
R/W
356BH
Output Compare 6
OCCP6
R/W
356CH
Output Compare 7
OCCP7
R/W
XXXXXXXXB
356DH
Output Compare 7
OCCP7
R/W
XXXXXXXXB
356EH
CAN Direct Mode Register
CDMR
R/W
CAN Clock Sync
XXXXXXX0B
356FH
CAN RX/TX redirect register
CANSWR
R/W
CAN 0/1/2/3
XXXX0000B
XXXXXXXXB
Stepping Motor
Controller 3
Stepping Motor
Controller 4
Stepping Motor
Controller 5
Output Compare 6/7
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
XXXXXXXXB
3570H to
Reserved for CAN Interface 2/3/4. Refer to “■ CAN CONTROLLERS”
359FH
35A0H
35A1H
35A2H
35A3H
35A4H
35A5H
35A6H
35A7H
35A8H
35A9H
I2C Bus Status Register
2
I C Bus Control Register
I2C Ten Bit Slave Address Register
I2C Ten Bit Address Mask Register
I2C Seven Bit Slave Address Register
2
I C Seven Bit Address Mask Register
2
I C Data Register
2
I C Noise Filter Configuration Register*
35AAH
35ABH
R
00000000B
IBCR
R/W
00000000B
ITBAL
R/W
00000000B
ITBAH
R/W
XXXXXX00B
ITMKL
R/W
ITMKH
R/W
ISBA
R/W
X0000000B
ISMK
R/W
01111111B
IDAR
R/W
00000000B
INFCR
R/W
XXXXXX01B
I2C Interface*4
11111111B
00XXXX11B
Reserved
2
I C Clock Control Register
35ACH to
35BFH
35C0H
2
IBSR
ICCR
R/W
I2C Interface*4
X0011111B
R/W
Clock Modulator
11111101B
Reserved
Parameter Register Low Byte
CMPRL
(Continued)
30
MB90390 Series
Address
Register
35C1H
Parameter Register High Byte
35C2H
Clock Modulator Control Register
35C3H to
35C8H
AbbreviAccess
ation
CMPRH
R/W
CMCR
R/W
Resource name
Clock Modulator
Initial value
XX000010B
00010000B
Reserved
35C9H
Input Capture Edge 0/1
ICE01
R/W
Input Capture 0/1
XXXXX0XXB
35CAH
Input Capture Edge 2/3*3
ICE23
R
Input Capture 2/3
XXXXXXXXB
35CBH
Input Capture Edge 4/5
ICE45
R/W
Input Capture 4/5
XXXXX0XXB
W
PLL
XXXX0000B
35CCH
to 35CEH
35CFH
Reserved
PLL and special configuration control resister
35D0H to
35D7H
PSCCR
Reserved
35D8H
Serial Mode Register
SMR2
R/W
00000000B
35D9H
Serial Control Register
SCR2
R/W
00000000B
35DAH
Reception/Transmission Data Register
RDR2/
TDR2
R/W
00000000B
35DBH
Serial Status Register
SSR2
R/W
35DCH
Extended Communication Control Register
ECCR2
R/W
35DDH
Extended Status/Control Register
ESCR2
R/W
00000X00B
35DEH
Baud Rate Register 0
BGR02
R/W
00000000B
35DFH
Baud Rate Register 1
BGR12
R/W
00000000B
35E0H
Detection Address Setting Register 0
(Low-order)
PADR0
R/W
XXXXXXXXB
35E1H
Detection Address Setting Register 0
(Middle-order)
PADR0
R/W
XXXXXXXXB
35E2H
Detection Address Setting Register 0
(High-order)
PADR0
R/W
35E3H
Detection Address Setting Register 1
(Low-order)
PADR1
R/W
35E4H
Detection Address Setting Register 1
(Middle-order)
PADR1
R/W
XXXXXXXXB
35E5H
Detection Address Setting Register 1
(High-order)
PADR1
R/W
XXXXXXXXB
35E6H to
35EFH
UART2*1
(LIN/SCI)
Address Match
Detection Function 0
00001000B
000000XXB
XXXXXXXXB
XXXXXXXXB
Reserved
35F0H
Detection Address Setting Register 3
(Low-order)
PADR3
R/W
35F1H
Detection Address Setting Register 3
(Middle-order)
PADR3
R/W
Address Match
Detection Function 1
XXXXXXXXB
XXXXXXXXB
(Continued)
31
MB90390 Series
(Continued)
Address
Register
AbbreviaAccess
tion
Resource name
Initial value
35F2H
Detection Address Setting Register 3
(High-order)
PADR3
R/W
XXXXXXXXB
35F3H
Detection Address Setting Register 4
(Low-order)
PADR4
R/W
XXXXXXXXB
35F4H
Detection Address Setting Register 4
(Middle-order)
PADR4
R/W
XXXXXXXXB
35F5H
Detection Address Setting Register 4
(High-order)
PADR4
R/W
Address Match
XXXXXXXXB
Detection Function 1
35F6H
Detection Address Setting Register 5
(Low-order)
PADR5
R/W
XXXXXXXXB
35F7H
Detection Address Setting Register 5
(Middle-order)
PADR5
R/W
XXXXXXXXB
35F8H
Detection Address Setting Register 5
(High-order)
PADR5
R/W
XXXXXXXXB
35F9H to
35FFH
Reserved
3600H to
37FFH
Reserved for CAN Interface 0. Refer to “■ CAN CONTROLLERS”
3800H to
39FFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
3A00H to
3BFFH
Reserved for CAN Interface 2. Refer to “■ CAN CONTROLLERS”
3C00H to
3DFFH
Reserved for CAN Interface 3. Refer to “■ CAN CONTROLLERS”
3E00H to
3FFFH
Reserved for CAN Interface 4. Refer to “■ CAN CONTROLLERS”
*1 : UART2 (LIN/SCI) is only available in MB90V390HA/HB.
*2 : I2C Noise Filter Configuration Register is only available in the devices MB90V390HA/HB, MB90394HA.
*3 : Input Capture Edge 2/3 register is different in MB90V390HA/HB, the access is “R/W” and initial value is
“XXXXX0XXB”.
*4 : I2C Interface is not available in MB90F394H(A).
32
MB90390 Series
• Explanation on read/write
R/W : Readable and writable
R : Read only
W : Write only
• Explanation on initial values
0 : Initial value is “0”.
1 : Initial value is “1”.
X : Initial value is undefined.
Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
address results in reading “X”.
33
MB90390 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for each
message buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
Address
CAN0
CAN1
CAN2
CAN3
CAN4
000070H
000080H
003570H
003580H
003590H
000071H
000081H
003571H
003581H
003591H
000072H
000082H
003572H
003582H
003592H
000073H
000083H
003573H
003583H
003593H
000074H
000084H
003574H
003584H
003594H
000075H
000085H
003575H
003585H
003595H
000076H
000086H
003576H
003586H
003596H
000077H
000087H
003577H
003587H
000078H
000088H
003578H
003588H
000079H
000089H
003579H
003589H
Register
Initial Value
Message buffer
valid register
BVALR
R/W
00000000B
00000000B
Transmit request
register
TREQR
R/W
00000000B
00000000B
Transmit cancel
register
TCANR
W
00000000B
00000000B
Transmit
003597H complete register
TCR
R/W
00000000B
00000000B
003598H Receive complete
register
003599H
RCR
R/W
00000000B
00000000B
RRTRR
R/W
00000000B
00000000B
ROVRR
R/W
00000000B
00000000B
RIER
R/W
00000000B
00000000B
00007AH 00008AH 00357AH 00358AH 00359AH
Remote request
00007BH 00008BH 00357BH 00358BH 00359BH receiving register
00007CH 00008CH 00357CH 00358CH 00359CH
00007DH 00008DH 00357DH 00358DH 00359DH
Receive overrun
register
00007EH 00008EH 00357EH 00358EH 00359EH Receive interrupt
00007FH 00008FH 00357FH 00358FH 00359FH enable register
34
AbbreviaAccess
tion
MB90390 Series
List of Control Registers (2)
Address
CAN0
CAN1
CAN2
CAN3
CAN4
003700H
003900H 003B00H 003D00H 003F00H
003701H
003901H 003B01H 003D01H 003F01H
003702H
003902H 003B02H 003D02H 003F02H
003703H
003903H 003B03H 003D03H 003F03H
003704H
003904H 003B04H 003D04H 003F04H
003705H
003905H 003B05H 003D05H 003F05H
003706H
003906H 003B06H 003D06H 003F06H
003707H
003907H 003B07H 003D07H 003F07H
003708H
003908H 003B08H 003D08H 003F08H
003709H
003909H 003B09H 003D09H 003F09H
00370AH 00390AH 003B0AH 003D0AH 003F0AH
00370BH 00390BH 003B0BH 003D0BH 003F0BH
00370CH 00390CH 003B0CH 003D0CH 003F0CH
00370DH 00390DH 003B0DH 003D0DH 003F0DH
00370EH 00390EH 003B0EH 003D0EH 003F0EH
00370FH 00390FH 003B0FH 003D0FH 003F0FH
Register
CSR
R/W, R
00XXX000B
0XXXX0X1B
Last event
indicator register
LEIR
R/W
XXXXXXXXB
000X0000B
Receive/transmit
error counter
RTEC
R
00000000B
00000000B
Bit timing
register
BTR
R/W
X1111111B
11111111B
IDE register
IDER
R/W
XXXXXXXXB
XXXXXXXXB
Transmit RTR
register
TRTRR
R/W
00000000B
00000000B
Remote frame
receive waiting
register
RFWTR
R/W
XXXXXXXXB
XXXXXXXXB
Transmit
interrupt enable
register
TIER
R/W
00000000B
00000000B
003910H 003B10H 003D10H 003F10H
003711H
003713H
003911H 003B11H 003D11H 003F11H Acceptance mask
select
003912H 003B12H 003D12H 003F12H
register
003913H 003B13H 003D13H 003F13H
003714H
003914H 003B14H 003D14H 003F14H
003715H
003716H
003915H 003B15H 003D15H 003F15H Acceptance mask
register 0
003916H 003B16H 003D16H 003F16H
003717H
003917H 003B17H 003D17H 003F17H
003718H
003918H 003B18H 003D18H 003F18H
003719H
003919H 003B19H 003D19H 003F19H Acceptance mask
register 1
00391AH 003B1AH 003D1AH 003F1AH
00371AH
00371BH 00391BH 003B1BH 003D1BH 003F1BH
Initial Value
Control status
register
003710H
003712H
AbbreviaAccess
tion
XXXXXXXXB
XXXXXXXXB
AMSR
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR0
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR1
R/W
XXXXXXXXB
XXXXXXXXB
35
MB90390 Series
List of Message Buffers (ID Registers) (1)
Address
CAN0
CAN1
CAN2
CAN3
CAN4
003600H 003800H 003A00H 003C00H 003E00H
to
to
to
to
to
00361FH 00381FH 003A1FH 003C1FH 003E1FH
003620H
003820H 003A20H 003C20H 003E20H
003621H
003821H 003A21H 003C21H 003E21H
003622H
003822H 003A22H 003C22H 003E22H
003623H
003823H 003A23H 003C23H 003E23H
003624H
003824H 003A24H 003C24H 003E24H
003625H
003825H 003A25H 003C25H 003E25H
003626H
003826H 003A26H 003C26H 003E26H
003627H
003827H 003A27H 003C27H 003E27H
003628H
003828H 003A28H 003C28H 003E28H
003629H
003829H 003A29H 003C29H 003E29H
00362AH 00382AH 003A2AH 003C2AH 003E2AH
Register
Abbreviation
Access
Initial Value
Generalpurpose RAM
⎯
R/W
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 0
IDR0
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 1
IDR1
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 2
IDR2
R/W
XXXXXXXXB
XXXXXXXXB
00362BH 00382BH 003A2BH 003C2BH 003E2BH
00362CH 00382CH 003A2CH 003C2CH 003E2CH
00362DH 00382DH 003A2DH 003C2DH 003E2DH
00362EH 00382EH 003A2EH 003C2EH 003E2EH
XXXXXXXXB
XXXXXXXXB
ID register 3
IDR3
R/W
XXXXXXXXB
XXXXXXXXB
00362FH 00382FH 003A2FH 003C2FH 003E2FH
003630H
003830H 003A30H 003C30H 003E30H
003631H
003831H 003A31H 003C31H 003E31H
003632H
003832H 003A32H 003C32H 003E32H
003633H
003833H 003A33H 003C33H 003E33H
003634H
003834H 003A34H 003C34H 003E34H
003635H
003835H 003A35H 003C35H 003E35H
003636H
003836H 003A36H 003C36H 003E36H
003637H
003837H 003A37H 003C37H 003E37H
003638H
003838H 003A38H 003C38H 003E38H
003639H
003839H 003A39H 003C39H 003E39H
00363AH 00383AH 003A3AH 003C3AH 003E3AH
XXXXXXXXB
XXXXXXXXB
ID register 4
IDR4
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 5
IDR5
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 6
IDR6
R/W
XXXXXXXXB
XXXXXXXXB
00363BH 00383BH 003A3BH 003C3BH 003E3BH
00363CH 00383CH 003A3CH 003C3CH 003E3CH
00363DH 00383DH 003A3DH 003C3DH 003E3DH
00363EH 00383EH 003A3EH 003C3EH 003E3EH
00363FH 00383FH 003A3FH 003C3FH 003E3FH
36
XXXXXXXXB
XXXXXXXXB
ID register 7
IDR7
R/W
XXXXXXXXB
XXXXXXXXB
MB90390 Series
List of Message Buffers (ID Registers) (2)
Address
CAN0
CAN1
Address
CAN2
CAN3
CAN4
003640H
003840H 003A40H 003C40H 003E40H
003641H
003841H 003A41H 003C41H 003E41H
003642H
003842H 003A42H 003C42H 003E42H
003643H
003843H 003A43H 003C43H 003E43H
003644H
003844H 003A44H 003C44H 003E44H
003645H
003845H 003A45H 003C45H 003E45H
003646H
003846H 003A46H 003C46H 003E46H
003647H
003847H 003A47H 003C47H 003E47H
003648H
003848H 003A48H 003C48H 003E48H
003649H
003849H 003A49H 003C49H 003E49H
00364AH 00384AH 003A4AH 003C4AH 003E4AH
Register
Abbreviation
Access
XXXXXXXXB
XXXXXXXXB
ID register 8
IDR8
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 9
IDR9
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 10
IDR10
R/W
XXXXXXXXB
XXXXXXXXB
00364BH 00384BH 003A4BH 003C4BH 003E4BH
00364CH 00384CH 003A4CH 003C4CH 003E4CH
00364DH 00384DH 003A4DH 003C4DH 003E4DH
00364EH 00384EH 003A4EH 003C4EH 003E4EH
XXXXXXXXB
XXXXXXXXB
ID register 11
IDR11
R/W
XXXXXXXXB
XXXXXXXXB
00364FH 00384FH 003A4FH 003C4FH 003E4FH
003650H
003850H 003A50H 003C50H 003E50H
003651H
003851H 003A51H 003C51H 003E51H
003652H
003852H 003A52H 003C52H 003E52H
003653H
003853H 003A53H 003C53H 003E53H
003654H
003854H 003A54H 003C54H 003E54H
003655H
003855H 003A55H 003C55H 003E55H
003656H
003856H 003A56H 003C56H 003E56H
003657H
003857H 003A57H 003C57H 003E57H
003658H
003858H 003A58H 003C58H 003E58H
003659H
003859H 003A59H 003C59H 003E59H
00365AH 00385AH 003A5AH 003C5AH 003E5AH
XXXXXXXXB
XXXXXXXXB
ID register 12
IDR12
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 13
IDR13
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 14
IDR14
R/W
XXXXXXXXB
XXXXXXXXB
00365BH 00385BH 003A5BH 003C5BH 003E5BH
00365CH 00385CH 003A5CH 003C5CH 003E5CH
00365DH 00385DH 003A5DH 003C5DH 003E5DH
00365EH 00385EH 003A5EH 003C5EH 003E5EH
00365FH 00385FH 003A5FH 003C5FH 003E5FH
Initial Value
XXXXXXXXB
XXXXXXXXB
ID register 15
IDR7
R/W
XXXXXXXXB
XXXXXXXXB
37
MB90390 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
CAN0
CAN1
Address
CAN2
CAN3
CAN4
003660H
003860H 003A60H 003C60H 003E60H
003661H
003861H 003A61H 003C61H 003E61H
003662H
003862H 003A62H 003C62H 003E62H
003663H
003863H 003A63H 003C63H 003E63H
003664H
003864H 003A64H 003C64H 003E64H
003665H
003865H 003A65H 003C65H 003E65H
003666H
003866H 003A66H 003C66H 003E66H
003667H
003867H 003A67H 003C67H 003E67H
003668H
003868H 003A68H 003C68H 003E68H
003669H
003869H 003A69H 003C69H 003E69H
00366AH 00386AH 003A6AH 003C6AH 003E6AH
00366BH 00386BH 003A6BH 003C6BH 003E6BH
00366CH 00386CH 003A6CH 003C6CH 003E6CH
00366DH 00386DH 003A6DH 003C6DH 003E6DH
00366EH 00386EH 003A6EH 003C6EH 003E6EH
00366FH 00386FH 003A6FH 003C6FH 003E6FH
003670H
003870H 003A70H 003C70H 003E70H
003671H
003871H 003A71H 003C71H 003E71H
003672H
003872H 003A72H 003C72H 003E72H
003673H
003873H 003A73H 003C73H 003E73H
003674H
003874H 003A74H 003C74H 003E74H
003675H
003875H 003A75H 003C75H 003E75H
003676H
003876H 003A76H 003C76H 003E76H
003677H
003877H 003A77H 003C77H 003E77H
003678H
003878H 003A78H 003C78H 003E78H
003679H
003879H 003A79H 003C79H 003E79H
00367AH 00387AH 003A7AH 003C7AH 003E7AH
00367BH 00387BH 003A7BH 003C7BH 003E7BH
00367CH 00387CH 003A7CH 003C7CH 003E7CH
00367DH 00387DH 003A7DH 003C7DH 003E7DH
00367EH 00387EH 003A7EH 003C7EH 003E7EH
00367FH 00387FH 003A7FH 003C7FH 003E7FH
38
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
XXXXXXXXB
DLC register 1
DLCR1
R/W
XXXXXXXXB
DLC register 2
DLCR2
R/W
XXXXXXXXB
DLC register 3
DLCR3
R/W
XXXXXXXXB
DLC register 4
DLCR4
R/W
XXXXXXXXB
DLC register 5
DLCR5
R/W
XXXXXXXXB
DLC register 6
DLCR6
R/W
XXXXXXXXB
DLC register 7
DLCR7
R/W
XXXXXXXXB
DLC register 8
DLCR8
R/W
XXXXXXXXB
DLC register 9
DLCR9
R/W
XXXXXXXXB
DLC register 10
DLCR10
R/W
XXXXXXXXB
DLC register 11
DLCR11
R/W
XXXXXXXXB
DLC register 12
DLCR12
R/W
XXXXXXXXB
DLC register 13
DLCR13
R/W
XXXXXXXXB
DLC register 14
DLCR14
R/W
XXXXXXXXB
DLC register 15
DLCR15
R/W
XXXXXXXXB
MB90390 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
Address
Register
Abbreviation
Access
Initial Value
003880H 003A80H 003C80H 003E80H
to
to
to
to
003887H 003A87H 003C87H 003E87H
Data register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003688H 003888H 003A88H 003C88H 003E88H
to
to
to
to
to
00368FH 00388FH 003A8FH 003C8FH 003E8FH
Data register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003690H
to
003697H
003890H 003A90H 003C90H 003E90H
to
to
to
to
003897H 003A97H 003C97H 003E97H
Data register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003698H 003898H 003A98H 003C98H 003E98H
to
to
to
to
to
00369FH 00389FH 003A9FH 003C9FH 003E9FH
Data register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
0036A0H 0038A0H 003AA0H 003CA0H 003EA0H
to
to
to
to
to
0036A7H 0038A7H 003AA7H 003CA7H 003EA7H
Data register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
0036A8H 0038A8H 003AA8H 003CA8H 003EA8H
to
to
to
to
to
0036AFH 0038AFH 003AAFH 003CAFH 003EAFH
Data register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
0036B0H 0038B0H 003AB0H 003CB0H 003EB0H
to
to
to
to
to
0036B7H 0038B7H 003AB7H 003CB7H 003EB7H
Data register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
0036B8H 0038B8H 003AB8H 003CB8H 003EB8H
to
to
to
to
to
0036BFH 0038BFH 003ABFH 003CBFH 003EBFH
Data register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
0036C0H 0038C0H 003AC0H 003CC0H 003EC0H
to
to
to
to
to
0036C7H 0038C7H 003AC7H 003CC7H 003EC7H
Data register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
0036C8H 0038C8H 003AC8H 003CC8H 003EC8H
to
to
to
to
to
0036CFH 0038CFH 003ACFH 003CCFH 003ECFH
Data register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
0036D0H 0038D0H 003AD0H 003CD0H 003ED0H
Data register 10
to
to
to
to
to
(8 bytes)
0036D7H 0038D7H 003AD7H 003CD7H 003ED7H
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
0036D8H 0038D8H 003AD8H 003CD8H 003ED8H
Data register 11
to
to
to
to
to
(8 bytes)
0036DFH 0038DFH 003ADFH 003CDFH 003EDFH
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
0036E0H 0038E0H 003AE0H 003CE0H 003EE0H
Data register 12
to
to
to
to
to
(8 bytes)
0036E7H 0038E7H 003AE7H 003CE7H 003EE7H
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
0036E8H 0038E8H 003AE8H 003CE8H 003EE8H
Data register 13
to
to
to
to
to
(8 bytes)
0036EFH 0038EFH 003AEFH 003CEFH 003EEFH
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
003680H
to
003687H
CAN1
CAN2
CAN3
CAN4
39
MB90390 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Abbreviation
Access
Initial Value
0036F0H 0038F0H 003AF0H 003CF0H 003EF0H
Data register 14
to
to
to
to
to
(8 bytes)
0036F7H 0038F7H 003AF7H 003CF7H 003EF7H
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
0036F8H 0038F8H 003AF8H 003CF8H 003EF8H
Data register 15
to
to
to
to
to
(8 bytes)
0036FFH 0038FFH 003AFFH 003CFFH 003EFFH
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
40
Address
CAN1
CAN2
CAN3
CAN4
Register
MB90390 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
EI2OS
clear
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
Reset
N/A
#08
FFFFDCH
⎯
⎯
INT9 instruction
N/A
#09
FFFFD8H
⎯
⎯
Exception
N/A
#10
FFFFD4H
⎯
⎯
Time Base Timer
N/A
#11
FFFFD0H
#12
FFFFCCH
ICR00
0000B0H
ICR01
0000B1H
ICR02
0000B2H
ICR03
0000B3H
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
External Interrupt INT0 to INT7
CAN 0 RX
N/A
#13
FFFFC8H
CAN 0 TX/NS
N/A
#14
FFFFC4H
CAN 1 RX
N/A
#15
FFFFC0H
CAN 1 TX/NS
N/A
#16
FFFFBCH
PPG 0/1 / (CAN 2 RX)
N/A
#17
FFFFB8H
PPG 2/3 / (CAN 2 TX/NS)
N/A
#18
FFFFB4H
PPG 4/5 / (CAN 3 RX)
N/A
#19
FFFFB0H
PPG 6/7 / (CAN 3 TX/NS)
N/A
#20
FFFFACH
PPG 8/9 / (CAN 4 RX)
N/A
#21
FFFFA8H
PPG A/B / (CAN 4 TX/NS)
N/A
#22
FFFFA4H
16-bit Reload Timer 0
#23
FFFFA0H
16-bit Reload Timer 1
#24
FFFF9CH
Input Capture 0/1
#25
FFFF98H
Output compare 0/1
#26
FFFF94H
Input Capture 2/3 / Output Compare 6
#27
FFFF90H
Output Compare 2/3
#28
FFFF8CH
#29
FFFF88H
Output Compare 4/5 /I C
#30
FFFF84H
A/D Converter
#31
FFFF80H
#32
FFFF7CH
#33
FFFF78H
#34
FFFF74H
UART 0 RX
#35
FFFF70H
UART 0 TX
#36
FFFF6CH
UART 1 RX
#37
FFFF68H
UART 1 TX
#38
FFFF64H
Input Capture 4/5 / Output Compare 7
2
I/O Timer 0/1 / Watch Timer
N/A
Serial I/O
Sound Generator
N/A
(Continued)
41
MB90390 Series
(Continued)
Interrupt cause
EI2OS
clear
Interrupt vector
Number
Address
(UART 2 RX) / UART 3 RX
#39
FFFF60H
(UART 2 TX) / UART 3 TX
#40
FFFF5CH
Flash Memory
N/A
#41
FFFF58H
Delayed interrupt
N/A
#42
FFFF54H
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Note : For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
EI2OS, the other interrupt should be disabled.
42
MB90390 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*2
AVRH,
AVRL
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
DVCC
VSS − 0.3
VSS + 6.0
V
VCC ≥ DVCC
Input voltage*1
VI
VSS − 0.3
VSS + 6.0
V
*3
Output voltage*1
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
−4.0
+4.0
mA
*6
Σ|ICLAMP|
⎯
40
mA
*6
IOL1
⎯
15
mA
Normal outputs*4
IOLAV1
⎯
4
mA
Normal outputs, average value
IOL2
⎯
40
mA
High current outputs*5
“L” level average output current
IOLAV2
⎯
30
mA
High current outputs, average
value
“L” level maximum overall output current
ΣIOL1
⎯
100
mA
Sum of all normal outputs
“L” level maximum overall output current
ΣIOL2
⎯
330
mA
Sum of all high current outputs
“L” level average overall output current
ΣIOLAV1
⎯
50
mA
Sum of all normal outputs,
average value
“L” level average overall output current
ΣIOLAV2
⎯
250
mA
Sum of all high current outputs,
average value
IOH1
⎯
−15
mA
Normal outputs*4
IOHAV1
⎯
−4
mA
Normal outputs, average value
IOH2
⎯
−40
mA
High current outputs*5
“H” level average output current
IOHAV2
⎯
−30
mA
High current outputs, average
value
“H” level maximum overall output current
ΣIOH1
⎯
−100
mA
Sum of all normal outputs
“H” level maximum overall output current
ΣIOH2
⎯
−330
mA
Sum of all high current outputs
“H” level average overall output current
ΣIOHAV1
⎯
−50
mA
Sum of all normal outputs,
average value
“H” level average overall output current
ΣIOHAV2
⎯
−250
mA
Sum of all high current outputs,
average value
Power consumption
PD
⎯
800
mW MB90F394H(A)/MB90394HA
Operating temperature
TA
−40
+85
°C
TSTG
−55
+150
°C
Power supply voltage*1
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum output current
“H” level maximum output current
“H” level average output current
“H” level maximum output current
Storage temperature
(Continued)
43
MB90390 Series
(Continued)
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating. For ports P70 to P77, P80 to P87 and PA0 to PA7, VI and VO should not exceed DVCC + 0.3 V.
*4 : Applicable to pins
: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P90 to P97, PB0 to PB7
*5 : Applicable to pins
: P70 to P77, P80 to P87, PA0 to PA7
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67
P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Pch
Limiting
resistance
+B input (0 V to 16 V)
Nch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
44
MB90390 Series
2. Recommended Conditions
(VSS = AVSS = DVSS = 0 V)
Parameter
Power supply voltage
Symbol
VCC,
AVCC
Value
Unit
Remarks
Min
Typ
Max
4.5
5.0
5.5
V
Under normal operation
4.0
5.0
5.5
V
Under normal operation, when not
using the A/D converter
3.5
5.0
5.5
V
Under normal operation, when not
using the A/D converter and not
programming or erasing Flash
2.0
⎯
5.5
V
Retain RAM data in stop mode
MB90F394H(A)/MB90394HA*
Smoothing capacitor
CS
0.1
⎯
1.0
µF
Operating temperature
TA
−40
⎯
+85
°C
* : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the VCC pin (pin 15) , use a bypass
capacitor that has a larger capacity than that of CS. On the other VCC pin (pin 105) , use a bypass capacitor of
about 0.1 µF.
Refer to the following figure for connection of smoothing capacitor CS.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
45
MB90390 Series
3. DC Characteristics
(TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = DVSS = 0.0 V)
Parameter
Symbol
VIHS
VIHS
Input “H”
voltage
⎯
⎯
Condition
⎯
⎯
Value
Min
0.8 VCC
0.7 VCC
Typ
⎯
⎯
Max
VCC + 0.3
VCC + 0.3
Unit
Remarks
V
Port inputs if CMOS
Hysteresis input levels
are selected (except
SIN and I2C pins of
MB90394HA)
V
MB90394HA :
SIN (UART, SIO) and
I2C input pins if CMOS
Hysteresis levels are
selected
VIHA
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Port inputs if
AUTOMOTIVE
Hysteresis input levels
are selected
VIHR
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
RST input pin (CMOS
Hysteresis)
VIHM
⎯
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD input pin
V
Port inputs if CMOS
Hysteresis input levels
are selected (except
SIN and I2C pins of
MB90394HA)
V
MB90394HA :
SIN (UART, SIO) and
I2C input pins if CMOS
Hysteresis levels are
selected
VILS
VILS
Input “L”
voltage
Output “H”
voltage
Pin
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.2 VCC
0.3 VCC
VILA
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
Port inputs if
AUTOMOTIVE
Hysteresis input levels
are selected
VILR
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
RST input pin (CMOS
Hysteresis)
VILM
⎯
⎯
VSS − 0.3
⎯
VSS + 0.3
V
MD input pin
VCC − 0.5
⎯
⎯
V
VOH1
Normal
outputs
VCC = 4.5 V,
IOH1 = −4.0 mA
(Continued)
46
MB90390 Series
(TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = DVSS = 0.0 V)
Parameter
Symbol
Pin
Condition
Value
Min
Typ
Max
Unit
DVCC = 4.5 V,
IOH2 = −40.0 mA
Output “H”
voltage
Output “L” voltage
VOH2
VOL1
High
DVCC = 4.5 V,
current
IOH2 = −30.0 mA
outputs
DVCC = 4.5 V,
IOH2 = −30.0 mA
Normal VCC = 4.5 V,
outputs IOL1 = 4.0 mA
TA = − 40 °C
DVCC − 0.5
⎯
⎯
V
Input leak current
VOL2
IIL
High
DVCC = 4.5 V,
current
IOL2 = 30.0 mA
outputs
DVCC = 4.5 V,
IOL2 = 30.0 mA
⎯
ICC
Power supply
current*
VCC
ICCS
TA = + 25 °C
TA = + 85 °C
⎯
⎯
0.4
V
DVCC = 4.5 V,
IOL2 = 40.0 mA
Output “L” voltage
Remarks
TA = − 40 °C
⎯
⎯
0.5
V
TA = + 25 °C
TA = + 85 °C
VCC = 5.5 V,
VSS < VI < VCC
−5
⎯
+5
µA
VCC = 5.0 V,
Internal frequency :
20 MHz,
At normal operation.
⎯
50
70
mA
MB90394HA/
MB90F394H(A)
VCC = 5.0 V,
Internal frequency :
24 MHz,
At normal operation.
⎯
60
85
mA
MB90394HA/
MB90F394H(A)
VCC = 5.0 V,
Internal frequency :
20 MHz,
At writing Flash
memory.
⎯
65
85
mA
MB90F394H(A)
VCC = 5.0 V,
Internal frequency :
20 MHz,
At erasing Flash
memory.
⎯
70
90
mA
MB90F394H(A)
VCC = 5.0 V,
Internal frequency :
24 MHz,
At Sleep mode.
⎯
27
36
mA
MB90394HA/
MB90F394H(A)
(Continued)
47
MB90390 Series
(Continued)
Parameter
Power supply
current*
(TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = DVSS = 0.0 V)
Symbol
Pin
Value
Remarks
Typ
Max
ICTS
VCC = 5.0 V,
Internal frequency :
2 MHz,
At Main Timebase
timer mode
⎯
0.3
0.55
mA
MB90394HA/
MB90F394H(A)
ICTSPLL6
VCC = 5.0 V,
Internal frequency :
24 MHz,
At PLL Timebase
timer mode,
external frequency
= 4 MHz
⎯
5
7
mA
MB90394HA/
MB90F394H(A)
VCC = 5.0 V,
At Stop mode,
TA = +25°C
⎯
5
30
µA
MB90394HA/
MB90F394H(A)
VCC
CIN
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS, DVCC,
DVSS,
P70 to P77,
P80 to P87,
PA0 to PA7
⎯
⎯
5
15
pF
P70 to P77,
P80 to P87,
PA0 to PA7
⎯
⎯
15
30
pF
* : The power supply current is measured with an external clock.
48
Unit
Min
ICCH
Input
capacitance
Condition
MB90390 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = DVSS = 0.0 V)
Parameter
Clock frequency
Symbol
Clock cycle time
Remarks
8
MHz
When using a crystal oscillator
or a ceramic oscillator
⎯
12
MHz
When using an external clock
125
⎯
333
ns
When using a crystal oscillator
or a ceramic oscillator
X0
83.33
⎯
333
ns
When using an external clock
PWH, PWL
X0
20
⎯
⎯
ns
Duty ratio is about 30% to
70%.
tCR, tCF
X0
⎯
⎯
5
ns
When using external clock
tCYL
Input clock pulse width
Input clock rise and fall time
Min
Typ
Max
X0, X1
3
⎯
X0
3
X0, X1
⎯
Machine clock frequency
Machine clock cycle time
Value
Unit
fC
Pin
1.5
⎯
24
MHz
Except programming or erasing Flash memory. When using clock modulation, be sure
that the maximum momentary
frequency Fmax does not exceed 24 MHz. Refer to the
Clock Modulator chapter of
the Hardware Manual.
fCP
⎯
1.5
⎯
20
MHz
When programming or erasing Flash memory. Be sure
that the maximum momentary
frequency Fmax does not exceed 20 MHz.
⎯
41.67
⎯
666
ns
Except programming or erasing Flash memory.
⎯
50
⎯
666
ns
When programming or erasing Flash memory.
tCP
• Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
49
MB90390 Series
• Guaranteed PLL operation range
Guaranteed operation range
Guaranteed PLL operation range (CS2=1)
Power supply voltage VCC (V)
5.5
Guaranteed A/D converter
operation range
4.5
3.5
Guaranteed PLL operation range (CS2=0)
1.5
4
8
20
24
Machine clock fCP (MHz)
Guaranteed operation range of MB90394HA/MB90F394H(A)
• CS2 (bit 0 in PSCCR register) = 0
Machine clock fCP (MHz)
Guaranteed oscilation frequency range
×4 (CS=011) ×3 (CS=010)
20
×2 (CS=001)
16
×1*1 (CS=000)
12
8
6
4
1.5
×1/2 (PLL off)
3
4
6
8
10
12
External clock fC (MHz)*2
• CS2 (bit 0 in PSCCR register) = 1
Guaranteed oscilation frequency range
×6 (CS=110)
×4 (CS=101)
×2 (CS=100)
Machine clock fCP (MHz)
24
16
8
6
×1/2 (PLL off)
1.5
3
4
6
8
10
12
External clock fC (MHz)*2
*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz.
*2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz
External clock frequency and Machine clock frequency
50
MB90390 Series
(2) Reset Standby Input
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = DVSS = 0.0 V)
Parameter
Symbol
Reset input
time
tRSTL
Pin
RST
Value
Unit
Remarks
Min
Max
16 tCP*1
⎯
ns
Under normal operation
Oscillation time of oscillator*2
+ 100 µs + 16 tCP*1
⎯
ns
In Stop mode
100
⎯
µs
In Time Base Timer mode
*1 : tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
• Under Normal Operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In Stop Mode
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal operation
clock
16 tCP
Oscillation time
of oscillator
+100 µs
Oscillation setting time
Instruction execution
Internal reset
51
MB90390 Series
(3) Power On Reset
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = DVSS = 0.0 V)
Parameter
Symbol
Pin
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Condition
⎯
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
Remarks
Wait time until power on
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
VSS
52
Holds RAM data
MB90390 Series
(4) UART0/1 and Serial I/O Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → Valid SIN hold time
tSHIXI
Serial clock “H” pulse width
Parameter
Condition
Value
Unit
Min
Max
SCK0, SCK1, SCK4
8 tCP
⎯
ns
SCK0, SCK1, SCK4,
SOT0, SOT1, SOT4 Internal clock
operation output
SCK0, SCK1, SCK4, pins are
SIN0, SIN1, SIN4
CL = 80 pF + 1 TTL.
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
−80
+80
ns
100
⎯
ns
60
⎯
ns
tSHSL
SCK0, SCK1, SCK4
4 tCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0, SCK1, SCK4
4 tCP
⎯
ns
SCK ↓ → SOT delay time
tSLOVE
⎯
150
ns
Valid SIN → SCK ↑
tIVSHE
60
⎯
ns
60
⎯
ns
SCK ↑ → Valid SIN hold time tSHIXE
SCK0, SCK1, SCK4, External clock
SOT0, SOT1, SOT4 operation output
SCK0, SCK1, SCK4, pins are
CL = 80 pF + 1 TTL.
SIN0, SIN1, SIN4
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
Remarks
Notes : • Above rating is the case of CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
VIH
VIL
VIL
SIN
53
MB90390 Series
• External Shift Clock Mode
tSLSH
tSHSL
VIH
SCK
VIL
tR
tF
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
VIH
VIH
VIL
VIL
SIN
54
MB90390 Series
(5) UART2/3 (LIN/SCI)
• Bit setting : ESCR2/3 : SCES = 0, ECCR2/3 : SCDE = 0
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK2/3
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → Valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
Valid SIN → SCK ↑
tIVSHE
SCK ↑ → Valid SIN hold time
tSHIXE
SCK fall time
tF
SCK rise time
tR
Condition
Value
Unit
Min
Max
5 tCP
⎯
ns
−50
+50
ns
tCP + 80
⎯
ns
0
⎯
ns
SCK2/3
3 tCP − tR
⎯
ns
SCK2/3
tCP + 10
⎯
ns
⎯
2 tCP + 60
ns
30
⎯
ns
tCP + 30
⎯
ns
⎯
10
ns
⎯
10
ns
Internal clock
SCK2/3, SOT2/3 operation output pins
SCK2/3, SIN2/3 are
CL = 80 pF + 1 TTL.
SCK2/3, SIN2/3
SCK2/3, SOT2/3 External clock
operation output pins
SCK2/3, SIN2/3
are
SCK2/3, SIN2/3 CL = 80 pF + 1 TTL.
SCK2/3
SCK2/3
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
VIH
VIL
VIL
SIN
55
MB90390 Series
• External Shift Clock Mode
tSLSH
tSHSL
VIH
SCK
VIL
tR
tF
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
VIH
VIH
VIL
VIL
SIN
• Bit setting : ESCR2/3 : SCES = 1, ECCR2/3 : SCDE = 0
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
Valid SIN → SCK↓
tIVSLI
SCK ↓ → Valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↑ → SOT delay time
tSHOVE
Valid SIN → SCK↓
tIVSLE
SCK↓ →Valid SIN hold time
tSLIXE
5 tCP
⎯
ns
−50
+50
ns
tCP+80
⎯
ns
0
⎯
ns
SCK2/3
3 tCP−tR
⎯
ns
SCK2/3
tCP+10
⎯
ns
⎯
2 tCP+60
ns
30
⎯
ns
tCP+30
⎯
ns
SCK2/3
Internal clock
SCK2/3, SOT2/3 operation output
SCK2/3, SIN2/3 pins are
CL = 80 pF + 1 TTL
SCK2/3, SIN2/3
SCK2/3, SOT2/3 External clock
operation output
SCK2/3, SIN2/3
pins are
SCK2/3, SIN2/3 CL = 80 pF + 1 TTL
SCK fall time
tF
SCK2/3
⎯
10
ns
SCK rise time
tR
SCK2/3
⎯
10
ns
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
56
MB90390 Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
VIH
VIH
VIL
VIL
SIN
• External Shift Clock Mode
tSHSL
tSLSH
VIH
SCK
tSHOVE
tF
VIL
tR
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
VIH
VIH
VIL
VIL
SIN
57
MB90390 Series
• Bit setting : ESCR2/3 : SCES = 0, ECCR2/3 : SCDE = 1
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Parameter
Serial clock cycle time
SCK ↑ → SOT delay
time
Valid SIN → SCK↓
SCK ↓ → Valid SIN hold
time
SOT → SCK ↓ delay
time
Symbol
Pin
tSCYC
SCK2/3
tSHOVI
SCK2/3,
SOT2/3
tIVSLI
tSLIXI
tSOVLI
Value
Condition
Remarks
Max
5 tCP
⎯
ns
−50
+50
ns
MB90394HA,
MB90V390HA/HB
tCP − 60
tSCYC/2 +
70 − tCP
ns
MB90F394H(A),
MB90V390H
tCP + 80
⎯
ns
MB90394HA,
MB90V390HA/HB
⎯
ns
MB90F394H(A),
MB90V390H
⎯
ns
MB90394HA,
MB90V390HA/HB
⎯
ns
MB90F394H(A),
MB90V390H
3 tCP − 70
⎯
ns
MB90394HA,
MB90V390HA/HB
tCP − 60
⎯
ns
MB90F394H(A),
MB90V390H
SCK2/3,
SIN2/3 Internal clock
operation output
100 − tCP
pins are
CL = 80 pF + 1 TTL
0
SCK2/3,
SIN2/3
tSCYC/2
SCK2/3,
SOT2/3
Unit
Min
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
2.4 V
0.8 V
0.8 V
SOT
tIVSLI
tSLIXI
VIH
VIH
VIL
VIL
SIN
58
MB90390 Series
• Bit setting : ESCR2/3 : SCES = 1, ECCR2/3 : SCDE = 1
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Parameter
Serial clock cycle time
SCK ↓ → SOT delay
time
Valid SIN → SCK↓
SCK ↑ → Valid SIN hold
time
SOT → SCK ↑ delay
time
Symbol
Pin
tSCYC
SCK2/3
tSLOVI
SCK2/3,
SOT2/3
tIVSHI
tSHIXI
tSOVHI
Value
Condition
Remarks
Max
5 tCP
⎯
ns
−50
+50
ns
MB90394HA,
MB90V390HA/HB
tCP − 60
tSCYC/2 +
70 − tCP
ns
MB90F394H(A),
MB90V390H
tCP + 80
⎯
ns
MB90394HA,
MB90V390HA/HB
⎯
ns
MB90F394H(A),
MB90V390H
⎯
ns
MB90394HA,
MB90V390HA/HB
⎯
ns
MB90F394H(A),
MB90V390H
3tCP − 70
⎯
ns
MB90394HA,
MB90V390HA/HB
tCP − 60
⎯
ns
MB90F394H(A),
MB90V390H
SCK2/3,
SIN2/3 Internal clock
operation output
100 − tCP
pins are
CL = 80 pF + 1 TTL
0
SCK2/3,
SIN2/3
tSCYC/2
SCK2/3,
SOT2/3
Unit
Min
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSOVHI
tSLOVI
2.4 V
2.4 V
0.8 V
0.8 V
SOT
tIVSHI
tSHIXI
VIH
VIH
VIL
VIL
SIN
59
MB90390 Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Pin
tTIWH
TIN0, TIN1
tTIWL
IN0 to IN5
Input pulse width
Value
Condition
⎯
Min
Max
4 tCP
⎯
Unit
Remarks
ns
Note : tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Timer Input Timing
VIH
VIH
VIL
VIL
tTIWH
tTIWL
(7) Trigger Input Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Pin
Condition
tTRGH
tTRGL
INT0 to INT7
ADTG
Input pulse width
Value
Unit
Min
Max
⎯
200
⎯
ns
⎯
tCP + 200
⎯
ns
Remarks
Note : tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Trigger Input Timing
VIH
VIH
VIL
tTRGH
VIL
tTRGL
(8) Slew Rate High Current Outputs
(TA = −40 °C to +85 °C, VCC = DVCC = 3.5 V to 5.5 V, VSS = DVSS = 0 V)
Parameter
Symbol
Pin
Condition
Output Rise/Fall time
tR2
tF2
P70 to P77,
P80 to P87,
PA0 to PA7
⎯
Value
Min
Typ
Max
15
⎯
⎯
Unit
ns
• Slew Rate Output Timing
VH
VH
VL
VL
VH = VOL2 + 0.9 × (VOH2 − VOL2)
VL = VOL2 + 0.1 × (VOH2 − VOL2)
tR2
60
tF2
Remarks
MB90390 Series
(9) I2C Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
µs
Data set-up time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
⎯
100
⎯
ns
Set-up time for STOP condition
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
µs
tBUS
4.7
⎯
1.3
⎯
µs
SCL clock frequency
Hold time (repeated) START condition
SDA ↓ → SCL ↓
Bus free time between a STOP and START
condition
R = 1.3 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tSUDAT
tLOW
tBUS
tHDSTA
SCL
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
61
MB90390 Series
5. A/D Converter
(TA = −40 °C to +85 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Resolution
⎯
Conversion error
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3.0
LSB
Nonlinearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential nonlinearity
error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero reading voltage
VOT
AN0 to AN14 AVRL − 1.5
AVRL + 0.5
AVRL + 2.5
LSB
Full scale reading
voltage
VFST
AN0 to AN14 AVRH − 3.5
AVRH − 1.5
AVRH + 0.5 LSB
Compare time
Sampling time
⎯
⎯
⎯
⎯
3.3
⎯
16500
µs
⎯
3.3 (= 66 tCP)
⎯
µs
fCP = 20 MHz
⎯
3.7 (= 88 tCP)
⎯
µs
fCP = 24 MHz
1.6
⎯
∞
µs
⎯
1.6 (= 32 tCP)
⎯
µs
fCP = 20 MHz
⎯
2 (= 48 tCP)
⎯
µs
fCP = 24 MHz
Analog port input current
IAIN
AN0 to AN14
−1
⎯
+1
µA
Analog input voltage
range
VAIN
AN0 to AN14
AVRL
⎯
AVRH
V
⎯
AVRH
AVRL + 2.7
⎯
AVCC
V
⎯
AVRL
0
⎯
AVRH − 2.7
V
IA
AVCC
⎯
3.5
7.5
mA
IAH
AVCC
⎯
⎯
5
µA
Reference voltage range
Power supply current
Remarks
Reference voltage
current
IR
AVRH
⎯
165
250
µA
IRH
AVRH
⎯
⎯
5
µA
Offset between input
channels
⎯
AN0 to AN14
⎯
⎯
4
LSB
*
*
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .
Terminology
Conversion error
: Absolute maximum conversion deviation with respect to the theoretical conversion
line.
Nonlinearity
: Relative maximum conversion deviation with respect to the theoretical conversion line
connecting to the device unique zero reading voltage and full scale reading voltage.
Differential nonlinearity
: Max conversion deviation in any two adjacent reading voltages with respect to the
theoretical LSB conversion step.
Zero reading voltage
: Input voltage which results in the minimum conversion value.
Full scale reading voltage : Input voltage which results in the maximum conversion value.
Notes : • The accuracy gets worse as AVRH − AVRL becomes smaller.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing” in “4. AC Characteristics”.
62
MB90390 Series
6. Definition of A/D Converter Terms
Resolution
Linear error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential linear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
error
value.
Total error
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
Actual conversion
characteristics
1.5 LSB
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVSS
[V]
1024
Total error of digital output “N” =
1 LSB = (Ideal value)
[LSB]
N : A/D converter digital output value
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
63
MB90390 Series
(Continued)
Linear error
Differential linear error
Ideal
characteristics
3FFH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FDH
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
Actual conversion
characteristics
003H
Digital output
3FEH
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002H
Ideal characteristics
Actual conversion
characteristics
N−2
001H
VOT (actual measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
Linear error of digital output N =
Differential linear error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
−1 LSB [LSB]
[V]
N : A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
64
[LSB]
MB90390 Series
7. Notes on A/D Converter Section
• About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
2.4 kΩ (Max) 36.4 pF (Max)
MB90394HA/MB90F394H/MB90F394HA
Note : The values are reference values.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
100
90
20
External impedance [kΩ]
External impedance [kΩ]
MB90394HA
MB90F394H(A)
MB90394HA
MB90F394H(A)
80
70
60
50
40
30
20
10
0
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
0
Minimum sampling time [µs]
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
• About the error
The accuracy gets worse as |AVRH − AVRL| becomes smaller.
65
MB90390 Series
8. Flash Memory Program/Erase Characteristics
Parameter
Conditions
Sector erase time
Chip erase time
TA = +25 °C
VCC = 5.0 V
Word (16-bit width)
programming time
Value
Unit
Remarks
MIn
Typ
Max
⎯
1
15
s
Excludes 00H programming prior to erasure.
⎯
9
⎯
s
MB90F394H, Excludes
00H programming prior to
erasure.
⎯
16
3600
µs
Except for the over head
time of the system.
Programs/Erase cycle
⎯
10000
⎯
⎯
cycle
Flash Data Retention
Time
Average
TA = +85 °C
20
⎯
⎯
year
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
66
MB90390 Series
■ EXAMPLE CHARACTERISTICS
ICC - VCC (TA = +25 °C)
70
60
ICC [mA]
50
40
fCP = 5 MHz
fCP = 10 MHz
fCP = 20 MHz
fCP = 24 MHz
30
20
10
0
2
2.5
3.5
3
4.5
4
5.5
5
6
6.5
VCC [V]
ICCS - VCC (TA = +25 °C, fC = 4 MHz, fCP = 24 MHz)
30
25
ICCS [mA]
20
15
10
5
0
2
2.5
3.5
3
4.5
4
5.5
5
6
6.5
VCC [V]
ICTS - VCC (TA = +25 °C)
450
fC = 5 MHz,
fCP = 2.5 MHz
400
fC = 4 MHz,
fCP = 2 MHz
350
ICTS [µA]
300
250
200
150
100
50
0
3
4
5
6
7
VCC [V]
ICCH - TA
16
14
ICCH [µA]
12
10
VCC = 5.5 V
VCC = 4.5 V
VCC = 3.5 V
8
4
6
2
0
−40.00
−20.00
0.00
20.00
40.00
60.00
80.00
TA [°C]
67
MB90390 Series
• I/O characteristics
(VCC−VOH) − IOH
VOL − IOL
TA = +25 °C, VCC = 4.5 V
TA = +25 °C, VCC = 4.5 V
800
600
VOL (mV)
VCC VOH (mV)
700
500
400
300
200
100
0
0
1
2
3
4
5
7
6
8
9
1000
900
800
700
600
500
400
300
200
100
0
10
0
1
2
3
Automotive VIN − VCC
VIN (V)
VIN (V)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
CMOS VIN − VCC
UART-SIN pins and I2C pins of MB90394HA
VIN (V)
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIHS
VILS
3.0
3.5
4.0
4.5
5.0
VCC (V)
68
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
7
8
9
10
VIHS
VILS
2.5
3.0
3.5
4.0
4.5
5.0
VCC (V)
VCC (V)
2.5
6
Except UART-SIN pins and I2C pins of MB90394HA
TA = +25 °C
VIHA
VILA
2.5
5
CMOS VIN − VCC
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4
IOL (mA)
IOH (mA)
5.5
6.0
6.5
7.0
5.5
6.0
6.5
7.0
MB90390 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F394HPMT
120-pin Plastic LQFP
(FPT-120P-M21)
It is recommended to use MB90F394HA, because
MB90F394H does not support frequency modulation,
clock modulation and CAN message buffer RAM at
the same time.
MB90F394HAPMT
120-pin Plastic LQFP
(FPT-120P-M21)
MB90394HAPMT
120-pin Plastic LQFP
(FPT-120P-M21)
MB90V390HACR
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
It is recommended to use MB90V390HB, because
MB90V390HA does not support clock modulation
and CAN message buffer RAM at the same time.
MB90V390HBCR
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
MB90V390HCR
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
It is recommended to use MB90V390HB, because
MB90V390H does not support clock modulation and
CAN message buffer RAM at the same time.
69
MB90390 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
M ounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
1
30
0.50(.020)
C
70
"A"
31
2002 FUJITSU LIMITED F120033S-c-4-4
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB90390 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
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and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0605