FUJITSU MB95F118BW

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12615-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95110B Series
MB95116B/F118BS/F118BW/FV100D-101
■ DESCRIPTION
The MB95110B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set that is optimum to the controllers
• Multiplication and division instructions
• 16-bit arithmetic operation
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB95110B Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Time-base timer
• Watch prescaler (for dual clock product)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or Clock synchronous (SIO) serial data transfer capable
• UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or Clock synchronous (SIO) serial data transfer capable
2C*
•I
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Time-base timer mode
• I/O port:
• The number of maximum ports
• Single clock product : 39 ports
• Dual clock product : 37 ports
• Port configuration
• General-purpose I/O ports (N-ch open drain) : 2 ports
• General-purpose I/O ports (CMOS)
: Single clock product : 37 ports
Dual clock product : 35 ports
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
2
MB95110B Series
■ PRODUCT LINEUP
Part number
Parameter
Type
MB95116B
MB95F118BS
MB95F118BW
MASK ROM product
Flash memory product
ROM capacity
32 Kbytes
60 Kbytes
RAM capacity
1 Kbyte
2 Kbytes
Option*1
Reset output
Clock system
Low voltage
detection reset
Peripheral functions
CPU functions
No
Selectable
single/dual clock*2
Single clock
Dual clock
No
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25MHz)
Interrupt processing time
: 0.6 µs (at machine clock frequency 16.25 MHz)
General-purpose I/O
port
• Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
• Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports)
Time-base timer
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
: Minimum 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Minimum 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
I2C
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable.
LIN-UART
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable.
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(8 channels)
(Continued)
3
MB95110B Series
(Continued)
Part number
Peripheral functions
Parameter
MB95116B
MB95F118BS
MB95F118BW
8/16-bit
compound timer
(2 channels)
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer
× 1 channel”.
Built-in timer function, PWC function, PWM function, capture function and square
wave form output
Count clock : 7 internal clocks and external clock can be selected.
16-bit PPG
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG
× 1 channel”.
Counter operating clock : Eight selectable clock sources
Count clock : Four selectable clock sources (125ms, 250ms, 500ms, or 1s)
Watch counter
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
(for dual clock product)
selecting clock source 1 second and setting counter value to 60)
Watch prescaler
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
(for dual clock product)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded AlgorithmTM *3
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch (for dual clock product) , and time-base timer
*1 : For details of option, refer to “■ MASK OPTIONS”.
*2 : Specify clock mode when ordering MASK ROM.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of the evaluation products in MB95110B series is MB95FV100D-101. When using it, the MCU
board (MB2146-301A) is required.
4
MB95110B Series
■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY)
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value
of main clock oscillation stabilization wait time from among the following four values.
Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation
stabilization wait time at the maximum value.
Selection of oscillation stabilization wait time
Remarks
(2 − 2) /FCH
0.5 µs (at main oscillation clock 4 MHz)
(212 − 2) /FCH
Approx. 1.02 ms (at main oscillation clock 4 MHz)
(213 − 2) /FCH
Approx. 2.05 ms (at main oscillation clock 4 MHz)
(2 − 2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
2
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95116B
MB95F118BS/F118BW
MB95FV100D-101
Package
LCC-48P-M09
FPT-48P-M26
FPT-52P-M01
*
BGA-224P-M08
: Available
: Unavailable
* : Under development
5
MB95110B Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The evaluation product has not only the functions of the MB95110B corresponding products series but also
those of other products to support software development for multiple series and models of the F2MC-8FX family.
The I/O addresses for peripheral resources not used by the MB95110B series are therefore access-barred.
Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused
to operate, resulting in unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Note that the values read from barred addresses are different between the evaluation product and the Flash
memory product. Therefore, the value must not be used for program.
The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are
designed to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
The current consumption of Flash memory product is greater than for MASK ROM product.
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different among the evaluation, Flash memory, and MASK ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
• Difference between RST and MOD pins
The input type of RST and MOD pins is CMOS input on the Flash memory product.
The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for
the MOD pin of the MASK ROM product.
6
MB95110B Series
■ PIN ASSIGNMENTS
P64/EC1
P63/TO11
P62/TO10
P61/PPG11
P60/PPG10
P15
P14/PPG0
P13/TRG0/ADTG
P12/UCK0
P11/UO0
P10/UI0
P07/INT07
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
34
P04/INT04
P36/AN06
5
33
P03/INT03
P35/AN05
6
32
P02/INT02
P34/AN04
7
31
P01/INT01
P33/AN03
8
30
P00/INT00
P32/AN02
9
29
RST
P31/AN01
10
28
PG1/X0A*
P30/AN00
11
27
PG2/X1A*
AVss
12
26
PG0
25
Vcc
13
14
15
16
17
18
19
20
21
22
23
24
Vss
4
X1
P37/AN07
X0
P05/INT05
MOD
35
P50/SCL0
3
P51/SDA0
P67/SIN
P20/PPG00
P06/INT06
P21/PPG01
36
P22/TO00
2
P23/TO01
P66/SOT
P24/EC0
1
AVcc
P65/SCK
(LCC-48P-M09)
* : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product.
(Continued)
7
MB95110B Series
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P15
P60/PPG10
P61/PPG11
P62/TO10
P63/TO11
P64/EC1
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
P65/SCK
1
36
P06/INT06
P66/SOT
2
35
P05/INT05
P67/SIN
3
34
P04/INT04
P37/AN07
4
33
P03/INT03
P36/AN06
5
32
P02/INT02
P35/AN05
6
31
P01/INT01
P34/AN04
7
30
P00/INT00
P33/AN03
8
29
RST
P32/AN02
9
28
PG1/X0A*
P31/AN01
10
27
PG2/X1A*
P30/AN00
11
26
PG0
AVss
12
25
Vcc
Vss
X1
X0
MOD
P50/SCL0
P51/SDA0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
AVcc
P24/EC0
13 14 15 16 17 18 19 20 21 22 23 24
(FPT-48P-M26)
* : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product.
(Continued)
8
MB95110B Series
(Continued)
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
NC
P15
P60/PPG10
P61/PPG11
P62/TO10
P63/TO11
P64/EC1
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
P65/SCK
1
39
P06/INT06
P66/SOT
2
38
P05/INT05
P67/SIN
3
37
P04/INT04
P37/AN07
4
36
P03/INT03
P36/AN06
5
35
P02/INT02
P35/AN05
6
34
P01/INT01
NC
7
33
NC
P34/AN04
8
32
P00/INT00
P33/AN03
9
31
RST
P32/AN02
10
30
PG1/X0A*
P31/AN01
11
29
PG2/X1A*
P30/AN00
12
28
PG0
AVss
13
27
Vcc
Vss
X1
X0
MOD
P50/SCL0
P51/SDA0
NC
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
AVcc
P24/EC0
14 15 16 17 18 19 20 21 22 23 24 25 26
(FPT-52P-M01)
* : The pins are general-purpose port in single clock product or sub clock oscillation pin in dual clock product.
9
MB95110B Series
■ PIN DESCRIPTION
Pin no.
LQFP*1
LQFP*2
1
1
Pin name
I/O
Circuit
type*3
P65/SCK
K
2
2
P66/SOT
3
3
P67/SIN
4
4
P37/AN07
5
5
P36/AN06
6
6
P35/AN05
7
8
P34/AN04
8
9
P33/AN03
9
10
P32/AN02
10
11
P31/AN01
11
12
P30/AN00
12
13
13
Function
General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
General-purpose I/O port.
The pin is shared with LIN-UART data output.
L
General-purpose I/O port.
The pin is shared with LIN-UART data input.
J
General-purpose I/O port.
The pins are shared with A/D converter analog input.
AVss
⎯
A/D converter power supply pin (GND)
14
AVcc
⎯
A/D converter power supply pin
14
15
P24/EC0
15
16
P23/TO01
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input.
H
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.0 output.
16
17
P22/TO00
17
18
P21/PPG01
18
19
P20/PPG00
19
21
P51/SDA0
20
22
P50/SCL0
21
23
MOD
22
24
X0
23
25
X1
24
26
Vss
⎯
Power supply pin (GND)
25
27
Vcc
⎯
Power supply pin
26
28
PG0
H
General-purpose I/O port.
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.0 output.
I
B
A
General-purpose I/O port.
The pin is shared with I2C ch.0 data I/O.
General-purpose I/O port.
The pin is shared with I2C ch.0 clock I/O.
Operating mode designation pin
Main clock input oscillation pin
Main clock input/output oscillation pin
(Continued)
10
MB95110B Series
(Continued)
Pin no.
Pin name
LQFP*1
LQFP*2
27
29
PG2/X1A
28
30
PG1/X0A
29
31
RST
30
32
P00/INT00
31
34
P01/INT01
32
35
P02/INT02
33
36
P03/INT03
34
37
P04/INT04
35
38
P05/INT05
36
39
P06/INT06
37
40
P07/INT07
38
41
P10/UI0
39
42
P11/UO0
40
43
P12/UCK0
41
44
P13/TRG0/
ADTG
42
45
P14/PPG0
43
47
P15
44
48
P60/PPG10
45
49
P61/PPG11
46
50
P62/TO10
47
51
P63/TO11
48
52
P64/EC1
⎯
7, 20,
33, 46
NC
I/O
Circuit
type*3
H/A
Function
This pin is general-purpose port in single clock product (PG2) .
This pin is sub clock oscillation pin in dual clock product (32 kHz) .
This pin is general-purpose port in single clock product (PG1) .
This pin is sub clock oscillation pin in dual clock product (32 kHz) .
B’
Reset pin
C
General-purpose I/O port.
The pins are shared with external interrupt input. Large current port.
G
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D converter trigger input (ADTG).
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
General-purpose I/O port.
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.1 output.
K
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.1 output.
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.1 clock input.
⎯
Internal connect pin.
Be sure this pin is left open.
*1 : FPT-48P-M26
*2 : FPT-52P-M01
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”
11
MB95110B Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1 (X1A)
A
Remarks
Clock input
N-ch
X0 (X0A)
Standby control
B
Mode input
R
B’
Reset input
P-ch
• Oscillation circuit
• High-speed side
Feedback resistance value : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
Dumping resistance : approx. 144 kΩ
(Evaluation product : without dumping
resistance)
• Only for input
• Hysteresis input only for MASK ROM
product
• With pull-down resistor only for MASK
ROM product
Hysteresis input only for MASK ROM
product
• CMOS output
• Hysteresis input
Digital output
Digital output
C
N-ch
Hysteresis input
Standby control
External
interrupt enable
Pull-up control
R
P-ch
P-ch
G
N-ch
Digital output
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
Digital output
CMOS input
Standby control
Hysteresis input
(Continued)
12
MB95110B Series
(Continued)
Type
Circuit
R
P-ch
Remarks
Pull-up control
P-ch
• CMOS output
• Hysteresis input
• With pull-up control
Digital output
H
Digital output
N-ch
Hysteresis input
Standby control
Digital output
N-ch
• N-ch open drain output
• CMOS input
• Hysteresis input
I
CMOS input
Hysteresis input
Standby control
Pull-up control
R
P-ch
P-ch
J
•
•
•
•
CMOS output
Hysteresis input
Analog input
With pull-up control
Digital output
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
P-ch
• CMOS output
• Hysteresis input
Digital output
Digital output
K
N-ch
Hysteresis input
Standby control
P-ch
Digital output
N-ch
L
• CMOS output
• CMOS input
• Hysteresis input
Digital output
CMOS input
Standby control
Hysteresis input
13
MB95110B Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50 Hz/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the
transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply
is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
14
MB95110B Series
■ PIN CONNECTION
• Treatment of Unused Input Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ.
Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the
same as unused input pins. If there is unused output pin, make it to open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between VCC
and VSS pins near this device.
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection.
• Analog Power Supply
Always set the same potential to AVCC and VCC . When VCC > AVCC, the current may flow through the AN00 to
AN07 pins.
15
MB95110B Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-48P-M26
TEF110-118F37AP
FPT-52P-M01
TEF110-95F118PMC
LCC-48P-M09
TEF100-118F41AP
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Note: For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Flash memory
CPU address
Writer address*
1000H
71000H
1FFFH
2000H
71FFFH
72000H
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA2 (4 Kbytes)
Lower bank
SA1 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
Upper bank
SA5 (16 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
16
MB95110B Series
• Programming Method
1) Set the type code of the parallel programmer to “17226”.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer.
17
MB95110B Series
■ BLOCK DIAGRAM
2
F MC-8FX CPU
RST
X0,X1
PG2/X1A*
PG1/X0A*
PG0
Reset control
ROM
RAM
Clock control
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt
8/16-bit PPG ch.1
P10/UI0
UART/SIO
P13/TRG0/ADTG
P14/PPG0
16-bit PPG
P15
8/16-bit compound
timer ch.1
P63/TO11
P64/EC1
LIN-UART
P66/SOT
P65/SCK
P67/SIN
P20/PPG00
P21/PPG01
8/16-bit PPG ch.0
P22/TO00
P23/TO01
P24/EC0
8/16-bit compound
timer ch.0
P30/AN00 to P37/AN07
AVCC
P61/PPG11
P62/TO10
Internal bus
P11/UO0
P12/UCK0
P60/PPG10
8/10-bit
A/D converter
AVSS
P50/SCL0
P51/SDA0
I 2C
Port
Port
Other pins
MOD, VCC, VSS
* : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.
18
MB95110B Series
■ CPU CORE
1. Memory space
Memory space of the MB95110B series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95110B series shown in below.
• Memory Map
MB95F118BS
MB95F118BW
MB95116B
0000H
0080H
0100H
RAM 1 Kbyte
Register
0200H
0480H
0F80H
0000H
0000H
I/O
0080H
0100H
0880H
0080H
RAM 2 Kbytes
Register
RAM 3.75 Kbytes
0100H
Register
0200H
Access
prohibited
0F80H
Extension I/O
0F80H
Extension I/O
Extension I/O
1000H
1000H
1000H
I/O
I/O
0200H
Access
prohibited
MB95FV100D-101
Access
prohibited
Flash memory
60 Kbytes
Flash memory
60 Kbytes
8000H
MASK ROM
32 Kbytes
FFFFH
FFFFH
FFFFH
19
MB95110B Series
2. Register
The MB95110B series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
: A 16-bit register to indicate locations where instructions are stored.
Program counter (PC)
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower one byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower one byte is used.
: A 16-bit register for index modification
Index register (IX)
: A 16-bit pointer to point to a memory address.
Extra pointer (EP)
: A 16-bit register to indicate a stack area.
Stack pointer (SP)
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
: Program counter
FFFDH
A
: Accumulator
0000H
T
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
PC
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.)
• Structure of the program status
bit15 bit14 bit13 bit12 bit11 bit10
PS
R4
R3
R2
RP
20
R1
R0
DP2
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DP1
DP0
H
I
IL1
IL0
N
Z
V
C
DP
CCR
MB95110B Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
OP code lower
RP upper
"0"
Generated address
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by this bit.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
Low = no interruption
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
Z flag
V flag
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
C flag
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
bit is set to “0”.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB95110B Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. One bank contains
eight registers. Up to a total of 32 banks can be used on the MB95110B series. The bank currently in use is
specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register
0 (R0) to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
107H
R6
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
22
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
MB95110B Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
⎯
(Disabled)
⎯
⎯
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
PDR3
Port 3 data register
R/W
00000000B
0011H
DDR3
Port 3 direction register
R/W
00000000B
0012H,
0013H
⎯
(Disabled)
⎯
⎯
0014H
PDR5
Port 5 data register
R/W
00000000B
0015H
DDR5
Port 5 direction register
R/W
00000000B
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0029H
⎯
(Disabled)
⎯
⎯
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
⎯
(Disabled)
⎯
⎯
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
002FH
PUL3
Port 3 pull-up register
R/W
00000000B
0030H
to
0034H
⎯
(Disabled)
⎯
⎯
(Continued)
23
MB95110B Series
Address
Register
abbreviation
Register name
R/W
Initial value
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG status control register (Upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register (Lower byte) ch.0
R/W
00000000B
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
(Continued)
24
MB95110B Series
Address
Register
abbreviation
Register name
R/W
Initial value
0060H
IBCR00
I2C bus control register 0 ch.0
R/W
00000000B
2
0061H
IBCR10
I C bus control register 1 ch.0
R/W
00000000B
0062H
IBSR0
I2C bus status register ch.0
R
00000000B
0063H
IDDR0
I2C data register ch.0
R/W
00000000B
I C address register ch.0
R/W
00000000B
0064H
2
IAAR0
2
0065H
ICCR0
I C clock control register ch.0
R/W
00000000B
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
(Mirror of register bank pointer (RP) and direct bank
pointer (DP) )
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (Upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
(Continued)
25
MB95110B Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F86H
WRARH2
Wild register address setting register (Upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control
register ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control
register ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG starting register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (Upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (Lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (Upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (Lower byte) ch.0
R/W
11111111B
(Continued)
26
MB95110B Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
0FC3H
AIDRL
A/D input disable register (Lower byte)
R/W
00000000B
0FC4H
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
27
MB95110B Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
I2C ch.0
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler/watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
28
Interrupt
request
number
High
Low
MB95110B Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp current
“L” level maximum
output current
Symbol
Rating
Vcc,
AVcc
Vss − 0.3
Vss + 4.0
VI1
Vss − 0.3
Vss + 4.0
VI2
Vss − 0.3
Vss + 6.0
VO
Vss − 0.3
Vss + 4.0
V
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL1
IOL2
⎯
V
mA
mA
12
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
⎯
− 15
− 15
⎯
“H” level average current
mA
−4
IOHAV1
mA
−8
IOHAV2
“H” level total maximum
output current
15
V
4
IOLAV2
“H” level maximum
output current
15
⎯
“L” level average current
“L” level total average
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“H” level total average
output current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
*2
Other than P50, P51*3
P50, P51
*3
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(total of pins)
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(total of pins)
(Continued)
29
MB95110B Series
(Continued)
*1 : The parameter is based on AVCC = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc.
*3 : VI1 and VO should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI1 rating.
*4 : •
•
•
•
•
•
•
•
•
•
Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, PG0
Use within recommended operating conditions.
Use at DC voltage (current).
+B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the + B input pin open.
Sample recommended circuits :
• Input/Output Equivalent Circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
MB95110B Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
Operating
temperature
VCC,
AVCC
TA
Pin name
⎯
⎯
Conditions
⎯
⎯
Value
Unit
Remarks
Min
Typ
Max
1.8*
⎯
3.3
At normal operating, Flash
memory product,
TA = − 10 °C to + 85 °C
1.8*
⎯
3.6
At normal operating,
MASK ROM product,
TA = − 10 °C to + 85 °C
2.0*
⎯
3.3
At normal operating, Flash
memory product,
TA = − 40 °C to + 85 °C
2.0*
⎯
3.6
2.6
⎯
3.6
MB95FV100D-101,
TA = + 5 °C to + 35 °C
1.5
⎯
3.3
Retain status of stop mode
operation, Flash memory
product
1.5
⎯
3.6
Retain status of stop mode
operation, MASK ROM
product
− 40
⎯
+ 85
V
At normal operating,
MASK ROM product,
TA = − 40 °C to + 85 °C
°C
* : The values vary with the operating frequency.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
31
MB95110B Series
3. DC Characteristics
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
“H” level
input voltage
Symbol
Conditions
Value
Min
Typ
Max
Unit
Remarks
VIH1
P10, P67
*1
0.7 Vcc
⎯
Vcc + 0.3
V
At selecting of
CMOS input level
(hysteresis input)
VIH2
P50, P51
*1
0.7 Vcc
⎯
Vss + 5.5
V
At selecting of
CMOS input level
(hysteresis input)
VIHS1
P00 to P07,
P10 to P15,
P20 to P24,
P30 to P37,
P60 to P67,
PG0, PG1*1,
PG2*1
*1
0.8 Vcc
⎯
Vcc + 0.3
V
Hysteresis input
VIHS2
P50, P51
*1
0.8 Vcc
⎯
Vss + 5.5
V
Hysteresis input
⎯
0.7 Vcc
⎯
Vcc + 0.3
V
CMOS input
(Flash memory
product)
⎯
0.8 Vcc
⎯
Vcc + 0.3
V
Hysteresis input
(MASK ROM
product)
VIHM
RST, MOD
VIL
P10, P50,
P51, P67
*1
Vss − 0.3
⎯
0.3 Vcc
V
At selecting of
CMOS input level
(hysteresis input)
VILS
P00 to P07,
P10 to P15,
P20 to P24,
P30 to P37,
P50, P51,
P60 to P67,
PG0, PG1*1,
PG2*1
*1
Vss − 0.3
⎯
0.2 Vcc
V
Hysteresis input
⎯
Vss − 0.3
⎯
0.3 Vcc
V
CMOS input
(Flash memory
product)
⎯
Vss − 0.3
⎯
0.2 Vcc
V
Hysteresis input
(MASK ROM
product)
⎯
Vss − 0.3
⎯
Vss + 5.5
V
“L” level
input voltage
VILM
Open drain
output application
voltage
Pin name
VD
RST, MOD
P50, P51
(Continued)
32
MB95110B Series
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
VOH1
Output pin
other than
P00 to P07
VOH2
Value
Unit
Remarks
⎯
V
MB95FV100D-101 a
conditional :
IOH = − 2.0 mA
⎯
⎯
V
MB95FV100D-101 a
conditional :
IOH = − 5.0 mA
⎯
⎯
0.4
V
MB95FV100D-101 a
conditional :
IOL = 3.0 mA
IOL = 12 mA
⎯
⎯
0.4
V
MB95FV100D-101 a
conditional :
IOL = 8.0 mA
Port other
than P50,
P51
0.0 V < VI <
Vcc
−5
⎯
+5
µA
When no pull-up
prohibition setting
ILIOD
P50, P51
0.0 V < VI <
Vss + 5.5 V
⎯
⎯
5
µA
Pull-up resistor
RPULL
P10 to P15,
P20 to P24,
P30 to P37, VI = 0.0 V
PG0, PG1*2,
PG2*2
25
50
100
kΩ
When pull-up
permission setting
Pull-down resistor
RMOD MOD
50
100
200
kΩ
MASK ROM
product
14
Flash memory
product
mA (at other than Flash
memory writing and
erasing)
Min
Typ
Max
IOH =
− 4.0 mA
2.4
⎯
P00 to P07
IOH =
− 8.0 mA
2.4
VOL1
Output pin
other than
P00 to P07
IOL =
4.0 mA
VOL2
P00 to P07
ILI
“H” level
output voltage
“L” level
output voltage
Input leakage
current
(Hi-Z output
leakage current)
Open drain
output leakage
current
Conditions
VI = Vcc
⎯
Power supply
current*3
ICC
VCC
(external
clock
operation)
FCH = 20 MHz
FMP = 10 MHz
Main clock
mode
(divided by 2)
11
⎯
7.3
10
Flash memory
product
mA
(at Flash memory
writing and erasing)
⎯
30
35
mA
MASK ROM
product
(Continued)
33
MB95110B Series
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
Value
Min
⎯
ICC
17.6
Max
22.4
Unit
Remarks
mA
Flash memory
product
(at other than Flash
memory writing and
erasing)
⎯
38.1
44.9
mA
Flash memory
product
(at Flash memory
writing and erasing)
⎯
11.7
16.0
mA
MASK ROM
product
FCH = 20 MHz
FMP = 10 MHz
Main sleep mode
(divided by 2)
⎯
4.5
6
mA
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
⎯
7.2
9.6
mA
ICCL
FCL = 32 kHz
VCC
FMPL = 16 kHz
(external clock
Sub clock mode
operation)
(divided by 2) ,
TA = + 25 °C
⎯
25
35
µA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
7
15
µA
⎯
2
10
µA
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
Flash memory
product
⎯
1
5
µA
MASK ROM
product
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
⎯
10
14
mA
Flash memory
product
⎯
6.7
10
mA
MASK ROM
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯
16.0
22.4
mA
Flash memory
product
⎯
10.8
16.0
mA
MASK ROM
product
ICCS
Power supply
current*3
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
Typ
ICCMPLL
(Continued)
34
MB95110B Series
(Continued)
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Power supply
current*3
IA
AVcc
IAH
Input
capacitance
CIN
Other than
AVcc, AVss,
Vcc, and Vss
Unit
Typ
Max
⎯
190
250
µA
⎯
0.4
0.5
mA
Sub stop mode
TA = + 25 °C
⎯
1
5
µA
FCH = 10 MHz
At A/D converting
⎯
1.3
2.2
mA
FCH = 10 MHz
At A/D converting
stop
TA = + 25 °C
⎯
1
5
µA
f = 1 MHz
⎯
5
15
pF
VCC
(external clock FCH = 10 MHz
Time-base timer
operation)
mode
TA = + 25 °C
ICCH
Value
Min
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
ICCSPLL
ICTS
Conditions
Remarks
*1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*2 : Single clock products only
*3 : The power-supply current is determined by the external clock.
• Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for fMP and fMPL.
35
MB95110B Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
FCH
Pin
Conditions
X0, X1
Clock frequency
FCL
X0A,
X1A
Value
Unit
Remarks
16.25
MHz
When using main
oscillation circuit
⎯
32.50
MHz When using external clock
3.00
⎯
10.00
MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
Min
Typ
Max
1.00
⎯
1.00
kHz
When using sub
oscillation circuit
When using sub PLL
Flash memory product :
Vcc = 2.3 V to 3.3 V
MASK ROM product :
Vcc = 2.3 V to 3.6 V
⎯
32.768
⎯
kHz
100
⎯
1000
ns
When using main
oscillation circuit
50
⎯
1000
ns
When using external clock
When using sub
oscillation circuit,
When using external clock
⎯
tHCYL
X0, X1
Clock cycle time
Input clock pulse width
Input clock rise time and
fall time
36
tLCYL
X0A,
X1A
⎯
30.5
⎯
µs
tWH1
tWL1
X0
10
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0,
X0A
⎯
⎯
5
ns
When using external clock
MB95110B Series
• Input Wave form when using External Clock (Main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input Wave form when using External Clock (Sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of Sub clock Input Port External Connection
When using a crystal or
ceramic oscillator
Microcontroller
X0A
X1A
When using external clock
Microcontroller
X0A
FCL
X1A
Open
FCL
C1
C2
37
MB95110B Series
(2) Source Clock/Machine Clock
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Source clock*1
(Clock before setting
division)
Source clock frequency
Machine clock*2
(Minimum instruction
execution time)
Machine clock
frequency
Sym- Pin
bol name
tSCLK
Value
Unit
Remarks
2000
ns
When using Main clock
Min : FCH = 8.125 MHz, PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
⎯
61.0
µs
When using Sub clock
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
16.25
Min
Typ
Max
61.5
⎯
7.6
⎯
FSP
⎯
0.5
⎯
FSPL
⎯
16.38
4
⎯
100
⎯
32000
ns
When using Main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
⎯
976.5
µs
When using Sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
0.031
⎯
16.250 MHz When using Main clock
1.024
⎯
131.072 kHz When using Sub clock
tMCLK
FMP
FMPL
MHz When using Main clock
131.072 kHz When using Sub clock
⎯
⎯
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follow.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
38
MB95110B Series
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
( source clock )
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
39
MB95110B Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95116B
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
3.6
3.6
2.7
1.8
0.5 MHz 3 MHz 5 MHz
PLL operation guarantee range
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSP)
• MB95F118BS, MB95F118BW
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSP)
40
Operating voltage (V)
Operating voltage (V)
3.3
2.7
1.8
0.5 MHz 3 MHz 5 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
MB95110B Series
• Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
• MB95116B
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
2.3
2.0
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
3.6
2.7
2.0
0.5 MHz 3 MHz
5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSP)
• MB95F118BS, MB95F118BW
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
2.3
2.0
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSP)
Operating voltage (V)
Operating voltage (V)
3.3
3.3
2.7
2.0
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
41
MB95110B Series
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-101
Main clock mode and main PLL mode
operation guarantee range
3.6
Operating voltage (V)
Operating voltage (V)
Sub PLL , Sub clock mode and
watch mode operation guarantee range
2.6
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSP)
42
3.6
3.3
2.6
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
MB95110B Series
• Main PLL operation frequency
[MHz]
16.25
16
15
×4
Source clock frequency (FSP)
12
× 2.5
×2
×1
10
7.5
6
5
3
0
3
4
4.062
5
6.4
6.5
8
8.125
10 [MHz]
Main clock frequency (FMP)
43
MB95110B Series
(3) External Reset
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
RST “L” level pulse
width
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operating
Oscillation time of oscillator*2
+ 2 tMCLK*1
⎯
ns
At stop mode, sub clock mode,
sub sleep mode, and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds
of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
Oscillation time
of oscillator
2 tMCLK
Oscillation stabilization wait time
Execute instruction
Internal reset
44
MB95110B Series
(4) Power-on Reset
(AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min
Max
⎯
⎯
36
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
Note : The power supply must be turned on within the selected oscillation stabilization time.
tR
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold condition in stop mode
VSS
45
MB95110B Series
(5) Peripheral Input Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Peripheral input “H” pulse
width
tILIH
Peripheral input “L” pulse
width
tIHIL
Value
Pin name
INT00 to INT07, EC0, EC1,
TRG0/ADTG
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1,
TRG0/ADTG
46
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
Unit
Min
0.2 VCC
MB95110B Series
(6) UART/SIO, Serial I/O Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Value
Conditions
Unit
Min
Max
4 tMCLK*
⎯
ns
− 190
+ 190
ns
2 tMCLK*
⎯
ns
UCK0, UI0
2 tMCLK*
⎯
ns
tSHSL
UCK0
4 tMCLK*
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
UCK0, UO0
⎯
190
ns
Valid UI → UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
⎯
ns
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
⎯
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
External clock
operation output pin :
CL = 80 pF + 1 TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
UI0
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
47
MB95110B Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SCK ↑→ SOT delay time
SymPin name
bol
tSCYC
tSLOVI
Valid SIN→SCK↑
tIVSHI
SCK↑→ valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Conditions
Max
5 tMCLK*3
⎯
ns
− 95
+ 95
ns
⎯
ns
0
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
SCK
SCK
SCK ↓→SOT delay time
tSLOVE SCK, SOT
Valid SIN→SCK↑
tIVSHE
SCK↑→ valid SIN hold time
tSHIXE
External clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL
SCK, SIN
Unit
Min
t
* + 190
MCLK 3
MCLK 3
t
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
48
MB95110B Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
tSLSH
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tF
SOT
0.8 VCC
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
49
MB95110B Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
t
Unit
Min
Max
5 tMCLK*3
⎯
ns
− 95
+ 95
ns
⎯
ns
0
⎯
ns
* + 190
MCLK 3
Valid SIN→SCK↓
tIVSLI
SCK↓→ valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK↑ →SOT delay time
tSHOVE
Valid SIN→SCK↓
tIVSLE
SCK↓→ valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
SCK, SIN CL = 80 pF + 1 TTL
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
50
MB95110B Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
0.2 VCC
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
51
MB95110B Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Valid SIN→SCK↓
tIVSLI
SCK, SIN
SCK↓→ valid SIN hold time
tSLIXI
SCK, SIN
SOT→SCK↓ delay time
tSOVLI
SCK, SOT
Internal clock
operation output pin :
CL = 80 pF + 1 TTL
Unit
Min
Max
5 tMCLK*3
⎯
ns
− 95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
0.8 VCC
0.2 VCC
52
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.2 VCC
MB95110B Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK↓→SOT hold time
tSLOVI
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
− 95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN→SCK↑
tIVSHI
SCK↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operating output pin :
CL = 80 pF + 1 TTL
SCK, SIN
SOT→SCK↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
SIN
tSLOVI
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
53
MB95110B Series
(8) I2C Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin
name
Conditions
Standardmode
Fast-mode
Min
Max
Min
Max
Unit
fSCL
SCL0
0
100
0
400
kHz
tHD;STA
SCL0
SDA0
4.0
⎯
0.6
⎯
µs
SCL clock “L” width
tLOW
SCL0
4.7
⎯
1.3
⎯
µs
SCL clock “H” width
tHIGH
SCL0
4.0
⎯
0.6
⎯
µs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA
SCL0
SDA0
4.7
⎯
0.6
⎯
µs
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
SCL0
SDA0
0
3.45*2
0
0.9*3
µs
Data setup time SDA ↓ ↑ → SCL ↑
tSU;DAT
SCL0
SDA0
0.25
⎯
0.1
⎯
µs
Stop condition setup time SCL ↑ →
SDA ↑
tSU;STO
SCL0
SDA0
4
⎯
0.6
⎯
µs
tBUF
SCL0
SDA0
4.7
⎯
1.3
⎯
µs
SCL clock frequency
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
tSU;DAT
tSU;STO
tSU;STA
54
MB95110B Series
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Sym- Pin
Condition
bol name
Value*2
Min
Max
Unit
Remarks
SCL clock “L” width
tLOW
SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns
Master mode
SCL clock “H” width
tHIGH
SCL0
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns
Master mode
ns
Master mode
Maximum value is
applied when m, n = 1, 8.
Otherwise, the minimum
value is applied.
Start condition hold
time
tHD;STA
SCL0
SDA0
(−1 + nm / 2) tMCLK − 20
Stop condition setup
time
tSU;STO
SCL0
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition setup
time
tSU;STA
SCL0
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Bus free time between
stop condition and
start condition
tBUF
SCL0
SDA0
(2 nm + 4) tMCLK − 20
⎯
ns
tHD;DAT
SCL0
SDA0
3 tMCLK − 20
⎯
ns
Master mode
ns
Master mode
When assuming that “L”
of SCL is not extended,
the minimum value is
applied to first bit of
continuous data.
Otherwise, the maximum
value is applied.
Data hold time
Data setup time
tSU;DAT
SCL0
SDA0
(−1 + nm) tMCLK + 20
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
R = 1.7 kΩ,
C = 50 pF*1
Setup time between
clearing interrupt and tSU;INT SCL0
SCL rising
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Minimum value is
applied to interrupt at 9th
SCL↓.
Maximum value is
applied to interrupt at 8th
SCL↓.
SCL clock “L” width
tLOW
SCL0
4 tMCLK − 20
⎯
ns
At reception
SCL clock “H” width
tHIGH
SCL0
4 tMCLK − 20
⎯
ns
At reception
Start condition
detection
tHD;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK
is used at reception
Stop condition
detection
tSU;STO
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK
is used at reception
Restart condition
detection condition
tSU;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK
is used at reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW − 3 tMCLK − 20
⎯
ns
At slave transmission
mode
(Continued)
55
MB95110B Series
(Continued)
Parameter
Value*2
Sym- Pin
Condition
bol name
Data hold time
tHD;DAT
SCL0
SDA0
Data setup time
tSU;DAT
SCL0
R = 1.7 kΩ,
SDA0
C = 50 pF*1
SDA↓→SCL↑
(at wake-up function)
tWAKEUP
SCL0
SDA0
Unit
Remarks
Min
Max
0
⎯
ns
At reception
tMCLK − 20
⎯
ns
At reception
Oscillation stabilization
wait time
+ 2 tMCLK − 20
⎯
ns
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
56
MB95110B Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 1.8 V to 3.3 V [Flash memory product], AVcc = Vcc = 1.8 V to 3.6 V [MASK ROM product], AVss =
Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Linearity error
⎯
Differential linear
error
Zero transition
voltage
Full-scale transition
voltage
Compare time
Sampling time
VOT
VFST
⎯
Remarks
AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB
V
Flash memory product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVcc ≤ 3.6 V
AVss − 0.5 LSB AVss + 1.5 LSB AVss + 3.5 LSB
V
1.8 V ≤ AVcc < 2.7 V
AVcc − 3.5 LSB AVcc − 1.5 LSB AVcc + 0.5 LSB
V
Flash memory product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVcc ≤ 3.6 V
AVcc − 2.5 LSB AVcc − 0.5 LSB AVcc + 1.5 LSB
V
1.8 V ≤ AVcc < 2.7 V
1.3
⎯
140
µs
Flash memory product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVcc ≤ 3.6 V
20
⎯
140
µs
1.8 V ≤ AVcc < 2.7 V
0.4
⎯
∞
µs
Flash memory product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVcc ≤ 3.6 V
external impedance <
at 1.8 kΩ
30
⎯
∞
µs
1.8 V ≤ AVcc < 2.7 V
external impedance <
at 14.8 kΩ
⎯
Analog input
current
IAIN
−0.3
⎯
+ 0.3
µA
Analog input
voltage
VAIN
AVss
⎯
AVcc
V
⎯
AVss + 1.8
⎯
AVcc
V
AVcc pin
IR
⎯
400
600
µA
AVcc pin,
During A/D operation
IRH
⎯
⎯
5
µA
AVcc pin,
at stop mode
Reference voltage
Reference voltage
supply current
57
MB95110B Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input pin
Comparator
C
During sampling : ON
2.7 V ≤ AVcc ≤ 3.6 V
1.8 V ≤ AVcc < 2.7 V
R
1.7 kΩ (Max)
84 kΩ (Max)
C
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
AVcc ≥ 2.7 V
External impedance [kΩ]
External impedance [kΩ]
AVcc ≥ 2.7 V
100
90
80
70
60
50
40
30
20
10
0
AVcc ≥ 1.8 V
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
40
20
18
16
14
12
10
8
6
4
2
0
0
1
• About errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
58
2
3
Minimum sampling time [µs]
4
MB95110B Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
3FEH
1.5 LSB
004H
VOT
003H
002H
3FDH
Digital output
Digital output
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
Actual conversion
characteristic
003H
002H
1 LSB
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVCC
AVSS
Analog input
Analog input
AVCC
1 LSB = AVCC − AVSS (V)
1024
Total error of digital output N =
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
59
MB95110B Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004H
3FFH
003H
002H
Ideal
characteristics
Actual conversion
characteristic
Digital output
Digital output
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
AVSS
AVSS
AVCC
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
Ideal characteristics
003H
002H
Digital output
{1 LSB × N + VOT}
3FDH
Digital output
Ideal characteristics
N + 1H
3FEH
N − 1H
VNT
Actual conversion
characteristic
VOT (measurement value)
AVSS
AVCC
AVSS
AVCC
Analog input
Linear error in digital output N =
Analog input
VNT − {1 LSB × N + VOT}
1 LSB
Differential linear error in digital output N = V (N + 1) T − VNT
1 LSB
−1
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVCC − 1.5 LSB [V]
60
V (N + 1) T
NH
N − 2H
001H
AVCC
Analog input
MB95110B Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
3.0*2
s
Excludes 00H programming prior erasure
0.5*1
12.0*2
s
Excludes 00H programming prior erasure
⎯
32
3600
µs
Excludes system-level overhead
10000
⎯
⎯
cycle
Power supply voltage at
erase/program
2.7
⎯
3.3
V
Flash data retention time
20*3
⎯
⎯
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2*1
Sector erase time
(16 Kbytes sector)
⎯
Byte programming time
Erase/program cycle
year Average TA = +85 °C
*1 : TA = +25 °C, Vcc = 3.0 V, 10000 cycles
*2 : TA = +85 °C, Vcc = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
61
MB95110B Series
■ MASK OPTIONS
Part number
No
Specifying procedure
MB95116B
MB95F118BS
Specify when
Setting disabled
ordering MASK
MB95F118BW
MB95FV100D-101
Setting disabled
Setting disabled
1
Clock mode select
• Single-system clock mode
• Dual-system clock mode
Selectable
Single-system
clock mode
Dual-system
clock mode
Changing by the
switch on MCU
board
2
Low voltage detection reset*
• With low voltage detection
reset
• Without low voltage
detection reset
No
No
No
No
3
Selection of oscillation
Selectable
stabilization wait time
1 : ( 22 − 2) /FCH
• Selectable the initial value 2 : ( 212 − 2) /FCH
3 : ( 213 − 2) /FCH
of main clock oscillation
4 : ( 214 − 2) /FCH
stabilization wait time
Fixed to oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to oscillation
stabilization wait
time of
(214-2) /FCH
* : Low voltage detection reset is options of 5-V products.
■ ORDERING INFORMATION
Part number
MB95116BPV2
MB95F118BSPV2
MB95F118BWPV2
48-pin plastic BCC
(LCC-48P-M09)
MB95116BPMT
MB95F118BSPMT
MB95F118BWPMT
48-pin plastic LQFP
(FPT-48P-M26)
MB95116BPMC
MB95F118BSPMC
MB95F118BWPMC
52-pin plastic LQFP
(FPT-52P-M01)
MB2146-301A
(MB95FV100D-101PBT)
62
Package
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
(
)
MB95110B Series
■ PACKAGE DIMENSIONS
48-pin plastic BCC
Lead pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm Max
Weight
0.06 g
(LCC-48P-M09)
48-pin plastic BCC
(LCC-48P-M09)
0.75±0.05
(.030±.002)
(Mount height)
7.00±0.10(.276±.004)
37
0.50(.020)
TYP
25
6.20(.244)TYP
0.50±0.10
(.020±.004)
25
37
0.50(.020)
TYP
7.00±0.10
(.276±.004)
6.20(.244)
TYP
6.15(.242)TYP
6.25(.246)
REF
5.00(.197)
REF
6.15(.242)
TYP
INDEX AREA
0.50±0.10
(.020±.004)
"A"
1
13
0.05(.002)
13 "C"
0.075±0.025
(.003±.001)
(Stand off)
Details of "A" part
8-0.60±0.06
(8-.024±.002)
0.14(.006)
MIN
C
"B"
5.00(.197)REF
1
6.25(.246)REF
Details of "C" part
Details of "B" part
0.65±0.06
(.026±.002)
0.30±0.06
(.012±.002)
2004 FUJITSU LIMITED C48062S-c-1-1
C0.2(.008)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
63
MB95110B Series
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
1
0.50(.020)
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
64
MB95110B Series
(Continued)
52-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Code
(Reference)
P-LQFP52-10×10-0.65
(FPT-52P-M01)
52-pin plastic LQFP
(FPT-52P-M01)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
39
27
40
26
Details of "A" part
0.10(.004)
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0˚~8˚
52
14
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
13
0.65(.026)
0.30
.012
C
+0.065
–0.035
+.0027
–.0014
0.13(.005)
M
2005 FUJITSU LIMITED F52001S-c-1-1
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
65
MB95110B Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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risks or dangers that, unless extremely high safety is secured, could
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reaction control in nuclear facility, aircraft flight control, air traffic
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Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
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over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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Edited
Business Promotion Dept.
F0612