GENNUM GS1574

GS1574 HD-LINX ™ II
Adaptive Cable Equalizer
GS1574 Preliminary Data Sheet
Features
Description
•
The GS1574 is a second-generation high-speed bipolar
integrated circuit designed to equalize and restore
signals received over 75Ω co-axial cable.
•
•
•
•
•
•
•
•
•
•
•
•
•
SMPTE 292M, SMPTE 344M and SMPTE 259M
compliant
Automatic cable equalization
Multi-standard operation from 143Mb/s to 1.485Gb/s
Supports DVB-ASI at 270Mb/s
Small footprint (4mm x 4mm)
Pb-free and Green
Pin compatible with the GS9074 Cable Equalizer
Manual bypass (useful for low data rates with slow
rise/fall times)
Performance optimized for 270Mb/s and 1.485Gb/s
Typical maximum equalized length of Belden 1694A
cable: 140m at 1.485Gb/s, 350m at 270Mb/s
50Ω differential output (with internal 50Ω pull-ups)
Manual output mute or programmable mute based on
max cable length adjust
Single 3.3V power supply operation
Operating temperature range: 0°C to +70°C
Applications
•
SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial
Cable Serial Digital Interfaces.
The GS1574 is designed to support SMPTE 292M,
SMPTE 344M and SMPTE 259M, and is optimized for
performance at 270Mb/s and 1.485Gb/s.
The GS1574 features DC restoration to compensate for
the DC content of SMPTE pathological test patterns.
A voltage programmable mute threshold (MCLADJ) is
included to allow muting of the GS1574 output when an
approximate selected cable length is reached for
SMPTE 259M signals. This feature allows the GS1574
to distinguish between low amplitude SD-SDI signals
and noise at the input of the device. The serial digital
outputs of the GS1574 may be forced to a mute state by
applying a voltage to the MUTE pin.
Power consumption is typically 270mW using a 3.3V
power supply. The GS1574 is lead-free, and the
encapsulation compound does not contain halogenated
flame retardant.
CABLE LENGTH ADJUSTOR
CARRIER DETECT
MUTE
MCLADJ
MUTE
BYPASS
SDI
SDI
EQUALIZER
DC RESTORE
OUTPUT
SDO
SDO
AGC
GS1574 Functional Block Diagram
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GS1574 Preliminary Data Sheet
Contents
Features ........................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................3
1.1 GS1574 Pin Assignment .................................................................................3
1.2 GS1574 Pin Descriptions ................................................................................4
2. Electrical Characteristics ...........................................................................................5
2.1 Absolute Maximum Ratings ............................................................................5
2.2 DC Electrical Characteristics ..........................................................................5
2.3 AC Electrical Characteristics ...........................................................................6
2.4 Solder Reflow Profiles .....................................................................................7
3. Input / Output Circuits ...............................................................................................9
4. Detailed Description ................................................................................................11
4.1 Serial Digital Inputs .......................................................................................11
4.2 Cable Equalization ........................................................................................11
4.3 Programmable Mute Output ..........................................................................12
4.4 Mute ..............................................................................................................12
5. Application Information............................................................................................13
5.1 PCB Layout ...................................................................................................13
5.2 Typical Application Circuit A .........................................................................13
5.3 Typical Application Circuit B .........................................................................14
6. Package & Ordering Information .............................................................................15
6.1 Package Dimensions ....................................................................................15
6.2 Land Information ...........................................................................................16
6.3 Packaging Data .............................................................................................16
6.4 Ordering Information .....................................................................................16
7. Revision History ......................................................................................................17
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GS1574 Preliminary Data Sheet
1. Pin Out
VEE_A
1
SDI
2
VCC_A
NC
MUTE
VCC_D
1.1 GS1574 Pin Assignment
16
15
14
13
12
VEE_D
11
SDO
3
10
SDO
4
9
GS1574
(top view)
6
7
VEE_D
8
MCLADJ
AGC
5
BYPASS
VEE_A
AGC
SDI
Center Pad
(bottom of package, internally
bonded to VEE_A)
Figure 1-1: 16-Pin QFN
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GS1574 Preliminary Data Sheet
1.2 GS1574 Pin Descriptions
Table 1-1: GS1574 Pin Descriptions
Pin Number
Name
Timing
Type
Description
1, 4
VEE_A
Analog
Power
Most negative power supply for analog circuitry.
Connect to analog GND.
2, 3
SDI, SDI
Analog
Input
5, 6
AGC, AGC
Analog
–
Serial digital differential input.
External AGC capacitor.
Connect pin 5 and pin 6 together through a 1uF capacitor.
7
BYPASS
Not
Synchronous
Input
8
MCLADJ
Analog
Input
Forces the Equalizing and DC RESTORE stages into bypass mode
when HIGH. No equalization occurs in this mode.
Maximum cable length adjust.
Adjusts the approximate maximum amount of cable to be equalized
(from 0m to the maximum cable length). The output is muted (latched to
the last state) when the maximum cable length is achieved.
NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.
9
VEE_D
Analog
Power
Most negative power supply for the digital circuitry and output buffer.
Connect to digital GND.
10, 11
SDO, SDO
Analog
Output
Equalized serial digital differential output.
12
VEE_D
Analog
Power
Most negative power supply for the digital circuitry and output buffer.
Connect to digital GND.
13
VCC_D
Analog
Power
Most positive power supply for the digital I/O pins of the device.
Connect to +3.3V DC.
14
MUTE
Not
Synchronous
Input
CONTROL SIGNAL INPUT
levels are LVCMOS/LVTTL compatible. (3.3V Tolerant)
When the MUTE pin is set HIGH by the application interface, the serial
digital output of the device will be forced to a steady state.
When the MUTE pin is set LOW, the serial digital output of the device
will be active.
15
NC
–
–
16
VCC_A
Analog
Power
No Connect.
Most positive power supply for the analog circuitry of the device.
Connect to +3.3V DC.
–
Center Pad
–
Power
Internally bonded to VEE_A.
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GS1574 Preliminary Data Sheet
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value
Supply Voltage
-0.5V to +3.6 VDC
Input ESD Voltage (Human Body Model)
500V
Storage Temperature Range
-50°C < Ts < 125°C
Input Voltage Range (any input)
-0.3 to (VCC +0.3)V
Operating Temperature Range
0°C to 70°C
Power Dissipation
300mW
Lead Temperature (soldering, 10 sec)
260°C
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VDD = 3.3V,
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Levels
Notes
Supply Voltage
VCC
–
3.135
3.3
3.465
V
–
±5%
Power Consumption
PD
TA = 25°C
–
265
–
mW
2
–
Supply Current
Is
TA = 25°C
–
80
–
mA
1
–
Output Common Mode
Voltage
VCMOUT
TA = 25°C
–
VCC - ∆VSDO/2
–
V
7
–
Input Common Mode
Voltage
VCMIN
TA = 25°C
–
1.75
–
V
8
–
Floating MCLADJ DC
Voltage
–
0m, TA = 25°C
–
1.3
–
V
7
–
MCLADJ Range
–
TA = 25°C
–
0.69
–
V
7
–
Mute Input Voltage
Required to Force Outputs
to Mute
VMute
Min to Mute
3.0
–
–
V
7
–
Mute Input Voltage
Required to Force Outputs
Active
VMute
Max to
Activate
–
–
2.0
V
7
–
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GS1574 Preliminary Data Sheet
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Levels
Notes
Serial input data rate
DRSDO
GS1574
143
–
1485
Mb/s
6
–
Input Voltage Swing
∆VSDI
TA =25°C, differential
720
800
950
mVp-p
2
1
Output Voltage Swing
∆VSDO
100Ω load, TA =25°C,
differential
–
750
–
mVp-p
1
–
Maximum Equalized
Cable Length
–
270Mb/s, Belden 1694A,
0.2UI Output Jitter
–
350
–
m
5
2
–
270Mb/s, Belden 8281,
0.2UI Output Jitter
–
280
–
m
2
2
–
540Mb/s, Belden 8281,
0.2UI Output Jitter
–
100
–
m
8
2
–
1.485Gb/s, Belden 1694A,
0.25UI Output Jitter
–
140
–
m
5
2
–
1.485Gb/s, Belden 8281,
0.25UI Output Jitter
–
100
–
m
2
2
Output Rise/Fall time
–
20% - 80%
–
80
220
ps
1
–
Mismatch in rise/fall time
–
–
–
–
30
ps
1
–
Duty cycle distortion
–
–
–
–
30
ps
1
1
Overshoot
–
–
–
–
10
%
7
–
Input Return Loss
–
–
15
–
–
dB
8
3
Input Resistance
–
single ended
–
1.64
–
kΩ
6
–
Input Capacitance
–
single ended
–
1
–
pF
6
–
Output Resistance
–
single ended
–
50
–
Ω
6
–
TEST LEVELS
NOTES:
1. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
1. 0m cable length.
2. Equalizer Pathological.
3. Tested on CB1574 board from 5MHz to 2GHz.
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GS1574 Preliminary Data Sheet
2.4 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. The recommended standard
eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 2-2.
60-150 sec.
Temperature
10-20 sec.
230˚C
220˚C
3˚C/sec max
183˚C
6˚C/sec max
150˚C
100˚C
25˚C
Time
120 sec. max
6 min. max
Figure 2-1: Standard Eutectic Solder Reflow Profile (Pb-free package)
Temperature
60-150 sec.
20-40 sec.
260˚C
250˚C
3˚C/sec max
217˚C
6˚C/sec max
200˚C
150˚C
25˚C
Time
60-180 sec. max
8 min. max
Figure 2-2: Maximum Pb-free Solder Reflow Profile (Pb-free package)
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GS1574 Preliminary Data Sheet
GigaBERT
1400
EXT. CLOCK DATA
CLOCK OUT
OUT
8281 or 1694A CABLE
50/75
IN
GS1574
TEST BOARD
OUT
CH. 1
OUT
CH. 2
EXT.
CLOCK
1.485GHz/270MHz
TDS 820
EXT. TRIGGER
Figure 2-3: Test Circuit
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GS1574 Preliminary Data Sheet
3. Input / Output Circuits
3k
3k
SDI
SDI
RC
3.6k
3.6k
Figure 3-1: Input Equivalent Circuit
VCC
12.0k
+
MCLADJ
-
150µ
Figure 3-2: MCLADJ Equivalent Circuit
50
50
SDO
SDO
Figure 3-3: Output Circuit
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GS1574 Preliminary Data Sheet
VCC
7.5k
OUTPUT
STAGE
MUTE
CONTROL
MUTE
Figure 3-4: MUTE Circuit
Bypass
Internal
Reference
Figure 3-5: Bypass Circuit
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GS1574 Preliminary Data Sheet
4. Detailed Description
The GS1574 is a high speed bipolar IC designed to equalize serial digital signals.
The GS1574 can equalize both HD and SD serial digital signals, and will typically
equalize greater than 140m of Belden 1694A cable at 1.485Gb/s and 350m at
270Mb/s.
The GS1574 is powered from a single +3.3V power supply and consumes
approximately 270mW of power.
4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is
recommended, as the SDI and SDI inputs are internally biased at approximately
1.8V.
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic. In addition,
the variation of the frequency response with control voltage imitates the variation
of the inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an
internal and an external AGC filter capacitor providing a steady control voltage for
the gain stage. As the frequency response of the gain stage is automatically varied
by the application of negative feedback, the edge energy of the equalized signal is
kept at a constant level which is representative of the original edge energy at the
transmitter. The equalized signal is also DC restored, effectively restoring the logic
threshold of the equalized signal to its correct level independent of shifts due to AC
coupling. The digital output signals have a nominal voltage of 750mVpp differential,
or 375mVpp single ended when terminated with 50Ω as shown in Figure 4-1.
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GS1574 Preliminary Data Sheet
+187.5mV
VCM = 2.925V
typical
SDO
-187.5mV
SDO
+187.5mV
50
50
VCM = 2.925V
typical
-187.5mV
Figure 4-1: Typical Output Voltage Levels
4.3 Programmable Mute Output
For SMPTE 259M inputs, the GS1574 incorporates a programmable threshold
output mute (MCLADJ).
In applications where there are multiple input channels using the GS1574, it is
advantageous to have a programmable mute output to avoid signal crosstalk.
The output of the GS1574 can be muted when the input signal decreases below a
certain input level. This threshold is determined using the input voltage applied to
the MCLADJ pin. The MCLADJ pin may be left unconnected for applications where
output muting is not required.
This feature has been designed for use in applications such as routers where
signal crosstalk and circuit noise cause the equalizer to output erroneous data
when no input signal is present. The use of a Carrier Detect function with a fixed
internal reference does not solve this problem since the signal to noise ratio on the
circuit board could be significantly less than the default signal detection level set by
the on chip reference.
NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.
4.4 Mute
In addition to the programmable mute output, the GS1574 includes a MUTE input
pin that allows the application interface to mute the serial digital output at any time.
Set the MUTE pin HIGH to mute SDO and SDO.
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GS1574 Preliminary Data Sheet
5. Application Information
5.1 PCB Layout
Special attention must be paid to component layout when designing serial digital
interfaces for HDTV. An FR-4 dielectric can be used, however, controlled
impedance transmission lines are required for PCB traces longer than
approximately 1cm. Note the following PCB artwork features used to optimize
performance:
•
PCB trace width for HD rate signals is closely matched to SMT component
width to minimize reflections due to change in trace impedance.
•
The PCB ground plane is removed under the GS1574 input components to
minimize parasitic capacitance.
•
The PCB ground plane is removed under the GS1574 output components to
minimize parasitic capacitance.
•
High speed traces are curved to minimize impedance changes.
5.2 Typical Application Circuit A
MUTE
VCC_A
VCC
13
VCC_D
1
MUTE
VCC_A
6.4n
10n
VEE_D
VEE_A
1u
2
SDO
SDI
75
12
+
4u7
SDO
11
GS1574
3
VEE_A
6
5
+
7
MCLADJ
37.5
BYPASS
4
75
SDO
SDI
AGC
1u
AGC
SDI
14
15
NC
16
10n
VEE_D
10
+
SDO
9
4u7
8
MCLADJ
1u
BYPASS
NOTE: All resistors in Ohms, capacitors in Farads,
and inductors in Henrys, unless otherwise noted.
Figure 5-1: GS1574 Typical Application Circuit
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GS1574 Preliminary Data Sheet
5.3 Typical Application Circuit B
This application circuit should be used for future compatibility with the GS1574A.
This circuit will work with GS1574 as well as the GS1574A and is recommended
for all new designs.
CD
MUTE
VCC_A
VCC
13
VCC_D
1
MUTE
6.4n
1u
10n
VEE_D
VEE_A
2
SDO
SDI
75
12
+
4u7
SDO
11
GS1574A
3
VEE_A
5
6
MCLADJ
37.5
BYPASS
4
75
SDO
SDI
AGC
1u
AGC
SDI
14
15
CD
VCC_A
16
10n
7
VEE_D
10
+
SDO
9
4u7
8
MCLADJ
470n*
470n*
BYPASS
* Value subject to change.
NOTE: All resistors in Ohms, capacitors in Farads,
and inductors in Henrys, unless otherwise noted.
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GS1574 Preliminary Data Sheet
6. Package & Ordering Information
6.1 Package Dimensions
0.40+/-0.05
2.76+/-0.10
4.00
DATUM A
2.76+/-0.10
B
4.00
PIN 1 AREA
CENTER TAB
DETAIL B
2X
0.15 C
2X
0.000.350.05
DATUM B
0.15 C
0.65
0.20 REF
16X
0.10 C
0.10
CAB
0.05
C
DATUM A OR B
16X
0.08 C
SEATING PLANE
0.65/2
TERMINAL TIP
0.90+/-0.10
+0.03
0.02-0.02
0.65
DETAIL B
SCALE:NTS
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GS1574 Preliminary Data Sheet
6.2 Land Information
0.35
0.65
0.55
3.70
2.75
CENTER PAD
NOTE: All dimensions
are in millimeters.
2.75
3.70
The Center Pad should be connected to the most negative power supply plane for
analog circuitry in the device (VEE_A) by a minimum of 5 vias.
NOTE: Suggested dimensions only. Final dimensions should conform to customer
design rules and process optimizations.
6.3 Packaging Data
Parameter
Value
Package Type
4mm x 4mm 16-pin QFN
Package Drawing Reference
JEDEC M0220
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance, θj-c
31.0°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow)
43.8°C/W
Psi
11.0°C/W
Pb-free and Green
Yes
6.4 Ordering Information
Part Number
Package
Temperature Range
GS1574-CNE3
Pb-free 16-pin QFN
0°C to 70°C
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GS1574 Preliminary Data Sheet
7. Revision History
Version
ECR
Date
Changes and/or Modifications
B
133285
March 2004
Updated AIN to include information on the GS9074.
0
134166
August 2004
Upgrade to preliminary data sheet. Remove all
information on the GS9074. Expand detailed
description information. AC/DC parameters updated.
Add Pb-free and conventional solder reflow profiles.
Edit pin descriptions.
1
134891
November 2004
Added packaging data section. Added Pad Layout
information. Updated Packaging Dimensions
diagram. Corrected minor typing errors.
2
135370
December 2004
Added Typical Application Circuit section with
application information for future drop-in compatibility
with GS1574A part.
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change without notice.
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku,
Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
TEL. +44 (0)1252 747 000 FAX +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein
and makes no representations that they are free from patent infringement.
© Copyright March 2004 Gennum Corporation. All rights reserved.
Printed in Canada
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