GENNUM GS1504

HD-LINX ™ GS1504
HDTV Adaptive Equalizer
PRELIMINARY DATA SHEET
DESCRIPTION
• SMPTE 292M compliant
The GS1504 is a high performance cable equalizer
designed to equalize HDTV component signal conforming
to SMPTE 292M. The adaptive cable equalizer is capable of
equalizing up to 100m of Belden 8281 co-axial cable.
• Automatic, adjustment free cable equalization for
1.485Gb/s HDTV signals
• Differential serial outputs capable of driving 50Ω loads
The GS1504 features DC restoration for immunity to the DC
content in pathological test patterns. The device also
incorporates a Cable Length Indicator signal that provides
an indication of the amount of cable being equalized.
• Typically equalizes 100m of Belden 8281 or 150m of
Belden 1694 high quality co-axial cable
• Cable Length Indication
• Output Mute
• Maximum Cable Length Adjust
• Low power
• Minimal external components
• Single +5V or -5V power supply operation
APPLICATIONS
1.485Gb/s HDTV Serial Digital Receiver Interfaces for
Routers, Distribution Amplifiers, Switchers, and other
receiving equipment.
A voltage programmable mute threshold (MCLADJ) is
included to allow muting of the GS1504 output when a
selected cable length is reached. This feature allows the
GS1504 to distinguish between low amplitude HD SDI
signals and noise at the input of the device. The CD/Mute
pin provides an indication of the GS1504 mute status in
addition to functioning as a mute control input. The output
of the GS1504 may be forced to an active or a mute
condition by applying a voltage to the CD/Mute pin.
The GS1504 is a low power device that operates from a
single 5V power supply. The GS1504 is packaged in a
16 pin narrow SOIC and does not need external pull-up
resistors.
ORDERING INFORMATION
MCLADJ
PACKAGE
TEMPERATURE
GS1504-CKD
16 pin narrow SOIC
0°C to 70°C
GS1504-CTD
16 pin Tape and Reel
0°C to 70°C
CABLE LENGTH INDICATOR/ADJUSTOR
CARRIER DETECT
MUTE
SDI
SDI
PART NUMBER
DC
RESTORE
EQUALIZER
CLI
CD/MUTE
SDO
OUTPUT
SDO
AGC
PATENT PENDING
BLOCK DIAGRAM
Revision Date: March 2000
Document No. 522 - 05 - 02
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS1504
FEATURES
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise indicated
PARAMETER
VALUE
Supply Voltage
5.5V
Input Voltage Range (any input)
-0.3 to (VCC +0.3)V
GS1504
Operating Temperature Range
0°C to 70°C
Storage Temperature
-65°C to 150°C
Power Dissipation
300mW
Lead Temperature (soldering, 10 sec)
260°C
Input ESD Voltage
2000V
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0°C to 70°C, Data Rate = 1.485Gb/s
SYMBOL
MIN
TYP
MAX
UNITS
TEST
LEVELS
VCC
4.75
5.00
5.25
V
1
Power Consumption
-
250
-
mW
1
Supply Current
-
50
65.0
mA
1
3.75
4
4.25
V
1
PARAMETER
CONDITIONS
Positive Supply Voltage
Output CM Voltage
Input DC Voltage
Internal Bias. See Figure 2
-
2.7
-
V
1
CLI DC Voltage (0m)
CLI Output for 0m Cable
-
3.3
-
V
4
0.9
1.3
1.7
V
1
-
2
-
V
2
2.80
3.1
3.4
V
1
V
2
V
1
CLI DC Voltage (no signal input)
Cable Length Indicator Range
0 - Max m
MCLADJ DC Voltage
MCLADJ Input Voltage
Required to Mute Output
MCLADJ Range
(max cable to 0m)
Mute DC Voltage
Output Voltage of CD/Mute
when Output is Active
Voltage Required to Force Outputs to Mute
Min to Mute; VCD/Mute
4.2
V
2
Voltage Required to Force Outputs Active
Max to Activate; VCD/Mute
3.8
V
2
TEST LEVELS: 1. 100% tested at 25°C.
CLI
1
2. Guaranteed by design.
1.5
3. Correlated Value.
GigaBERT
1400
4. Using EB1504
8281 or 1694A CABLE
IN
50/75
2k
CLI
GS1504
EVAL. BOARD
MCLADJ
10k
15k
Fig. 1 Test Setup
2
522 - 05 - 02
2.1
DVM
EXT. CLOCK DATA
CLOCK OUT
OUT
EXT.
CLOCK
1.485GHz
1.8
OUT
CH. 1
OUT
CH. 2
TDS 820
EXT. TRIGGER
AC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0°C to 70°C, Data Rate = 1.485Gb/s
TYP
MAX
UNITS
TEST
LEVEL
100m (8281), PRN and pathological
-
80
135
ps p-p
1
Belden 8281
-
100
-
m
1
Belden 1694
-
150
-
m
3
20% - 80%
-
130
270
ps
1
Input Resistance
Single Ended
-
2.8
.
kΩ
2
Input Capacitance
Single Ended
-
1
-
pF
2
Output Resistance
Single Ended
-
50
-
Ω
2
Into 50Ω Loads; See Figure 21.
160
200
240
mVp-p
1
CONDITIONS
Jitter
Equalization
Output Rise/Fall Time
Output Signal Swing SDO, SDO
TEST LEVELS: 1. 100% tested at 25°C.
SYMBOL
2. Guaranteed by design.
3. Correlated Value.
4. Using EB1504
PIN CONNECTIONS
CLI
1
16
CD/MUTE
VCC
2
15
VCC
VEE
3
14
VEE
13
SDO
12
SDO
GS1504
TOP
VIEW
SDI
4
SDI
5
VEE
6
11
VEE
MCLADJ
7
10
NC
NC
8
9
NC
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1
CLI
O
Cable Length Indication. Provides a voltage output representing the amount of cable being
equalized. See figures 19 and 20. The CLI voltage is an approximation of the cable length
being equalized. It is intended as a guide for troubleshooting the initial design and not as an
accurate indication of cable length.
2, 15
VCC
I
Most positive supply voltage.
3, 6, 11, 14
VEE
I
Most negative supply voltage.
4, 5
SDI, SDI
I
Differential Input Pins. AC coupled termination is recommended.
7
MCLADJ
I
Adjusts the maximum amount of cable to be equalized (from 0m to the maximum cable
length). The output is muted (latched to the last state) when the maximum cable length is
reached. To achieve maximum cable length, this pin should be left open. See figures 10 - 12.
8, 9, 10
NC
-
No Connect. Do not connect these pins to supply or ground.
12, 13
SDO, SDO
O
Differential Serial Data Output Pins, with 50Ω output resistance.
16
CD/Mute
I/O
Carrier Detect/Mute Indicator/Control. When the CD/Mute output is low, the carrier is present
and the data output is active. When the CD/Mute output is high, the carrier is not present and
the data output is muted (latched to the last state). This indicates that the maximum cable
length as set by MCLADJ has been reached.
The above default CD/Mute function can be overwritten as follows: if the CD/Mute pin is tied
to ground the data output will not mute and the MCLADJ setting is overwritten. If the mute pin
is tied high, the data output will always mute and the MCLADJ setting is overwritten.
3
522 - 05 - 02
GS1504
MIN
PARAMETER
INPUT/OUTPUT CIRCUITS
All resistors in ohms, all capacitors in farads, unless otherwise shown.
GS1504
VCC
10k
6k
6k
SDI
SDI
10k
RC
7k
7k
-
CLI
+
Fig. 2 Input Equivalent Circuit
Fig. 5 CLI Output Circuit
VCC
VCC
40k
20k
OUTPUT
STAGE
+
MCLADJ
CD/MUTE
MUTE
CONTROL
-
10k
42µ
Fig. 3 MCLADJ Equivalent Circuit
50
Fig. 6 CD/Mute Circuit
50
SDO
SDO
Fig. 4 Output Circuit
4
522 - 05 - 02
TYPICAL PERFORMANCE CURVES (unless otherwise shown, VCC = 5V, TA = 25°C)
300
250
200
GS1504
POWER CONSUMPTION (mW)
350
MCLADJ
150
MCLADJ
100
50
0
0
20
40
60
Uncompensated
MCLADJ
80
Temperature Compensated
MCLADJ
TEMPERATURE (˚C)
Fig. 7 Power Consumption
Fig. 10 Temperature Compensation of MCLADJ
800
102
700
100
98
CABLE LENGTH (m)
JITTER (ps)
600
500
400
300
200
96
Compensated
94
92
90
Uncompensated
88
100
86
84
0
0
50
100
150
200
0
20
CABLE LENGTH (m)
60
80
TEMPERATURE (˚C)
23
Fig. 8 Typical Peak to Peak Jitter, PRN 2 -1, Belden 1694A
Fig. 11 Typical 1694A Cable Length vs. Temperature
(%)
800
90
CC
VOLTAGE NORMALIZED TO V
700
600
JITTER (ps)
40
500
400
300
200
100
80
70
60
50
40
30
20
10
0
0
50
100
150
0
200
CABLE LENGTH (m)
0
50
100
150
200
CABLE LENGTH (m)
23
Fig. 9 Typical Peak to Peak Jitter, PRN 2 -1, Belden 8281
Fig. 12 MCLADJ Input Voltage vs 1694A Cable Length
5
522 - 05 - 02
GS1504
TYPICAL PERFORMANCE CURVES (unless otherwise shown VCC = 5V, TA = 25°C)
Fig. 13 Input 100m (Belden 1694A)
Fig. 16 Output 150m (Belden 1694A)
50
40
30
20
10
0
-10
-20
-30
-40
-50
0.05 GHz
Fig. 14 Output 100m (Belden 1694A)
1 GHz
2 GHz
Fig. 17 Input Return Loss
OUTPUT SIGNAL SWING (mV)
500
400
300
200
100
0
0
20
40
60
TEMPERATURE (˚C)
Fig. 15 Input 150m (Belden 1694A)
Fig. 18 Output Signal Swing, p-p, Differential
6
522 - 05 - 02
80
CLI VOLTAGE (V)
3
2.5
2
1.5
1
0.5
0
0
50
100
150
200
+100mV
CABLE LENGTH (m)
VCM = 4.0V
typical
Fig. 19 CLI Voltage vs. Belden 1694A Cable Length
SDO
-100mV
SDO
+100mV
3.5
CLI VOLTAGE (V)
3
2.5
50
50
2
VCM = 4.0V
typical
-100mV
1.5
1
Fig. 21 Typical Output Voltage Levels
0.5
0
0
50
100
CABLE LENGTH INDICATION/CARRIER DETECT/MUTE
150
The GS1504 incorporates a versatile analog cable length
indicator (CLI) output and a programmable threshold output
mute (MCLADJ). In addition, a multi-function CD/MUTE pin
allows control of the GS1504 MUTE functionality.
CABLE LENGTH (m)
Fig. 20 CLI Voltage vs. Belden 8281 Cable Length
DETAILED DESCRIPTION
The voltage output of CLI pin is an approximation of the
amount of cable present at the GS1504 input. The CLI
voltage versus cable length (signal strength) is shown in
Figures 19 and 20. With 0m of cable (800mV input signal
levels), the CLI output voltage is approximately 3.3V. As the
cable length increases, the CLI voltage decreases
providing an approximate correlation between the CLI
voltage and cable length.
The GS1504 is a high speed bipolar IC designed to
equalize HD serial digital data at a rate of 1.485Gb/s. The
device can typically equalize greater than 100 meters of
Belden 8281 cable or 150 meters of Belden 1694 cable.
Powered from a single +5V or -5V power supply, the device
consumes approximately 250mW of power
The HD serial data signal may be connected to the input
pins (SDI/SDI) in either a differential or single ended
configuration. AC coupling of the inputs is recommended,
as the SDI and SDI inputs are internally biased at
approximately 2.7 volts. The input signal passes through a
variable gain equalizing stage whose frequency response
closely matches the inverse cable loss characteristic. In
addition, the variation of the frequency response with
control voltage imitates the variation of the inverse cable
loss characteristic with cable length.
In applications where there are multiple input channels
using the GS1504, it is advantageous to have a
programmable mute output.
The output of the GS1504 can be muted when the input
signal decreases below a preselected input level. The
voltage applied to the MCLADJ pin vs input cable length is
shown in Figure 12. The MCLADJ pin may be left
unconnected for applications where output muting is not
required. This feature has been designed for use in
applications such as routers where signal crosstalk and
circuit noise cause the equalizer to output erroneous data
when no input signal is present. The use of a Carrier Detect
function with a fixed internal reference does not solve this
problem since the signal to noise ratio on the circuit board
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an internal AGC filter capacitor providing a
7
522 - 05 - 02
GS1504
steady control voltage for the gain stage. As the frequency
response of the gain stage is automatically varied by the
application of negative feedback, the edge energy of the
equalized signal is kept at a constant level which is
representative of the original edge energy at the transmitter.
The equalized signal is also DC restored, effectively
restoring the logic threshold of the equalized signal to its
correct level independent of shifts due to AC coupling. The
digital output signals have a nominal voltage of 400mVpp
differential, or 200mVpp single ended when terminated with
50Ω as shown in Figure 21.
3.5
could be significantly less than the default signal detection
level set by the on chip reference.
•
Applying a LOW INPUT to the CD/Mute pin will force the
GS1504 outputs to remain active regardless of the
length of input cable and the voltage applied to the
MCLADJ pin. See the DC electrical characteristics table
for voltage level.
•
When used as an OUTPUT, the CD/Mute pin will provide
an indication of the output mute status. The CD/Mute pin
will be logic HIGH when the output is muted, and logic
LOW when the outputs are not muted.
The CD/Mute pin is a multi-function bidirectional pin that
provides the following functions:
GS1504
•
Applying a HIGH INPUT to the CD/Mute pin forces the
GS1504 outputs to a muted condition. See the DC
electrical characteristics table for voltage level. In this
condition the outputs will be latched to the last logic
level present at the output.
TYPICAL APPLICATION CIRCUIT
VCC
VCC
1
75
16
CLI
CD/MUTE
2
10n
3
10nH
47p
4
VCC
VCC
VEE
VEE
SDI
75
5
GS1504
SDI
47p
SDO
6
37.5
7
10n
1
2
J3
VCC
SDO
VEE
VEE
MCLADJ
NC
NC
NC
8
2k
10n
15
14
13
+ 4µ7
12
+
4µ7
11
10
10n
9
VCC
VCC
10k
1µ
100n
1n
15k
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
8
522 - 05 - 02
APPLICATION INFORMATION
PCB LAYOUT
•
•
The PCB ground plane is removed under the GS1504
input components to minimize parasitic capacitance.
•
The PCB ground plane is removed under the GS1504
output components to minimize parasitic capacitance.
•
High speed traces are curved to minimize impedance
changes.
A picture of the GS1504 PCB assembly is shown in Figure
28.
PCB trace width for HD rate signals is closely matched
to SMT component width to minimize reflections due to
change in trace impedance.
GS1504 EVALUATION BOARD
J5
VCC
R1
75
1
10n
C6
L4
J1
10nH
R4
75
37
R2
2
3
47p
C7
C8
47p
4
5
6
10n
C5
7
8
J4
VCC
TP1
CLI
CD/MUTE
VCC
VCC
VEE
VEE
SDI
SDO
SDI
SDO
VEE
VEE
MCLADJ
NC
NC
NC
2k
R5
16
C3
10n
15
14
4.7µ
13
12
+ C1
+ C2
11
4.7µ
10
10n
C4
9
J3
C1, C2 must be tantalum
capacitors.
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
VCC
VCC
J2
10k
R3
C10
1µ
15k
R6
C9
100n
C11
1n
Fig. 22 GS1504 Application Schematic
9
522 - 05 - 02
GS1504
Special attention must be paid to component layout when
designing serial digital interfaces for HDTV. Figures 23
through 27 show the artwork for a four layer printed circuit
evaluation board for the GS1504. The schematic is shown in
Figure 22. An FR-4 dielectric can be used, however,
controlled impedance transmission lines are required for
PCB traces longer than approximately 1cm. Note the
following PCB artwork features used to optimize
performance:
GS1504
Fig. 23 Silk Screen of EB1504 PCB Layout
Fig. 26 Bottom Layer of EB1504 PCB Layout
Fig. 24 Top Layer of EB1504 PCB Layout
Fig. 27 Power Layer of EB1504 PCB Layout
Fig. 25 Ground Layer of EB1504 PCB Layout
Fig. 28 Photograph of GS1504 Evaluation Board
10
522 - 05 - 02
GS1504 / GS1508 INTERFACING
•
PCB trace width for HD rate signals is closely matched
to SMT component width to minimize reflections due to
change in trace impedance.
•
The PCB ground plane is removed under the
GS1504/GS1508 input components to minimize
parasitic capacitance.
•
The PCB ground plane is removed under the
GS1504/GS1508 output components to minimize
parasitic capacitance.
•
High speed traces are curved to minimize impedance
changes.
A picture of the GS1504/08 PCB assembly is shown in
Figure 34.
VCC
TP1
C1
1µ
VCC
C2
100n
C3
1n
TP2
GND
VCC
C6
10n
J2
VIDEO IN
R16
75
L4 10n
R1
75
TP3
CLI
CC
3 V
EE
4 SDI
5 SDI
6 V
EE
C5
10n
R15
37.5
CLOSE
TO
MUTE
J1
1 CLI
2 V
C7
47p
C8
47p
C16
1n
R8
75
7 MCLADJ
8 nc
16
CD/MUTE
15
V
CC
VEE
VCC
VCC
R7
75
R8
75
C20
10n
14
SDO 8
SDI
2
SDO 7
SDI
3
GND 6
VEE
5
4
V
RSET CC
1
11
10
nc
9
nc
C4
10n
VCC
R11
53.6
C15
10n
L2 12n
R9
75
C17
1p
R7
75
U2
13
SDO
12
SDO
VEE
C10
100n
VCC
J4
SDO
EDGEMNT_BNC
J5
C12 4µ7
SDO
EDGEMNT_BNC
C11
C18
1p
R10
75
GS1508
L3 12n
2
4µ7
C11 AND C12 ARE
TC3216 TANTALUM
CAPACITORS.
J3
1
VCC
R4
2k
R5
10k
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
R6
15k
Fig. 29 GS1504/08 Evaluation Board Assembly
11
522 - 05 - 02
GS1504
Figures 30 through 34 show the artwork for a four layer
printed circuit evaluation board for the GS1504. The
schematic is shown in Fig 29. An FR-4 dielectric can be
used, however, controlled impedance transmission lines are
required for PCB traces longer than approximately 1cm.
Note the following PCB artwork features used to optimize
performance:
GS1504
Fig. 30 Top Layer of EB1504/08 PCB Layout
Fig. 32 Ground Layer of EB1504/08 PCB Layout
Fig. 31 Power Layer of EB1504/08 PCB Layout
Fig. 33 Bottom Layer of EB1504/08 PCB Layout
Fig. 34 Photograph of GS1504/GS1508 Evaluation Board
REVISION NOTES:
Updated ordering information, absolute maximum ratings, and
pin descriptions; Replaced 1504/08 Evaluation Board
assembly artwork, layouts, and photograph.
For the latest product information, visit www.gennum.com
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
This product is in production. Gennum reserves the right to make
changes to the product and to the documentation.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright August 1998 Gennum Corporation. All rights reserved. Printed in Canada.
522 - 05 - 02
12