GMT G1427F31U

G1427
Global Mixed-mode Technology Inc.
2W Stereo Audio Amplifier
6dB\10dB\15.6dB\21.6dB Selectable Gain Settings
Features
General Description
„
G1427 is a stereo audio power amplifier in 24pin
TSSOP thermal pad package. It can drive 2.0W continuous RMS power into 4Ω load per channel in
Bridge-Tied Load (BTL) mode at 5V supply voltage. Its
THD is smaller than 1% under the above operation
condition. To simplify the audio system design in the
notebook application, G1427 supports the Bridge-Tied
Load (BTL) mode for driving the speakers, Single-End
(SE) mode for driving the headphone. For the low
current consumption applications, the SHDN mode is
supported to disable G1427 when it is idle. The current
consumption can be reduced to 160µA (typically).
„
„
„
„
„
„
„
„
Internal Gain Control, Which Eliminates External Gain-Setting Resistors
Depop Circuitry Integrated
Output Power at 1% THD+N, VDD=5V
--2.0W/CH (typical) into a 4Ω Load
--1.2W/CH (typical) into a 8Ω Load
Bridge-Tied Load (BTL), Single-Ended (SE)
Stereo Input MUX
PC-Beep Input
Fully differential Input
Shutdown Control Available
Surface-Mount Power Package
24-Pin TSSOP-P
Amplifier gain is internally configured and controlled by
two terminals (GAIN0, GAIN1). BTL gain settings of
6dB, 10dB, 15.6dB, 21.6dB are provided, while SE
gain is always configured as 4.1dB (inverting) for
headphone driving. G1427 also supports two input
paths, that means two different amplitude AC signals
can be applied and chosen by setting HP/ LINE pin. It
enhances the hardware designing flexibility.
Applications
„
Stereo Power Amplifiers for Notebooks or
Desktop Computers
„ Multimedia Monitors
„ Stereo Power Amplifiers for Portable Audio
Systems
Ordering Information
ORDER
NUMBER
ORDER NUMBER
(Pb free)
TEMP.
RANGE
PACKAGE
G1427F31U
G1427F31Uf
-40°C to +85°C
TSSOP-24 (FD)
Note: U:Tape & Reel
(FD): Thermal Pad
Pin Configuration
G1427
GND/HS
GND/HS
1
24
GAIN0
2
23
RLINEIN
GAIN1
3
22
SHUTDOWN
LOUT+
4
21
ROUT+
LLINEIN
20
RHPIN
LPHIN
5
6
19
VDD
PVDD
7
18
PVDD
HP/LINE
RIN
8
17
LOUT-
9
16
ROUT-
LIN
BYPASS
10
11
15
14
SE/BTL
PC-BEEP
GND/HS 12
13
GND/HS
Thermal
Pad
Top View
TSSOP-24
Bottom View
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.3
Sep 23, 2005
1
G1427
Global Mixed-mode Technology Inc.
Absolute Maximum Ratings
Power Dissipation (1)
TA ≤ 25°C ………...….…………………………..2.7W
TA ≤ 70°C ………...….…………………………..1.7W
Electrostatic Discharge, VESD
Human body mode..…………………….…………3000(2)
Supply Voltage, VCC…………………..…..…….….…...6V
Operating Ambient Temperature Range
TA…….…………………………….……….-40°C to +85°C
Maximum Junction Temperature, TJ…..……….….150°C
Storage Temperature Range, TSTG….…-65°C to+150°C
Reflow Temperature (soldering, 10sec)……..……260°C
Note:
(1)
: Recommended PCB Layout
(2)
: Human body model : C = 100pF, R = 1500Ω, 3 positive pulses plus 3 negative pulses
Electrical Characteristics
DC Electrical Characteristics, TA=+25°C
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
4.5
5
5.5
V
2
---
---
V
SE/ BTL , HP/ LINE , SHUTDOWN , GAIN0,
---
---
0.8
V
GAIN1
VDD = 5V,Gain = 2
---
mV
Supply voltage VDD
High-Level Input voltage, VIH
VDD
VIH
SE/ BTL , HP/ LINE , SHUTDOWN , GAIN0,
Low-Level Input voltage, VIL
VIL
GAIN1
DC Differential Output Voltage
VO(DIFF)
Supply Current in Mute Mode
IDD
VDD = 5V
IDD in Shutdown
ISD
VDD = 5V
Stereo BTL
Stereo SE
-----
5
50
7.5
13
4
160
7
300
mA
µA
(AC Operation Characteristics, VDD = 5.0V, TA=+25°C, RL = 4Ω, unless otherwise noted)
PARAMETER
Output power (each channel) see Note
SYMBOL
P(OUT)
Total harmonic distortion plus noise
THD+N
Maximum output power bandwidth
BOM
Power supply ripple rejection
PSRR
Channel-to-channel output separation
Line/HP input separation
BTL attenuation in SE mode
Input impedance
Signal-to-noise ratio
Output noise voltage
MIN
TYP
MAX
THD = 1%, BTL, RL = 4Ω G=-2V/V
CONDITION
---
2
---
THD = 1%, BTL, RL = 8Ω G=-2V/V
---
1.25
---
THD = 10%, BTL, RL = 4Ω G=-2V/V
THD = 10%, BTL, RL = 8Ω G=-2V/V
THD = 0.1%, SE, RL = 32Ω
PO = 1.6W, BTL, RL = 4Ω G=-2V/V
-------------
2.5
1.6
85
100
60
80
-------------
PO = 1W, BTL, RL = 8Ω G=-2V/V
PO = 75mW, SE, RL = 32Ω
VI = 1V, RL = 10KΩ, SE
THD = 5%
F=1kHz, BTL mode G=-2V/V
CBYP=1µF
f = 1kHz
Vn
PO = 500mW, BTL, G=-2V/V
BTL, G=-2V/V, A Weighted filter
W
mW
m%
---
30
---
-----
>15
68
-----
kHz
dB
---
80
---
dB
-----
dB
dB
MΩ
-----
dB
µV (rms)
----ZI
UNIT
80
85
See Table 2
--90
--45
Note :Output power is measured at the output terminals of the IC at 1kHz.
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.3
Sep 23, 2005
2
G1427
Global Mixed-mode Technology Inc.
Typical Characteristics
Table of Graphs
FIGURE
vs Frequency
vs Output Power
1,2,7,8,13,14,19,21
3,4,5,6,9,10,11,12,15,16,17,18,20
Output Noise Voltage
vs Output Voltage
vs Frequency
22
27
Vn
Supply Ripple Rejection Ratio
vs Frequency
23,24
PO
PD
Crosstalk
Output Power
Power Dissipation
vs Frequency
vs Load Resistance
vs Output Power
25,26
28,29
30,31
THD +N Total Harmonic Distortion Plus
Noise
Total Harmonic Distortion Plus
Noise vs Output Frequency
Total Harmonic Distortion Plus
Noise vs Output Frequency
10
5
2
1
10
VDD=5V
RL=3Ω
BTL
Po=1.75W
5
Av=21.6dB
2
VDD=5V
RL=3Ω
BTL,Av=6dB
1
Av=15.6dB
0.5
Po=0.5W
0.5
%
%
0.2
0.2
0.1
0.1
0.0 5
Po=1W
0.05
Av=10dB
Av=6dB
0.0 2
0.02
0.0 1
20
0.01
20
50
100
200
50 0
1k
2k
5k
10k
2 0k
Po=1.5W
50
100
20 0
5 00
Hz
2k
5k
10k
Figure 1
Figure 2
Total Harmonic Distortion Plus
Noise vs Output Power
Total Harmonic Distortion Plus
Noise vs Output Power
10
20 k
10
VDD=5V
RL=3Ω
BTL,Av=6dB
15kHz
5
2
VDD=5V
RL=3Ω
BTL,Av=10dB
15kHz
5
2
1
1
0.5
0.5
%
1kHz
%
1kHz
0.2
0.2
0.1
0.1
0.05
0.0 5
20Hz
0.02
0.01
3m
1k
Hz
20Hz
0.0 2
5m
10m
20m
50 m
100m
200 m
50 0m
1
2
0.0 1
3m
3
W
5m
10m
20m
50 m
100m
200m
500m
1
2
3
W
Figure 3
Figure 4
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.3
Sep 23, 2005
3
G1427
Global Mixed-mode Technology Inc.
Total Harmonic Distortion Plus
Noise vs Output Power
Total Harmonic Distortion Plus
Noise vs Output Power
10
10
5
2
2
1
1
0.5
0.5
1kHz
%
0.2
0.1
0.02
0.01
3m
1kHz
%
0.2
0.05
15kHz
5
15kHz
0.1
VDD=5V
RL=3Ω
BTL,Av=15.6dB
5m
10m
20m
20Hz
0.05
0.02
50 m
100m
200 m
50 0m
1
2
0.01
3m
3
5m
1
50 m
200 m
Figure 6
50 0m
1
2
3
Total Harmonic Distortion Plus
Noise vs Frequency
10
5
Av=21.6dB
2
VDD=5V
RL=4Ω
BTL,Av=6dB
1
0.5
0.5
Av=15.6dB
Po=0.25W
%
0.2
0.2
Av=6dB
0.1
Po=1.5W
0.1
0.0 5
0.05
Av=10dB
0.0 1
20
50
0.02
100
200
50 0
1k
2k
5k
10k
Po=1W
0.01
20
2 0k
50
100
20 0
5 00
Hz
1k
2k
5k
10k
20 k
Hz
Figure 7
Figure 8
Total Harmonic Distortion Plus
Noise vs Output Power
Total Harmonic Distortion Plus
Noise vs Output Power
10
10
5
VDD=5V
RL=4Ω
BTL,Av=6dB
15kHz
2
5
VDD=5V
RL=4Ω
BTL,Av=10dB
15kHz
2
1
1
0.5
0.5
1kHz
%
1kHz
%
0.2
0.2
0.1
0.1
0.05
0.0 5
20Hz
20Hz
0.02
0.01
3m
100m
Figure 5
VDD=5V
RL=4Ω
BTL
Po=1.75W
%
0.0 2
20m
W
10
2
10m
W
Total Harmonic Distortion Plus
Noise vs Frequency
5
20Hz
VDD=5V
RL=3Ω
BTL,Av=21.6dB
0.0 2
5m
10m
20m
50 m
100m
200 m
50 0m
1
2
0.0 1
3m
3
W
5m
10m
20m
50 m
100m
200m
500m
1
2
3
W
Figure 9
Figure 10
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.3
Sep 23, 2005
4
G1427
Global Mixed-mode Technology Inc.
Total Harmonic Distortion Plus
Noise vs Output Power
Total Harmonic Distortion Plus
Noise vs Output Power
10
10
15kHz
5
5
15kHz
2
2
1kHz
1
1
1kHz
0.5
0.5
%
%
0.2
0.2
0.05
0.02
0.01
3m
20Hz
0.1
0.1
VDD=5V
RL=4Ω
BTL,Av=15.6dB
5m
10m
20m
0.05
20Hz
0.02
50 m
100m
200 m
50 0m
1
2
0.01
3m
3
VDD=5V
RL=4Ω
BTL,Av=21.6dB
5m
10m
20m
50 m
100m
2
1
Figure 12
Total Harmonic Distortion Plus
Noise vs Frequency
Total Harmonic Distortion Plus
Noise vs Frequency
2
3
10
VDD=5V
RL=8Ω
BTL,Av=6dB
5
2
1
1
0.5
0.5
%
Po=0.25W
0.2
0.1
50 0m
Figure 11
10
5
200 m
W
W
VDD=5V
RL=8Ω
BTL
Po=1W
Av=15.6dB
%
0.2
Av=21.6dB
0.1
Po=1W
0.05
Av=6dB
0.0 5
Po=0.5W
0.02
0.01
20
50
100
20 0
5 00
1k
Av=10dB
0.0 2
2k
5k
10k
0.0 1
20
20 k
50
100
200
50 0
1k
2k
Hz
Hz
Figure 13
Figure 14
5k
10k
2 0k
Total Harmonic Distortion Plus
Noise vs Output Power
Total Harmonic Distortion Plus
Noise vs Output Power
10
10
VDD=5V
RL=8Ω
BTL,Av=6dB
5
15kHz
2
VDD=5V
RL=8Ω
BTL,Av=10dB
5
15kHz
2
1
1
0.5
0.5
%
%
0.2
0.2
1kHz
1kHz
0.1
0.1
0.05
0.0 5
20Hz
0.02
0.01
3m
5m
10m
20Hz
0.0 2
20m
50 m
100m
200 m
50 0m
1
2
0.0 1
3m
3
5m
10m
20m
50 m
100m
200m
W
W
Figure 15
Figure 16
500m
1
2
3
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.3
Sep 23, 2005
5
G1427
Global Mixed-mode Technology Inc.
Total Harmonic Distortion Plus
Noise vs Output Power
Total Harmonic Distortion Plus
Noise vs Output Power
10
10
5
VDD=5V
RL=8Ω
BTL,Av=15.6dB
15kHz
2
5
15kHz
2
1
1
0.5
0.5
1kHz
%
1kHz
%
0.2
0.2
0.1
0.1
20Hz
0.05
0.05
0.02
0.01
3m
0.02
5m
10m
20m
50 m
100m
200 m
50 0m
1
2
0.01
3m
3
5
VDD=5V
RL=32Ω
SE,Av=4.1dB
2
1
2
3
15kHz
0.2
Po=75mW
0.1
0.05
20Hz
0.05
50
10 0
200
1kHz
0.02
Po=25mW
50 0
1k
2k
5k
1 0k
0.01
1m
20k
2m
5m
10 m
2 0m
Hz
W
Figure 19
Figure 20
50m
100m
20 0m
Total Harmonic Distortion Plus
Noise vs Output Voltage
Total Harmonic Distortion Plus
Noise vs Frequency
10
10
5
1
50 0m
VDD=5V
RL=32Ω
SE,Av=4.1dB
%
Po=50mW
0.1
2
200 m
10
1
0.01
20
100m
Total Harmonic Distortion Plus
Noise vs Output Power
0.5
0.02
50 m
Figure 18
0.5
0.2
20m
Figure 17
1
%
10m
W
10
2
5m
20Hz
W
Total Harmonic Distortion Plus
Noise vs Frequency
5
VDD=5V
RL=8Ω
BTL,Av=21.6dB
5
VDD=5V
RL=10kΩ
SE,Av=4.1dB
Cout=1000µF
2
1
0.5
VDD=5V
RL=10kΩ
SE,Av=4.1dB
Cout=1000µF
0.5
%
%
0.2
0.2
0.1
0.05
0.05
0.02
0.02
0.01
20
50
10 0
200
50 0
Hz
1k
15kHz
20Hz
0.1
Vo=1Vrms
2k
5k
1 0k
0.01
100m
20k
Figure 21
1kHz
2 00m
300 m
400 m 50 0m
7 00m
Vo-Outpu t Vol tage-Vrms
1
2
3
Figure 22
TEL: 886-3-5788833
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Ver: 1.3
Sep 23, 2005
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G1427
Global Mixed-mode Technology Inc.
Supply Ripple Rejection Ratio
vs Frequency
+0
T T
-10
T
T
T
Supply Ripple Rejection Ratio
vs Frequency
+0
T T
VDD=5V
RL=8Ω
Cb=1µF
BTL
-20
-30
-20
-30
-40
d
B
VDD=5V
RL=8Ω
Cb=1µF
SE
-10
-40
Av=21.6dB
-50
d
B
-50
-60
-60
-70
-70
Av=6dB
-80
-80
-90
-90
-100
20
-100
20
50
10 0
200
50 0
Hz
1k
2k
5k
1 0k
20k
50
100
200
5 00
Figure 23
-35
-40
-45
-50
T
20 k
5k
1 0k
20k
-25
-30
VDD=5V
Po=1W
RL=8Ω
BTL,Av=6dB
-35
-40
-45
-50
-55
d
B
-60
VDD=5V
Po=1W
RL=8Ω
SE,Av=4.1dB
-60
-65
-65
L TO R
-70
L TO R
-70
-75
-75
-80
-80
-85
-85
-90
50
100
200
5 00
1k
2k
5k
R TO L
-90
R TO L
-95
-100
20
10k
Channel Separation
-55
d
B
5k
-20
-25
-30
2k
Figure 24
Channel Separation
-20
1k
Hz
-95
10k
-100
20
20 k
50
10 0
200
50 0
1k
Hz
Hz
Figure 25
Figure 26
Output Noise vs Frequency
2k
Output Power vs Load Resistance
2.5
5 00u
4 00u
2 00u
VDD=5V
RL=4Ω
BTL,Av=6dB
A-Weighted filter
1.5
1 00u
V
VDD=5V
THD+N=1%
BTL
Each Channel
2
Output Power(W)
3 00u
70u
60u
50u
40u
1
30u
0.5
20u
10u
20
50
100
200
5 00
1k
2k
5k
10k
0
20 k
0
Hz
Figure 27
10
20
Load Resistance(Ω)
30
40
Figure 28
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.3
Sep 23, 2005
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G1427
Global Mixed-mode Technology Inc.
Power Dissipation vs Output Power
Output Power vs Load Resistance
1.8
0.7
1.6
VDD=5V
THD+N=1%
SE
Each Channel
0.5
0.4
RL=3Ω
1.4
Power Dissipation
Output Power(W)
0.6
0.3
0.2
1.2
RL=4Ω
1
VDD=5V
BTL
Each Channel
0.8
0.6
0.4
0.1
RL=8Ω
0.2
0
0
4
8
12
16
20
24
Load Resistance(Ω)
28
32
0
Figure 29
0.5
1
1.5
Po-Output Pow er(W)
2
2.5
Figure 30
Recommend PCB Footprint
Power Dissipation vs Output Power
0.35
Power Dissipation(W)
0.3
RL=4Ω
0.25
0.2
0.15
0.1
RL=8Ω
0.05
VDD=5V
SE
Each Channel
RL=32Ω
0
0
0.2
0.4
0.6
0.8
Po-Output Pow er(W)
Figure 31
TEL: 886-3-5788833
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Ver: 1.3
Sep 23, 2005
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G1427
Global Mixed-mode Technology Inc.
Pin Description
PIN
NAME
1,12,13,24
2
GND/HS
GAIN0
I/O
I
Ground connection for circuitry, directly connected to thermal pad.
Bit 0 of gain control
FUNCTION
3
4
GAIN1
LOUT+
I
O
Bit 1 of gain control
Left channel + output in BTL mode, + output in SE mode.
5
LLINEIN
I
Left channel line input, selected when HP/ LINE pin is held low.
6
LPHIN
I
Left channel headphone input, selected when HP/ LINE pin is held high.
7,18
8
9
10
11
14
PVDD
RIN
LOUTLIN
BYPASS
PC-BEEP
I
I
O
I
15
SE/ BTL
I
Power supply for output stages.
Common right input for fully differential inputs. AC ground for single-ended inputs.
Left channel - output in BTL mode, and high impedance in SE mode.
Common left input for fully differential inputs. AC ground for single-ended inputs.
Tap to voltage divider for internal mid-supply bias generator.
The input for PC-BEEP mode. PC-BEEP is enabled when at least eight continuous >
1-VPP (peak to peak) square waves is input to PC-BEEP pin.
Hold low for BTL mode, hold high for SE mode.
16
17
ROUTHP/ LINE
O
I
19
VDD
Right channel - output in BTL mode, high impedance state in SE mode.
MUX control input, hold high to select headphone inputs (6,20), hold low to select line
inputs (5,23).
Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve
highest performance.
20
RHPIN
I
Right channel headphone input, selected when HP/ LINE pin is held high.
21
22
ROUT+
SHUTDOWN
O
I
Right channel + output in BTL mode, positive output in SE mode.
Places entire IC in shutdown mode when held low, expect PC-BEEP remains active.
23
RLINEIN
I
Right channel line input, selected when HP/ LINE pin is held low.
I
TEL: 886-3-5788833
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Ver: 1.3
Sep 23, 2005
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G1427
Global Mixed-mode Technology Inc.
Block Diagram
RLINEIN
RHPIN
Right
MUX
_
ROUT+
+
RIN
PC-Beep
PC-Beep
_
GAIN0
GAIN1
SE/BTL
HP/LINE
LLINEIN
LHPIN
ROUT-
+
BYPASS
Depop
Circuitry
Gain/MUX
Control
PVDD
Power
Management
VDD
SHUTDOWN
GND
Left
MUX
LOUT+
_
+
LIN
LOUT-
_
+
TEL: 886-3-5788833
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Ver: 1.3
Sep 23, 2005
10
G1427
Global Mixed-mode Technology Inc.
Application Circuit
Right Linein Negative
Differential Input
1µF
23
RLINEIN
20
RHPIN
Right
MUX
1µF
Right Hpin Negative
Differential Input
_
8
14
PC-Beep
11
BYPASS
2
3
15
GAIN0
GAIN1
17
HP/LINE
5
LLINEIN
6
LHPIN
SE/BTL
Depop
Circuitry
220µF
VDD
PVDD
Gain/MUX
Control
Power
Management
VDD
SHUTDOWN
Left
MUX
LOUT+
7,18 VDD
22 1µF 10µF
Note
100K
1K
4
_
+
10
1K
19
1,12,13,24
GND
Left Hpin Negative 1µF
Differential Input
Left Hpin/Linein Positive
Differential Input
16
PC-Beep
_
2.2µF
Left Linein Negative
Differential Input
1µF
ROUT-
RIN
+
1µF
PC-BEEP Input Signal
21
+
Right Hpin/Linein Positive
1µF
Differential Input
ROUT+
220µF
LIN
1µF
LOUT-
3
_
+
0.1µF
Application Circuit Using Differential Inputs
Note: 1µF ceramic capacitor should be placed as close as possible to the IC to filter the higher-frequency noise.
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Application Circuit (continued)
Right Hpin Input
1µF
23
RLINEIN
20
RHPIN
Right
MUX
1µF
_
Right Linein Input
ROUT+
21
ROUT-
16
+
RIN
14
PC-Beep
11
BYPASS
2
3
15
GAIN0
GAIN1
17
HP/LINE
5
LLINEIN
6
LHPIN
2.2µF
Left Hpin Input
1µF
SE/BTL
Depop
Circuitry
220µF
VDD
PVDD
Gain/MUX
Control
Power
Management
VDD
SHUTDOWN
Left
MUX
1µF
LOUT+
7,18 VDD
22 1µF 10µF
Note
100K
1K
4
+
10
1K
19
1,12,13,24
GND
_
Left Linein Input
PC-Beep
_
1µF
PC-BEEP Input Signal
8
+
1µF
220µF
LIN
1µF
LOUT-
3
_
+
0.1µF
Application Circuit Using Single-Ended Inputs
Note: 1µF ceramic capacitor should be placed as close as possible to the IC to filter the higher-frequency noise.
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Application Information
Table 2
Gain setting via GAIN0 and GAIN1 inputs
The internal gain setting is determined by two input
terminals, GAIN0 and GAIN1. The gains listed in Table
1 are realized by changing the taps on the input resistors inside the amplifier. This will cause the internal
input impedance, ZI, to be dependent on the gain setting. Although the real input impedance will shift by
30% due to process variation from part-to-part, the
actual gain settings are controlled by the ratios of the
resistors and the actual gain distribution from part-topart is quite good.
GAIN1
SE/ BTL
AV (dB)
0
0
0
6
0
1
0
10
1
0
0
15.6
1
1
0
21.6
X
X
1
4.1
Zi
45
15.6
70
10
90
6
The value of Ci is important to consider as it directly affects the bass performance of the application circuit. For
example, if the input resistor is 15kΩ, the input capacitor
is 1µF, the flat bass response will be down to 10.6Hz.
Because the small leakage current of the input capacitors will cause the dc offset voltage at the input to the
amplifier that reduces the operation headroom, especially at the high gain applications. The low-leakage
tantalum or ceramic capacitors are suggested to be
used as the input coupling capacitors. When using the
polarized capacitors, it is important to let the positive
side connecting to the higher dc level of the application.
The typical input impedance at each gain setting is given
in the Table 2. Each gain setting is achieved by varying
the input resistance of the amplifier, which can be over 3
times from its minimum value to the maximum value. As
a result, if a single capacitor is used in the input high
pass filter, the -3dB or cut-off frequency will be also
change over 3 times. To reduce the variation of the
cut-off frequency, an additional resistor can be connected from the input pin of the amplifier to the ground,
as shown in Figure 1. With the extra resistor, the cut-off
frequency can be re-calculated using equation : f-3dB= 1/
2πC(R||RI). Using small external R can reduce the variation of the cut-off frequency. But the side effect is small
external R will also let (R||RI) become small, the cut-off
frequency will be larger and degraded the bass-band
performance. The other side effect is with extra power
dissipation through the external resistor R to the ground.
So using the external resistor R to flatting the variation of
the cut-off frequency, the user must also consider the
bass-band performance and the extra power dissipation
to choose the accepted external resistor R value.
C
21.6
In the typical application, an input capacitor Ci is required to allow the amplifier to bias the input signal to
the proper dc level for optimum operation. In this
case ,Ci and the input impedance of the amplifier, Zi,
form a high-pass filter with the -3dB determined by the
equation: f-3dB= 1/ (2πRI Ci)
Input Resistance
Input Signal
AV (dB)
30
Input Capacitor
Table 1
GAIN0
Zi (Kohm)
Power Supply Decoupling
The G1427 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
make sure the output total harmonic distortion (THD)
as low as possible. The optimum decoupling is using
two capacitors with different types that target different
types of noise on the power supply leads. For high
frequency transients, spikes, a good low ESR ceramic
capacitor works best, typically 0.1µF/1µF used and
placed as close as possible to the G1427 VDD lead. A
larger aluminum electrolytic capacitor of 10µF or
greater placed near the device power is recommended
for filtering low-frequency noise.
Optimizing DEPOP Operation
Circuitry has been implemented in G1427 to minimize the amount of popping heard at power-up and
when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the
speaker and making the differential voltage generated at the two ends of the speaker. To avoid the
popping heard, the bypass capacitor should be
chosen promptly, 1/(CBx170kΩ) ≦ 1/(CI*(RI+RF)).
Zf
IN
R
Figure 1
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Where 170kΩ is the output impedance of the
mid-rail generator, CB is the mid-rail bypass capacitor, CI is the input coupling capacitor, RI is the
input impedance, RF is the gain setting impedance
which is on the feedback path. CB is the most important capacitor. Besides it is used to reduce the
popping, CB can also determine the rate at which
the amplifier starts up during startup or recovery
from shutdown mode.
Output coupling capacitor
G1427 can drive clean, low distortion SE output power
with gain –1V/V into headphone loads (generally 16Ω
or 32Ω) as in Figure 3. Please refer to Electrical
Characteristics to see the performances. A coupling
capacitor is needed to block the dc-offset voltage, allowing pure ac signals into headphone loads. Choosing the coupling capacitor will also determine the -3dB
point of the high-pass filter network, as Figure 4.
fC=1/(2πRLCC)
De-popping circuitry of G1427 is shown as below
Figure 2. The PNP transistor limits the voltage drop
across the 120kΩ by slewing the internal node
slowly when power is applied. At start-up, the voltage at BYPASS capacitor is 0. The PNP is ON to
pull the mid-point of the bias circuit down. So the
capacitor sees a lower effective voltage, and thus
the charging is slower. This appears as a linear
ramp (while the PNP transistor is conducting), followed by the expected exponential ramp of an R-C
circuit.
For example, a 220µF capacitor with 32Ω headphone
load would attenuate low frequency performance below 22.6Hz. So the coupling capacitor should be well
chosen to achieve the excellent bass performance
when in SE mode operation.
VDD
Vo(PP)
For better performance, CB is recommended to be
at least 1.5 times of input coupling capacitor CI. For
example, if using 1µF input coupling capacitor,
2.2µF ceramic or tantalum low-ESR capacitors are
recommended to achieve the better THD performance.
CC
RL
Vo(PP)
Figure 3
VDD
100 kΩ
120 kΩ
Bypass
-3 dB
100 kΩ
fc
Figure 4
Figure 2
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Bridged-Tied Load Mode Operation
G1427 has two linear amplifiers to drive both ends of
the speaker load in Bridged-Tied Load (BTL) mode
operation. Figure 5 shows the BTL configuration. The
differential driving to the speaker load means that
when one side is slewing up, the other side is slewing
down, and vice versa. This configuration in effect will
double the voltage swing on the load as compared to a
ground reference load. In BTL mode, the peak-to-peak
voltage VO(PP) on the load will be two times than a
ground reference configuration. The voltage on the
load is doubled, this will also yield 4 times output
power on the load at the same power supply rail and
loading. Another benefit of using differential driving
configuration is that BTL operation cancels the dc offsets, which eliminates the dc coupling capacitor that is
needed to cancelled dc offsets in the ground reference
configuration. Low-frequency performance is then limited only by the input network and speaker responses.
Cost and PCB space can be minimized by eliminating
the dc coupling capacitors.
Shutdown mode
When the normal operation, the SHUTDOWN pin
should be held high. Pulling SHUTDOWN low will
mute the outputs and deactivate almost circuits except
PC-BEEP monitoring block. At this moment, the current of this device will be reduced to about 160µA to
save the battery energy. The SHUTDOWN pin should
never be left unconnected during the normal applications.
INPUT *
HP/ LINE SE/ BTL SHUTDOWN
X
Low
High
Low
High
High
High
Low
High
High
High
High
X
Line
Line
headphone
headphone
Mute
BTL
SE
BTL
SE
PC-BEEP Operation
The PC-BEEP input allows a system beep to be sent
directly from a computer through the amplifier to the
speakers with a few external components. It is activated automatically by detecting the PC-BEEP input.
The preferred input signal is a square wave or pulse
train with an amplitude of 1-VPP or greater. To be accurately detected, the signal must be with at least
1-VPP amplitude, 8 continuous rising edges, rise and
fall times less than 0.1µs. When the signal is no longer
detected, the amplifier will return its previous operating
mode and volume setting.
VDD
Vo(PP)
RL
X
Low
Low
INPUT OUTPUT
* Inputs should never be left unconnected
X= do not care
Input MUX And SE/ BTL Operation
VDD
AMPLIFIER STATE
2xVo(PP)
-Vo(PP)
When the PC-BEEP mode is activated, both the
LINEIN and HPIN are deselected and the outputs will
be driven in BTL mode with the signal from PC-BEEP.
The gain setting will be also fixed at 0.3V/V, independent of the volume setting. If the device is in the
SHUTDOWN mode, activating PC-BEEP will take the
device out of shutdown mode and output the
PC-BEEP input signal until the PC-BEEP signal no
longer detected. And then the device will return the
shutdown mode when no PC-BEEP signal is detected.
Figure 5
The G1427 allows two different input sources applied
to the audio amplifiers, which can be independent to
the SE/ BTL setting. When HP/ LINE is held high, the
headphone inputs are active. When the HP/ LINE is
held low, the line inputs are selected.
When SE/ BTL is held low, all four internal audio amplifiers are activated to drive the stereo speakers.
When SE/ BTL is held high, two amplifiers are activated to drive the stereo headphones. The other two
amplifiers are disable and keeping the outputs high
impedance.
The PC-BEEP input can be dc-coupled to save the
coupling capacitor. This pin is set at mid-rail normally
when no signal is present.
If AC-coupling is desired, the value of the coupling
capacitor should be chosen to satisfy the equation:
CPCB≧ 1/( 2πfPCB*150KΩ)
CPCB is the PC-BEEP AC-coupling capacitor. fPCB is the
frequency of applied PC-BEEP input signal.
TEL: 886-3-5788833
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Package Information
C
D
24
L
1.88
1.88
3.85
E1 E
2.8
0.71
1
Note 5
θ
A2
A
A1
e
b
NOTE:
1. Package body sizes exclude mold flash protrusions or gate burrs
2. Tolerance ±0.1mm unless otherwise specified
3. Coplanarity : 0.1mm
4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Follow JEDEC MO-153
SYMBOL
A
A1
A2
b
C
D
E
E1
e
L
y
θ
MIN.
DIMENSION IN MM
NOM.
MAX.
----0.00
0.80
0.19
0.09
7.70
6.20
4.30
----0.45
----0º
--------1.00
--------7.80
6.40
4.40
0.65
0.60
---------
1.15
0.10
1.05
0.30
0.20
7.90
6.60
4.50
----0.75
0.10
8º
MIN.
DIMENSION IN INCH
NOM.
MAX.
----0.000
0.031
0.007
0.004
0.303
0.244
0.169
----0.018
----0º
--------0.039
--------0.307
0.252
0.173
0.026
0.024
---------
0.045
0.004
0.041
0.012
0.008
0.311
2.260
0.177
----0.030
0.004
8º
Taping Specification
PACKAGE
Q’TY/REEL
TSSOP-24 (FD)
2,500 ea
F e e d D ir e c tio n
T y p ic a l T S S O P P a c k a g e O r ie n ta tio n
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
TEL: 886-3-5788833
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