TIGER ELECTRONIC CO.,LTD Single Timer Outline Drawing DESCRIPTION The NE555N/NE555D NE555N/NE555D is a highly stable controller capable of producing accurate timing pulses. With a monostable operation, the time delay is controlled by one external resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one NE555N capacitor. FEATURES DIP8 High Current Drive Capability (200mA) Adjustable Duty Cycle Temperature Stability of 0.005%/°C Timing From Sec to Hours NE555D Turn off Time Less Than 2 Sec APPLICATIONS Precision Timing Pulse Generation Time Delay Gen eratio n SOP8 Sequential Timing 1/11 NE555N/NE555D BLOCK DIAGRAM AND PIN CONNECTION ABSOLUTE MAXIMUM RATINGS (Ta=25 °C) Characteristic Symbol Value Unit Vcc 16 V Pd 600 mW Operating temp erature Topr -0~+70 °C Storage temperature Tstg -65~+150 °C TLEAD 300 °C Power Supply voltage Power Dissipation Lead Temperature (Soldering 10sec) 2/11 NE555N/NE555D ELECTRICAL CHARACTERISTICS (Unless otherwise specified: Vcc=5~15V， Ta=2 5°C) Characteristics Symbol S u p p l y Vo l t a g e Vcc Supply current(low stable)* Icc Ti m i n g E r r o r ( M o n o s t a b l e ) Initial Accuracy ** D r i f t w i t h Te m p e r a t u r e * * * * D r i f t w i t h S u p p l y Vo l a t g e **** Ti m i n g E r r o r ( A s t a b l e ) Initial Accuracy ** D r i f t w i t h Te m p e r a t u r e * * * * D r i f t w i t h S u p p l y Vo l a t g e **** C o n t r o l Vo l t a g e ACCUR ∆t/∆T ∆t/∆Vcc ACCUR ∆t/∆T ∆t/∆Vcc Vc T h r e s h o l d Vo l t a g e VTH Threshold Current*** ITH Tr i g g e r Vo l t a g e VTR Tr i g g e r C u r r e n t ITR R e s e t Vo l t a g e VRST Reset Current IRST L o w O u t p u t Vo l t a g e VOL Test conditions Min VOH Max Unit 16 V 4.5 Vcc=5V,R L =∞ 3 6 Vcc=15V,R L =∞ 7.5 15 R A =1kΩ to 100k Ω C=0.1µF 1.0 50 0.1 3.0 R A =1kΩ to 100k Ω C=0.1µF 0.5 9.0 10.0 11 . 0 Vcc=5V 2.6 3.33 4.0 10.0 Vcc=5V 3.33 % p p m / °C %/V %/V Vcc=15V Vcc=15V mA % p p m / °C 2.25 150 0.3 V V 0.1 0.25 µA Vcc=5V 1.1 1.67 2.2 Vcc=15V 4.5 5 5.6 0.01 2.0 µA 0.7 1.0 V 0.1 0.4 mA 0.06 0.3 0.25 0.75 V 0.05 0.35 V T R =0V 0.4 Vcc=15V I S I N K =10mA I S I N K =50mA Vcc=5V H i g h O u t p u t Vo l t a g e Typ I S I N K =5mA Vcc=15V I S O U R C E =200mA I S O U R C E =100mA 12.75 12.5 13.3 2.75 3.3 Vcc=5V I S O U R C E =100mA V V R i s e Ti m e o f O u t p u t * * * * tR 100 ns F a l l Ti m e o f O u t p u t * * * * tF 100 ns ILKG 20 D i s c h a rg e L e a k a g e C u r r e n t 100 nA * When the output is high, the supply current is typically 1mA less than at Vcc = 5V. ** Tested at Vcc = 5.0V and Vcc = 15V. *** This will determine the maximu m value of R A + R B for 15V operation, the max. total R = 20M Ω , and for 5V operation, the max. total R = 6.7M Ω . ****These parameters, although guaranteed, are not 100% tested in production. 3/11 NE555N/NE555D APPLICATION INFORMATION Table below is the basic operating table of D555/D555F timer T h r e s h o l d Vo l t a g e (Vth)(PIN6) Tr i g g e r Vo l t a g e (Vtr)(PIN2) Reset(PIN4) Output(PIN3) D i s c h a rg i n g Tr. (PIN7) Don’t care Vth>2Vcc/3 Vcc/3<Vth<2Vcc/3 Vth<Vcc/3 Don’t care Vth>2Vcc/3 Vcc/3<Vth<2Vcc/3 Vth<Vcc/3 Low High High High Low Low ON ON High OFF When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high. 1、 Monostable Operation 4/11 NE555N/NE555D Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=R A *C and reaches 2Vcc/3 at td=1.1R A *C. Hence, capacitor C1 is charged through resistor R A . The greater the time constant R A C, the longer it takes for the VC1 to reach 2Vcc/3. In other words, the time constant R A C controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comp arator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low. In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on R A and C. Figure 3 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality. 5/11 NE555N/NE555D 2 、 Astable Operation An astable timer operation is achieved by adding resistor R B to Figure 1 and configuring as shown on Figure 5. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a mu lti vibrator. When the timer output is high, its internal discharging Tr. turns off and the V C 1 increases by exponential function with the time constant (R A +R B )*C. When the V C 1 , or the threshold voltage, reaches 2Vcc/3, the comp arator output on the trigger terminal becomes high, resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by R B and the discharging Tr. When the V C 1 falls below Vcc/3, the 6/11 NE555N/NE555D comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the V C 1 rises again. In the above process, the section where the timer output is high is the time it takes for the V C 1 to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the V C 1 to drop from2 Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows: Since the duration of the timer output high state(t H ) is the amount of time it takes for the V C 1 (t) to reach 2Vcc/3, The equivalent circuit for discharg ing capacitor C1,when timer output is low is ,as follows: Since the duration of the timer output low state(t L ) is the amount of time it takes for the V C 1 (t) to reach Vcc/3, 7/11 NE555N/NE555D Since R D is normally R B >>R D although related to the size of discharging Tr., Consequently, if the timer operates in astable, the period is the same with 'T=t H +t L =0.693(R A +R B )C 1 +0.693R B C 1 =0.693(R A +2R B )C 1 ' because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies. 3、 Frequency divider By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure8. illustra tes a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. 4 、 Pulse Width Modulation The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 modulation circuit. illustrates the pulse width When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform. 8/11 NE555N/NE555D 5 、 Pulse Position Modulation If the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal. Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used. 6 、 Linear Ramp When the pull-up resistor R A in the monostable circuit shown in Figure 1 is replaced with constant current source, the V C 1 increases linearly, generating a linear ramp. Figure 13 9/11 NE555N/NE555D shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms. In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and R E . For example, if Vcc=15V, R E =20k Ω , R1=5kW, R2=10k Ω , and V B E =0.7V, V E =0.7V+10V=10.7V Ic=(15-10.7)/20k=0.215mA When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as follows: Here the Vp-p is the peak-to-peak voltage. If the electric charge amount accumu lated in the capacitor is divided by the capacitance, the V C comes out as follows: V=Q/C (15) The above equation divided on both sides by T gives us 10/11 NE555N/NE555D and may be simp lified into the following equation. S=I/C (17) In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02μ F, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022 μ = 9.77V/ms. 11/11