HANBIT HCPMEM-512

HANBit
HCPMEM-512
EDO DRAM Board 512Mbyte ( 32M x 144-Bit ) organized as 4Banks of
8Mx144, 4K Ref., 3.3V, ECC
Part No. HCPMEM-512
GENERAL DESCRIPTION
The HCPMEM-512 is a 32M x 144 bit Dynamic RAM high-density module, organized with four banks of 8M x 144 bits.
The HCPMEM-512 consists of thirty six 8M x 16, 4K refresh DRAMs in TSOPII packages, five 16 bit buffer/drivers and one
PLD. The PLD controls the WRITE Enable and Output Enable signals to the DRAMS. Connectors on each side of the
module allow two memories to mated together.
FEATURES
-
VTTL compatible inputs and outputs
10 bit Column addressing
Single 3.3V +/- .3 power supply
Buffered Address and Control lines
Mezzanine stackingAccess time: 60 ns (max)
Power dissipation
* Active: 7.5 W (max)
* Standby : 400 mW (max) (CMOS interface)
EDO page mode capability
CAS-before-RAS refreshRefresh cycles
FR4-PCB design
Application : Sun Microsystem CP 1400/1500
• The used device is HM5113165F-6
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Rev. 1.0 (March, 2002)
1
HANBit Electronics Co.,Ltd.
HANBit
HCPMEM-512
Pin Configuration (TOP)
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
D0
D1
D2
VDD
D3
D4
D5
GND
D6
D7
D8
VDD
D9
D10
D11
GND
D12
D13
D14
VDD
D15
D16
D17
GND
GND
D18
D19
D20
VDD
D21
D22
D23
GND
D24
D25
D26
VDD
D27
D28
D29
GND
D30
D31
D32
VDD
D33
D34
D35
GND
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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Rev. 1.0 (March, 2002)
J2
GND
D36
D37
D38
VDD
D39
D40
D41
GND
D42
D43
D44
VDD
D45
D46
D47
GND
D48
D49
D50
VDD
D51
D52
D53
GND
GND
D54
D55
D56
VDD
D57
D58
D59
GND
D60
D61
D62
VDD
D63
D64
D65
GND
D66
D67
D68
VDD
D69
D70
D71
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
D72
D73
D74
VDD
D75
D76
D77
GND
D78
D79
D80
VDD
D81
D82
D83
GND
D84
D85
D86
VDD
D87
D88
D89
VDD
VDD
D90
D91
D92
VDD
D93
D94
D95
GND
D96
D97
D98
VDD
D99
D100
D101
GND
D102
D103
D104
VDD
D105
D106
D107
GND
J3
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
2
GND
D108
D109
D110
VDD
D111
D112
D113
GND
D114
D115
D116
VDD
D117
D118
D119
GND
D120
D121
D122
VDD
D123
D124
D125
GND
GND
D126
D127
D128
VDD
D129
D130
D131
GND
D132
D133
D134
VDD
D135
D136
D137
GND
D138
D139
D140
VDD
D141
D142
D143
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
A0
A1
VDD
A2
A3
GND
A4
A5
VDD
A6
A7
GND
A8
A9
VDD
A10
A11
GND
A12
GND
GND
/RASB2_L
NC
VDD
/RAST2_L
NC
GND
/RAB3_L
VDD
VDD
/RAST3_L
GND
GND
/RASB0_L
NC
VDD
/RAST0_L
NC
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
/RASB1_L
EN U1 3
VDD
/RAST1_L
GND
GND
/CAS0(0)_
/CAS0(1)_
VDD
GND
/CAS1(0)_
/CAS1(1)_
VDD
VDD
NC
GND
/WE0_L
VDD
VDD
VDD
XOE_L
GND
GND
XOEA_L
50_60NS_RA
VDD
VDD
NC
GND
TDI
TDO
VDD
TMS1
VDD
NC
GND
TCLK1
GND
GND
HANBit Electronics Co.,Ltd.
HANBit
HCPMEM-512
Pin Configuration (BOTTOM)
J4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
D0
D1
D2
VDD
D3
D4
D5
GND
D6
D7
D8
VDD
D9
D10
D11
GND
D12
D13
D14
VDD
D15
D16
D17
GND
GND
D18
D19
D20
VDD
D21
D22
D23
GND
D24
D25
D26
VDD
D27
D28
D29
GND
D30
D31
D32
VDD
D33
D34
D35
GND
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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Rev. 1.0 (March, 2002)
J5
GND
D36
D37
D38
VDD
D39
D40
D41
GND
D42
D43
D44
VDD
D45
D46
D47
GND
D48
D49
D50
VDD
D51
D52
D53
GND
GND
D54
D55
D56
VDD
D57
D58
D59
GND
D60
D61
D62
VDD
D63
D64
D65
GND
D66
D67
D68
VDD
D69
D70
D71
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
D72
D73
D74
VDD
D75
D76
D77
GND
D78
D79
D80
VDD
D81
D82
D83
GND
D84
D85
D86
VDD
D87
D88
D89
VDD
VDD
D90
D91
D92
VDD
D93
D94
D95
GND
D96
D97
D98
VDD
D99
D100
D101
GND
D102
D103
D104
VDD
D105
D106
D107
GND
J6
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
3
GND
D108
D109
D110
VDD
D111
D112
D113
GND
D114
D115
D116
VDD
D117
D118
D119
GND
D120
D121
D122
VDD
D123
D124
D125
GND
GND
D126
D127
D128
VDD
D129
D130
D131
GND
D132
D133
D134
VDD
D135
D136
D137
GND
D138
D139
D140
VDD
D141
D142
D143
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
A0
A1
VDD
A2
A3
GND
A4
A5
VDD
A6
A7
GND
A8
A9
VDD
A10
A11
GND
A12
GND
GND
/RASB0_L
NC
VDD
/RAST0_L
NC
GND
/RAB1_L
VDD
VDD
/RAST1_L
GND
GND
/RASB2_L
NC
VDD
/RAST2_L
NC
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
/RASB3_L
EN U1 3
VDD
/RAST3_L
GND
GND
/CAS0(0)_
/CAS0(1)_
VDD
GND
/CAS1(0)_
/CAS1(1)_
VDD
VDD
NC
GND
/WE0_L
VDD
VDD
VDD
XOE_L
GND
GND
XOEA_L
50_60NS_RA
VDD
VDD
NC
GND
TDI
TDO
VDD
TMS1
VDD
NC
GND
TCLK1
GND
GND
HANBit Electronics Co.,Ltd.
HANBit
HCPMEM-512
FUNCTIONAL BLOCK DIAGRAM
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HANBit
HCPMEM-512
ABSOLUTE MAXIMUM RATINGS
Notes :
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C)
Notes :
1. All voltage referred to VSS .
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the
same level.
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HANBit Electronics Co.,Ltd.
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HCPMEM-512
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
450
Notes :
1. Icc depends on output load condition when the device is selected. Icc max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, tHPC.
4. VIH ≥ VCC – 0.2V, 0 V ≤ VIL ≤ 0.2 V.
CAPACITANCE (TA = 25° C, V CC = 3.3 V ± 0.3 V)
Notes :
1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /RAS, /UCAS AND /LCAS = VIH TO DISABLE DOUT.
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HCPMEM-512
AC Characteristics (Ta = 0 to +70° C, V = 3.3 V ± 0.3 V, V = 0 V)
Test Conditions
•Input rise and fall time: 2 ns
•Input pulse levels: VIL = 0 V, VIH = 3.0 V
•Input timing reference levels: 0.8 V, 2.0 V
•Output timing reference levels: 0.8 V, 2.0 V
•Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
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HCPMEM-512
Read Cycle
Write Cycle
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HCPMEM-512
Read-Modify-Write Cycle
Refresh Cycle
EDO Page Mode Cycle
EDO Page Mode Read-Modify-Write Cycle
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Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
HCPMEM-512
AC measurements assume tT = 2 ns.
An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any
combination of cycles containing /RAS-only refresh or /CAS -before-/RAS refresh).
Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference
point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively
by tCAC .
Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference
point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by
tAA .
Either tOED or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH (min) and VIL (max).
Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open
circuit condition and are not referred to output voltage levels.
tWCS , tRWD , tCWD , tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out
pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD
(min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle
is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
tDS and tDH are referred to /UCAS and /LCAS leading edge in early write cycles and to /WE leading edge in
delayed write or read-modify-write cycles.
tRASP defines /RAS pulse width in EDO page mode cycles.
Access time is determined by the longest among tAA , tCAC and tCPA .
In delayed write or read-modify-write cycles, /OE must disable output buffer prior to applying data to the device.
When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output
buffer is turned on and off within a very short time, generally it causes large Vcc /Vss line noise, which causes to
degrade VIH min/VIL max level.
tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If
both write and read operation are mixed in a EDO page mode /RAS cycle (EDO page mode mix cycle (1), (2)),
minimum value of /CAS cycle (tCAS + tCP + 2 tT ) becomes greater than the specified tHPC (min) value. The
value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS . Hold time and turn
off time are specified by the timing specifications of later rising edge of /RAS and /CAS between tOHR and tOH
and between tOFR and tOFF .
tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference
level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the
condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at qual interval to all
refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6µs after exiting
from self refresh mode.
In case of entering from /RAS -only-refresh, it is necessary to execute CBR refresh before and after self refresh
mode according as note 23.
At tRASS > 100 µs, self refresh mode is activated, and not activated at tRASS < 10 µs. It is undefined within the
range of 10 µs ≤ tRASS ≤ 100 µs. For tRASS ≥ 10 µs, it is necessary to satisfy tRPS .
tASC , tCAH , tRCS , tWCS , tWCH , tCSR , tRPC , tCRP , tCHR , tRCH , tCPA , tCPW , tCWL , tDH , tDS ,
tCHS and tCP are determined by each of /UCAS /LACS independently.
XXX : H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
/////// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or
VIL .
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HANBit Electronics Co.,Ltd.
HANBit
HCPMEM-512
TIMING DIAGRAMS
CAS -Before-RAS Refresh Cycle
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HCPMEM-512
Hidden Refresh Cycle
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HCPMEM-512
EDO Page Mode Read Cycle (1)
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HCPMEM-512
EDO Page Mode Read Cycle (2)
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HCPMEM-512
EDO Page Mode Early Write Cycle
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HCPMEM-512
EDO Page Mode Delayed Write Cycle*18
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HCPMEM-512
EDO Page Mode Read-Modify-Write Cycle*18
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HCPMEM-512
EDO Page Mode Mix Cycle (1) * 20
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HCPMEM-512
EDO Page Mode Mix Cycle (2)*20
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HCPMEM-512
PACKAGING INFORMATION
Unit
: Mil
[ Milimeter ]
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HCPMEM-512
ORDERING INFORMATION
Part Number
Density
Org.
Package
Mode
Ref
Vcc
SPEED
HCPMEM-512
512MByte
32MX 144bit
Mezzanine
EDO
4K
3.3V
60ns
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