HM5116400 Series HM5117400 Series 4,194,304-word 4-bit Dynamic RAM ADE-203-648C (Z) Rev. 3.0 Feb. 27, 1997 Description The Hitachi HM5116400 Series, HM5117400 Series are CMOS dynamic RAMs organized 4,194,304-word 4-bit. They employ the most advanced 0.5 m CMOS technology for high performance and low power. The HM5116400 Series, HM5117400 Series offer Fast Page Mode as a high speed access mode. They have package variations of standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP. Features • • • • • • • • Single 5 V ( 10%) Access time: 50 ns/60 ns/70 ns (max) Power dissipation Active mode : 495 mW/440 mW/385 mW (max) (HM5116400 Series) : 550 mW/495 mW/440 mW (max) (HM5117400 Series) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 4096 refresh cycles : 64 ms (HM5116400 Series) : 128 ms (L-version) 2048 refresh cycles : 32 ms (HM5117400 Series) : 128 ms (L-version) 3 variations of refresh -only refresh -beforerefresh Hidden refresh Battery backup operation (L-version) Test function 16-bit parallel test mode HM5116400 Series, HM5117400 Series Ordering Information Type No. Access time Package HM5116400S-5 HM5116400S-6 HM5116400S-7 50 ns 60 ns 70 ns 300-mil 26-pin plastic SOJ (CP-26/24DB) HM5116400LS-5 HM5116400LS-6 HM5116400LS-7 50 ns 60 ns 70 ns HM5117400S-5 HM5117400S-6 HM5117400S-7 50 ns 60 ns 70 ns HM5117400LS-5 HM5117400LS-6 HM5117400LS-7 50 ns 60 ns 70 ns HM5116400TS-5 HM5116400TS-6 HM5116400TS-7 50 ns 60 ns 70 ns HM5116400LTS-5 HM5116400LTS-6 HM5116400LTS-7 50 ns 60 ns 70 ns HM5117400TS-5 HM5117400TS-6 HM5117400TS-7 50 ns 60 ns 70 ns HM5117400LTS-5 HM5117400LTS-6 HM5117400LTS-7 50 ns 60 ns 70 ns 2 300-mil 26-pin plastic TSOP II (TTP-26/24DA) HM5116400 Series, HM5117400 Series Pin Arrangement HM5116400S/LS Series HM5116400TS/LTS Series VCC 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 4 23 4 23 5 22 5 22 A11 6 21 A9 A11 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 VCC 13 14 VSS VCC 13 14 VSS (Top view) (Top view) Pin Description Pin name Function A0 to A11 Address input — Row/Refresh address A0 to A11 — Column address A0 to A9 I/O1 to I/O4 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC Power supply VSS Ground 3 HM5116400 Series, HM5117400 Series Pin Arrangement HM5117400S/LS Series HM5117400TS/LTS Series VCC 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 4 23 4 23 5 22 5 22 NC 6 21 A9 NC 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 VCC 13 14 VSS VCC 13 14 VSS (Top view) Pin Description Pin name Function A0 to A10 Address input — Row/Refresh address A0 to A10 — Column address A0 to A10 I/O1 to I/O4 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC Power supply VSS Ground NC No connection (Top view) HM5116400 Series, HM5117400 Series Block Diagram (HM5116400 Series) Timing and control A0 Column decoder A1 to • • • Column 4M array address buffers A9 • • • Row address Row decoder 4M array I/O buffers 4M array I/O1 to I/O4 buffers A10 4M array A11 5 HM5116400 Series, HM5117400 Series Block Diagram (HM5117400 Series) Timing and control A0 Column decoder A1 to • • • Column 4M array address buffers A10 • • • Row address Row decoder 4M array I/O buffers 4M array buffers 4M array 6 I/O1 to I/O4 HM5116400 Series, HM5117400 Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg –55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70˚C) Parameter Symbol Min Typ Max Unit Note Supply voltage VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Note: 1. All voltage referred to VSS. 7 HM5116400 Series, HM5117400 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 5 V 10%, VSS = 0 V) (HM5116400 Series) HM5116400 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 90 — 80 — 70 mA t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface , = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface , VCC – 0.2 V Dout = High-Z I CC2 — 150 — 150 A CMOS interface , VCC – 0.2 V Dout = High-Z I CC3 — 90 — 80 — 70 mA t RC = min I CC5 — 5 — 5 — 5 mA = VIH = VIL Dout = enable I CC6 — 90 — 80 — 70 mA t RC = min Fast page mode current*1, * 3 I CC7 — 80 — 70 — 60 mA t PC = min Battery backup current (Standby with CBR refresh) (L-version) I CC10 — 350 — 350 A CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s Input leakage current I LI –10 10 –10 10 –10 10 A 0V Output leakage current I LO –10 10 –10 10 –10 10 A 0 V Vin 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 4.2 mA 1 Standby current (L-version) -only refresh current*2 1 Standby current* -beforecurrent refresh 0 150 — 350 — 0 Vin 7V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. 8 HM5116400 Series, HM5117400 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 5 V 10%, VSS = 0 V) (HM5117400 Series) HM5117400 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 100 — Standby current I CC2 — 2 — 1 I CC2 — 150 — 150 — I CC3 — 100 — 90 I CC5 — 5 I CC6 — Fast page mode current*1, * 3 I CC7 — 90 Battery backup current (Standby with CBR refresh) (L-version) I CC10 — 350 — Input leakage current I LI –10 10 –10 10 Output leakage current I LO –10 10 –10 10 Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 4.2 mA 1 Standby current (L-version) -only refresh current*2 1 Standby current* -beforecurrent refresh 90 — 80 mA t RC = min — 2 — 2 mA TTL interface , = VIH Dout = High-Z — 1 — 1 mA CMOS interface , VCC – 0.2 V Dout = High-Z 150 A CMOS interface , VCC – 0.2 V Dout = High-Z — 80 mA t RC = min 5 — 5 mA = VIH = VIL Dout = enable 100 — 90 — 80 mA t RC = min — 80 — 70 mA t PC = min 350 A CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 s t RAS 0.3 s –10 10 A 0V –10 10 A 0 V Vin 7 V Dout = disable — 0 350 — 0 Vin 7V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. 9 HM5116400 Series, HM5117400 Series Capacitance (Ta = 25˚C, VCC = 5 V 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = VIH to disable Dout. AC Characteristics (Ta = 0 to +70˚C, VCC = 5 V 10%, VSS = 0 V) *1, *2, *18, *19 Test Conditions • • • 10 Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) HM5116400 Series, HM5117400 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116400/HM5117400 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 90 — 110 — 130 — ns precharge time t RP 30 — 40 — 50 — ns precharge time t CP 7 — 10 — 10 — ns pulse width t RAS 50 10000 60 10000 70 10000 ns pulse width t CAS 13 10000 15 10000 18 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 7 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 7 — 10 — 15 — ns t RCD 17 37 20 45 20 52 ns 3 to column address delay time t RAD 12 25 15 30 15 35 ns 4 hold time t RSH 13 — 15 — 18 — ns hold time t CSH 50 — 60 — 70 — ns to t CRP 5 — 5 — 5 — ns to Din delay time t OED 13 — 15 — 18 — ns 5 delay time from Din t DZO 0 — 0 — 0 — ns 6 t DZC 0 — 0 — 0 — ns 6 tT 3 50 3 50 3 50 ns 7 to delay time precharge time delay time from Din Transition time (rise and fall) Notes 11 HM5116400 Series, HM5117400 Series Read Cycle HM5116400/HM5117400 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from t RAC — 50 — 60 — 70 ns 8, 9, 20 Access time from t CAC — 13 — 15 — 18 ns 9, 10, 17, 20 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 17, 20 Access time from t OEA — 13 — 15 — 18 ns 9, 20 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to t RCH 0 — 0 — 0 — ns 12 Read command hold time to t RRH 0 — 0 — 0 — ns 12 Column address to lead time t RAL 25 — 30 — 35 — ns Column address to lead time t CAL 25 — 30 — 35 — ns t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 13 — 15 — 15 ns 13 Output buffer turn-off to t OEZ — 13 — 15 — 15 ns 13 t CDD 13 — 15 — 18 — ns 5 to output in low-Z to Din delay time Write Cycle HM5116400/HM5117400 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14 Write command hold time t WCH 7 — 10 — 15 — ns Write command pulse width t WP 7 — 10 — 10 — ns Write command to lead time t RWL 13 — 15 — 18 — ns Write command to lead time t CWL 13 — 15 — 18 — ns Data-in setup time t DS 0 — 0 — 0 — ns 15 Data-in hold time t DH 7 — 10 — 15 — ns 15 12 HM5116400 Series, HM5117400 Series Read-Modify-Write Cycle HM5116400/HM5117400 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 131 — 155 — 181 — ns Notes to delay time t RWD 73 — 85 — 98 — ns 14 to delay time t CWD 36 — 40 — 46 — ns 14 t AWD 48 — 55 — 63 — ns 14 t OEH 13 — 15 — 18 — ns Column address to delay time hold time from Refresh Cycle HM5116400/HM5117400 -5 Parameter Symbol -6 -7 Min Max Min Max Min Max Unit setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns hold time (CBR refresh cycle) t CHR 7 — 10 — 10 — ns setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns hold time (CBR refresh cycle) t WRH 7 — 10 — 10 — ns t RPC 5 — 5 — 5 — ns precharge to hold time Notes Fast Page Mode Cycle HM5116400/HM5117400 -5 -6 -7 Min Max Min Max Parameter Symbol Min Max Fast page mode cycle time t PC 35 — Fast page mode pulse width t RASP — 100000 — Access time from precharge t CPA — 30 — 35 30 — 35 — hold time from precharge t CPRH 40 — 45 100000 — — Unit Notes ns 100000 ns 16 — 40 ns 9, 17, 20 40 — ns 13 HM5116400 Series, HM5117400 Series Fast Page Mode Read-Modify-Write Cycle HM5116400/HM5117400 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Fast page mode read-modify-write cycle time t PRWC 76 — 85 — 96 — ns 53 — 60 — 68 — ns 14 Notes delay time from precharge t CPW Notes Test Mode Cycle *19 HM5116400/HM5117400 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test mode setup time t WTS 0 — 0 — 0 — ns Test mode hold time t WTH 7 — 10 — 10 — ns Refresh (HM5116400 Series) Parameter Symbol Max Unit Notes Refresh t REF 64 ms 4096 cycles Refresh (L-version) t REF 128 ms 4096 cycles Parameter Symbol Max Unit Notes Refresh period t REF 32 ms 2048 cycles Refresh period (L-version) t REF 128 ms 2048 cycles Refresh (HM5117400 Series) 14 HM5116400 Series, HM5117400 Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If the internal refresh counter is used, a minimum of eight -beforerefresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + t AA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + t AA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. leading edge in early write cycles and to leading 15. These parameters are referred to edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in Fast page mode cycles. 17. Access time is determined by the longest among t AA, t CAC and t CPA. 18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to the device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don’t care during test mode. Test mode is set by performing a -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular beforerefresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 15 HM5116400 Series, HM5117400 Series 21. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. +16 HM5116400 Series, HM5117400 Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If the internal refresh counter is used, a minimum of eight -beforerefresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + t AA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + t AA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. leading edge in early write cycles and to leading 15. These parameters are referred to edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in Fast page mode cycles. 17. Access time is determined by the longest among t AA, t CAC and t CPA. 18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to the device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don’t care during test mode. Test mode is set by performing a -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular beforerefresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 15 HM5116400 Series, HM5117400 Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD t CRP t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH WE t DS Din Dout t DH Din High-Z* * t WCS 18 t WCS (min) HM5116400 Series, HM5117400 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS WE t DZC Din t DS High-Z t DH Din t DZO t OEH t OED OE t OEZ t CLZ High-Z Dout Invalid Dout 19 HM5116400 Series, HM5117400 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR Address t RAH t ASC Row t CAH Column t RCS t CWD t CWL t AWD t RWL t RWD t WP WE t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA OE t CAC t OEZ t AA t RAC t OHO Dout Dout t CLZ 20 High-Z HM5116400 Series, HM5117400 Series -Only Refresh Cycle t RC t RAS t RP tT t CRP t RPC t ASR Address t CRP t RAH Row t OFF Dout High-Z 21 HM5116400 Series, HM5117400 Series -Before- Refresh Cycle t RC t RP t RPC t RAS t CSR t RP t CHR t RPC tT t CP t WRP t WRH t CP Address t OFF Dout 22 High-Z t CRP HM5116400 Series, HM5117400 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASC t ASR t RAH Address t RAL Row t CAH Column t WRP t RRH t RCS t WRH t WRP t WRH WE t DZC t CDD High-Z Din t DZO t OED t OEA OE t CAC t OEZ t OHO t AA t RAC t OFF t OH t CLZ Dout Dout 23 HM5116400 Series, HM5117400 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t PC t CSH t RCD t CAS t CP t RSH t CP t CAS t CRP t CAS CAS t RAD Address t RAL t CAL t ASR t RAH t CAL t ASC t CAH t CAL t ASC t CAH t ASC t CAH Row Column 1 Column 2 Column N t RCS t RCS t RCH t RCS t RRH t RCH t RCH WE t DZC Din t DZO t DZC t DZC t CDD t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED OE t RAC t AA t OH t OEA 24 t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N HM5116400 Series, HM5117400 Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS Address t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS t WCS (min) 25 HM5116400 Series, HM5117400 Series Fast Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t DH Din 2 t DZO t OED Din N t DZO t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout 26 Invalid Dout Invalid Dout HM5116400 Series, HM5117400 Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL Column N t CPW t AWD t CWL t CPW t AWD t CWD t RCS t CWL t AWD t CWD t RCS t RWL t CWD WE t RCS t WP t WP t DZC t DS t WP t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OEH Din N t OED t DZO t OEH t OEH OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t OHO t OEA t CAC t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N 27 HM5116400 Series, HM5117400 Series Test Mode Cycle*19 Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L 28 HM5116400 Series, HM5117400 Series Test Mode Set Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC t CRP tT CAS t CP t WTS t WTH t CP WE Address t OFF Dout High-Z 29 HM5116400 Series, HM5117400 Series Package Dimensions HM5116400S/LS Series HM5117400S/LS Series (CP-26/24DB) 26 1 16.90 17.27 Max 21 19 6 8 0.74 Unit: mm 14 13 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 2.54 6.71 ± 0.25 0.10 Hitachi Code JEDEC Code EIAJ Code Weight 30 CP-26/24DB MO-077-AA SC-632-A 0.8 g HM5116400 Series, HM5117400 Series HM5116400TS/LTS Series HM5117400TS/LTS Series (TTP-26/24DA) 26 0.42 0.40 17.14 17.54 Max 21 19 1 6 8 1.27 0.08 0.06 0.21 M 1.15 Max Unit: mm 14 13 0.80 9.22 0.20 0–5 0.50 2.54 0.10 0.10 Hitachi Code JEDEC Code EIAJ Code Weight TTP-26/24DA MO-132AB — 0.30 g 31 HM5116400 Series, HM5117400 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 32 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 HM5116400 Series, HM5117400 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 1.0 Oct. 14, 1996 Initial issue Y. Kasama M. Mishima 2.0 Nov. 14, 1996 Addition of HM5116400-5 Series Y. Kasama Y. Matsuno Addition of HM5117400-5 Series Power dissipation (active) 605/550 mW(max) to 550/495/440 mW (max) (HM5117400 Series) DC Characteristics (HM5117400 Series) I CC1 max: 110/100 mA to 100/90/80 mA I CC3 max: 110/100 mA to 100/90/80 mA I CC6 max: 110/100 mA to 100/90/80 mA 3.0 Feb. 27, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns 33