HANBit HMD8M36M18G 32Mbyte(8Mx36) 72-pin FP with Parity MODE 2K Ref. SIMM Design 5V Part No. HMD8M36M18, HMD8M36M18G GENERAL DESCRIPTION The HMD8M36M18G is a 8M x 36bit dynamic RAM high density memory module. The module consists of sixteen CMOS 4M x 4bit DRAM in 24-pin SOJ packages and two CMOS 4Mx 4bit Quad-CAS DRAM in 28pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible. PIN ASSIGNMENT FEATURES w Part Identification PIN SYMBOL PIN SYMBOL PIN SYMBO L PIN SYMBOL HMD8M36M18---- 2048 Cycles/32ms Ref. Solder Lead 1 Vss 19 A10 37 DQ17 55 DQ12 HMD8M36M18G-- 2048 Cycles/32ms Ref. Gold Lead 2 DQ0 20 DQ4 38 DQ35 56 DQ30 w Access times : 50, 60ns 3 DQ18 21 DQ22 39 Vss 57 DQ13 w High-density 32MByte design 4 DQ1 22 DQ5 40 /CAS0 58 DQ31 w Single + 5V ±0.5V power supply 5 DQ19 23 DQ23 41 /CAS2 59 Vcc w JEDEC standard PDpin and pinout 6 DQ2 24 DQ6 42 /CAS3 60 DQ32 w Fast Page with Parity mode operation 7 DQ20 25 DQ24 43 /CAS1 61 DQ14 w /CAS-before-/RAS refresh capability 8 DQ3 26 DQ7 44 /RAS0 62 DQ33 w/RAS-only and Hidden refresh capability 9 DQ21 27 DQ25 45 /RAS1 63 DQ15 w TTL compatible inputs and outputs 10 Vcc 28 A7 46 NC 64 DQ34 w FR4-PCB design 11 NC 29 NC 47 /WE 65 DQ16 12 A0 30 Vcc 48 NC 66 NC 13 A1 31 A8 49 DQ9 67 PD1 -5 14 A2 32 A9 50 DQ27 68 PD2 -6 15 A3 33 NC 51 DQ10 69 PD3 16 A4 34 NC 52 DQ28 70 PD4 17 A5 35 DQ26 53 DQ11 71 NC 18 A6 36 DQ8 54 DQ29 72 Vss OPTIONS MARKING w Timing 50ns access 60ns access w Packages 72-pin SIMM M PRESENCE DETECT PINS(Optional) Pin 50ns 60ns PD1 NC NC PD2 Vss Vss PD3 Vss NC PD4 Vss NC SIMM TOP VIEW Note: A11 is used for only 4K Ref. PERFORMANCE RANGE Speed tRAC tCAC tRC 5 50ns 13ns 90ns 6 60ns 15ns 110ns URL:www.hbeoc.kr REV.1.0 (August.2002) -1- HANBit Electronics Co.,Ltd. HANBit HMD8M36M18G FUNCTIONAL BLOCK DIAGRAM /CAS0 /RAS0 /CAS0 /RAS0 /OE /W /CAS0 /RAS0 /OE /W /CAS1 /CAS1 /RAS0 /OE /W /CAS1 /RAS0 /OE /W /CAS0 /CAS1 /CAS2 /CAS3 /RAS0 /OE /W /CAS2 /CAS2 /RAS0 /OE DQ3 /CAS2 /RAS0 /OE DQ3 /CAS3 /CAS3 /RAS0 /OE DQ3 /CAS3 /RAS0 /OE DQ3 U2 A0-A10 U4 A0-A10 U6 A0-A10 U8 A0-A10 U1 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0-3 DQ4-7 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ9-12 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ13-16 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ8 DQ17 DQ26 DQ35 U3 /W U5 /W U7 /W U9 /W U11 /W /W DQ0 DQ1 DQ18-21 DQ2 DQ3 DQ0 DQ1 DQ2 A0-A10 DQ0 DQ1 DQ22-25 DQ2 DQ3 DQ0 DQ1 DQ2 A0-A10 DQ0 DQ1 DQ27-30 DQ2 DQ3 DQ0 DQ1 DQ2 A0-A10 DQ0 DQ1 DQ31-34 DQ2 DQ3 /CAS0 /RAS1 A0-A10 /OE U15 /W A0-A10 /CAS1 /RAS1 /OE U17 /W /CAS1 /RAS1 A0-A10 /OE /CAS0 /CAS1 /CAS2 /CAS3 /RAS1 A0-A10 /OE U10 /W DQ0 DQ1 DQ2 A0-A10 /CAS0 /RAS1 A0-A10 /OE U13 DQ0 DQ1 DQ2 DQ3 A0-A10 /WE A0-A10 URL:www.hbeoc.kr REV.1.0 (August.2002) DQ0 DQ1 DQ2 DQ3 U12 /W /CAS2 /RAS1 A0-A10 /OE U14 /W /CAS2 /RAS1 A0-A10 /OE U16 /W /CAS3 /RAS1 A0-A10 /OE U18 /W /CAS3 /RAS1 A0-A10 /OE Vcc Vss -2- 0.1uF or Capacitor for each DRAM HANBit Electronics Co.,Ltd. 0.22uF HANBit HMD8M36M18G ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 7.0V Voltage on Vcc Supply Relative to Vss Vcc -1V to 7.0V Power Dissipation PD 18W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 1008 mA -6 - 918 mA Don't care - 36 mA -5 - 1008 mA -6 - 918 mA -5 - 828 mA -6 - 738 mA Don't care - 18 mA -5 - 1008 mA -6 - 918 mA Il(L) -90 90 µA IO(L) -10 10 µA ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 VOH 2.4 - V VOL - 0.4 V ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=VIH, /RAS, Address cycling @tRC=min ) URL:www.hbeoc.kr REV.1.0 (August.2002) -3- HANBit Electronics Co.,Ltd. HANBit HMD8M36M18G ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE o ( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance [A0-A11(A10)] CIN1 - 110 pF Input Capacitance (/W) C IN2 - 130 pF Input Capacitance (/RAS0) CIN3 - 80 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 40 pF Input/Output Capacitance (DQ0-31) CDQ1 - 25 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 STANDARD OPERATION -6 SYMBOL UNIT MIN MAX MAX Random read or write cycle time tRC Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 3 Output buffer turn-off delay tOFF 3 13 3 13 ns Transition time (rise and fall) tT 2 50 2 50 ns /RAS precharge time tRP 30 /RAS pulse width tRAS 50 /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 50 60 ns /CAS pulse width tCAS 13 10K 15 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns URL:www.hbeoc.kr REV.1.0 (August.2002) -4- 90 MIN 110 ns 3 ns 40 10K 60 ns 10K ns HANBit Electronics Co.,Ltd. HANBit HMD8M36M18G Column address set-up time tASC 0 0 ns Column address hold time tCAH 10 10 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 Write command hold time tWCH 10 10 ns Write command hold referenced to /RAS tWCR 50 55 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 13 15 ns Write command to /CAS lead time tCWL 13 15 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 10 15 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 5 5 ns /CAS hold time (C-B-R refresh) tCHR 10 10 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA /CAS precharge time (Fast page) tCP 10 /RAS pulse width (Fast page ) tRASP 50 /W to /RAS precharge time (C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns 64 ns 64 30 35 10 200K 60 ns ns ns 200K ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. URL:www.hbeoc.kr REV.1.0 (August.2002) -5- HANBit Electronics Co.,Ltd. HANBit HMD8M36M18G TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE tRC tRAS VIH/RAS tRP VILtCRP tCSH tRCD tCRP tRSH /CAS VIH- tCAS tRAD VILtASR tRAH tCAH tASC tRAL VIHA VIL- ROW ADDRESS COLUMN ADDRESS tRCS tRRH tRCH VIH/W VIL- tAA tOFF tCAC tCLZ tRAC DQ0-DQ7 VOHVOL- DATA-OUT OPEN TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) NOTE : Dout = Open tRC /RAS VIH- tRP tRAS VILtCRP tCSH tRCD VIH/CAS tCAS tRAD VILtASR A tCRP tRSH tRAH tCAH tASC tRAL VIHVIL- ROW ADDRESS COLUMN ADDRESS tCWL tRWL tWCS tWCH VIHtWP /W VIL- tDS DQ0-DQ7 tDH VOHVOL- URL:www.hbeoc.kr REV.1.0 (August.2002) DATA-IN -6- HANBit Electronics Co.,Ltd. HANBit HMD8M36M18G PACKAGING INFORMATION SIMM Design (Front) 2.54 mm 0.25 mm MAX MIN 1.29 ±0.08mm Gold : 1.04±0.10 mm Solder:0.914±0.10mm 1.27 ORDERING INFORMATION Part Number Density Org. Package Vcc SPEED HMD8M36M18G-5 32MByte 8MX 36bit 72 Pin-SIMM 5.0V 50ns HMD8M36M18G-6 32MByte 8MX 36bit 72 Pin-SIMM 5.0V 60ns URL:www.hbeoc.kr REV.1.0 (August.2002) -7- HANBit Electronics Co.,Ltd.