HANBit HMD16M32M8GH 64Mbyte (16Mx36) FP Mode 4K Ref. 72pin-SIMM Design Part No. HMD16M32M8GH GENERAL DESCRIPTION The HMD16M32M8GH is a 16M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 4bit DRAMs in 32-pin SOJ or TSOP packages mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a Single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible. PIN ASSIGNMENT FEATURES wPart Identification PIN HMD16M32M8GH ---4K Cycles/64ms Ref, Gold w Access times : 50, 60ns w High-density 64MByte design w Single + 5V ±0.5V power supply w JEDEC standard Pdpin & pinout w TTL compatible inputs and outputs w/CAS-before-/RAS & Hidden Refresh capability w/RAS-only refresh capability wFast Page Mode Operation OPTIONS MARKING w Timing 50ns access 60ns access -5 -6 w Packages 72-pin SIMM M PERFORMANCE RANGE Speed tRAC tCAC tRC 5 50ns 13ns 90ns 6 60ns 15ns 110ns PI N SYMBOL PI N SYMBO L A10 37 NC 55 DQ12 DQ4 38 NC 56 DQ30 39 Vss 57 DQ13 40 /CAS0 58 DQ31 41 /CAS2 59 Vcc 42 /CAS3 60 DQ32 43 /CAS1 61 DQ14 44 /RAS0 62 DQ33 SYMBOL PIN SYMBOL 1 Vss 19 2 DQ0 20 3 DQ18 21 DQ22 4 DQ1 22 DQ5 5 DQ19 23 DQ23 6 DQ2 24 DQ6 7 DQ20 25 DQ24 8 DQ3 26 DQ7 9 DQ21 27 DQ25 45 NC 63 DQ15 10 Vcc 28 A7 46 NC 64 DQ34 11 NC 29 A11 47 /W 65 DQ16 12 A0 30 Vcc 48 NC 66 NC 13 A1 31 A8 49 DQ9 67 PD1 14 A2 32 A9 50 DQ27 68 PD2 15 A3 33 NC 51 DQ10 69 PD3 16 A4 34 /RAS2 52 DQ28 70 PD4 17 A5 35 NC 53 DQ11 71 NC 18 A6 36 NC 54 DQ29 72 Vss PRESENCE DETECT PINS Pin 50ns 60ns PD1 Vss Vss PD2 NC NC PD3 Vss NC PD4 Vss NC URL:www.hbe.co.kr REV.1.0 (August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8GH FUNCTIONAL BLOCK DIAGRAM DQ0-DQ35 /CAS0 /RAS0 CAS CAS RAS RAS OE W OE W CAS CAS RAS RAS OE W OE W CAS CAS RAS W RAS W /CAS1 CAS CAS RAS RAS OE W OE W CAS CAS RAS RAS OE W OE W CAS CAS RAS W RAS W DQ0 DQ0-DQ3 DQ1 DQ2 A0-A11 DQ3 A0-A11 U0 U1 /CAS2 /RAS2 DQ0 DQ4-DQ7 DQ1 DQ2 A0-A11 DQ3 A0-A11 U1 U2 U2 U10 CAS RAS OE W D DQ8 Q CAS RAS A0-A11 A0-A11 DQ0 U0 U5 DQ9-DQ12 DQ1 A0-A11 A0-A11 /CAS3 DQ2 DQ3 DQ0 U1 U6 DQ13-DQ16 DQ1 A0-A11 A0-A11 U9 U2 CAS RAS OE W D DQ17 Q W CAS RAS OE W CAS RAS A0-A11 A0-A11 A0-A11 U8 DQ22-DQ25 A0-A11 U3 CAS RAS OE W DQ2 DQ3 U7 DQ18-DQ21 DQ26 A0-A11 U11 DQ27-DQ30 A0-A11 U12 DQ31-DQ34 A0-A11 U4 W DQ35 A0-A11 /W A0-A11 URL:www.hbe.co.kr REV.1.0 (August.2002) 2 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8GH ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 7.0V Voltage on Vcc Supply Relative to Vss Vcc -1V to 7.0V Power Dissipation PD 12W TSTG -55oC to 125oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc V Input Low Voltage VIL -1.0 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 1080 mA -6 - 960 mA Don’t care - 24 mA -5 - 1080 mA -6 - 960 mA -5 - 840 mA -6 - 600 mA Don’t care - 12 mA -5 - 1080 mA -6 - 960 mA -10 10 µA -5 5 µA ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Il(L) Don’t care IO(L) VOH 2.4 - V VOL - 0.4 V ICC1 : Operating Current * (/RAS , /CAS , Address cycling @tRC=min.) URL:www.hbe.co.kr REV.1.0 (August.2002) 3 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8GH ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE o ( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A11) CIN1 - 50 pF Input Capacitance (/W) C IN2 - 66 pF Input Capacitance (/RAS0) CIN3 - 38 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 24 pF Input/Output Capacitance (DQ0-31) CDQ1 - 17 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 PARAMETER -6 SYMBOL UNIT MIN MAX MAX Random read or write cycle time tRC Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 3 Output buffer turn-off delay tOFF 3 13 3 15 ns Transition time (rise and fall) tT 1 50 1 50 ns /RAS precharge time tRP 30 /RAS pulse width tRAS 50 /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 38 45 ns /CAS pulse width tCAS 8 10K 10 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns URL:www.hbe.co.kr REV.1.0 (August.2002) 84 MIN 4 104 ns 3 ns 40 10K 60 ns 10K ns HANBit Electronics Co.,Ltd. HANBit HMD16M32M8GH /RAS to column address delay time tRAD 15 25 15 /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 8 10 ns Column address hold referenced to /RAS tAR 50 55 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 ns Write command hold time tWCH 10 10 ns Write command hold referenced to /RAS tWCR 50 55 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 13 10 ns Write command to /CAS lead time tCWL 8 10 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 8 10 ns Data-in hold referenced to /RAS tDHR 50 55 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 5 5 ns /CAS hold time (C-B-R refresh) tCHR 10 10 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA Fast page mode cycle time tPC 40 45 ns /CAS precharge time (Fast page) tCP 8 10 ns /RAS pulse width (Fast page ) tRASP 50 /W to /RAS precharge time(C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns /CAS precharge(C-B-R counter test) tCPT 20 30 ns 64 64 28 200K 30 35 60 200K ns ns ns ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. URL:www.hbe.co.kr REV.1.0 (August.2002) 5 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8GH 5.Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD anf tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. URL:www.hbe.co.kr REV.1.0 (August.2002) 6 HANBit Electronics Co.,Ltd. HANBit HMD16M32M8GH PACKAGING INFORMATION SIMM Design Unit : mm 107.95 ± 0.20 3.38 3.38 27.0 ±0.2 10.16 6.35 1 71 2.03 1.0 6.35 1.27 3.34 95.25 6.35 Front View 2 72 Back View 0.25 2.54 MAX MIN 1.27 Gold : 1.04±0.10 Solder:0.914±0.10 1.27 ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE SPEED HMD16M32M8GH-5 64Byte x 32 72 Pin-SIMM-Gold 4K 5V FPM 50ns HMD16M32M8GH-6 64Byte x 32 72 Pin-SIMM-Gold 4K 5V FPM 60ns URL:www.hbe.co.kr REV.1.0 (August.2002) 7 HANBit Electronics Co.,Ltd.