HANBit HMD4M32M2VE 16Mbyte(4Mx32) DRAM SIMM EDO MODE, 4K Refresh, 3.3V Part No. HMD4M32M2VE, HMD4M32M2VEG GENERAL DESCRIPTION The HMD4M32M2VE is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of two CMOS 4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 3.3V DC power supply. All inputs and outputs are LVTTL-compatible. FEATURES PIN ASSIGNMENT w Part Identification HMD4M32M2VE----Lead finish Solder HMD4M32M2VEG- Lead finish Gold w Access times : 50, 60ns w High-density 16MByte design w 4K Cycles/64ms Ref, Gold w Single +3.3V± 0.3V power supply wJEDEC standard pinout w EDO Mode operation w LVTTL compatible inputs and outputs w FR4-PCB design OPTIONS MARKING w Timing PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 VSS 19 A10 37 NC 55 DQ11 2 DQ0 20 DQ4 38 NC 56 DQ27 3 DQ16 21 DQ20 39 VSS 57 DQ12 4 DQ1 22 DQ5 40 /CAS0 58 DQ28 5 DQ17 23 DQ21 41 /CAS2 59 VCC 6 DQ2 24 DQ6 42 /CAS3 60 DQ29 7 DQ18 25 DQ22 43 /CAS1 61 DQ13 8 DQ3 26 DQ7 44 /RAS0 62 DQ30 9 DQ19 27 DQ23 45 NC 63 DQ14 10 VCC 28 A7 46 NC 64 DQ31 11 NC 29 A11 47 /W 65 DQ15 12 A0 30 VCC 48 NC 66 NC 13 A1 31 A8 49 DQ8 67 PD1 50ns access -5 14 A2 32 A9 50 DQ24 68 PD2 60ns access -6 15 A3 33 NC 51 DQ9 69 PD3 16 A4 34 NC 52 DQ25 70 PD4 17 A5 35 NC 53 DQ10 71 NC 18 A6 36 NC 54 DQ26 72 VSS w Packages 72-pin SIMM M PERFORMANCE RANGE Speed tRAC tCAC tRC 5 50ns 13ns 84ns 6 60ns 15ns 104ns PIN NAMES Pin Name Function Pin Name Function Pin Name Function A0-A11 Address Input(4K Ref) /RAS0 Row Address Strobe Vss Ground DQ0-DQ31 Data In/Out /CAS0 - /CAS3 Column Address Strobe NC No Connection Read/Write Input PD1 - PD4 Presence Detect Vcc Power(+3.3V) /W URL:www.hbe.co.kr REV.1.0 (August.2002) 1 H ANBit Electronics Co.,Ltd. HANBit HMD4M32M2VE FUNCTIONAL BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U0 /RAS /RAS0 /CAS0 /CAS1 /LCAS /UCAS /OE /W DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 /RAS /CAS2 /CAS3 DQ0-DQ7 /LCAS DQ8-DQ15 DQ16-DQ23 /UCAS /OE /W A0-A11 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ24-DQ31 /W A0-A11 Vcc Vss URL:www.hbe.co.kr REV.1.0 (August.2002) 2 0.1uF or Capacitor for each DRAM 0.22uF Toall DRAMs H ANBit Electronics Co.,Ltd. HANBit HMD4M32M2VE ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -0.5V to 6.5V Voltage on Vcc Supply Relative to Vss Vcc -0.5V to 4.6V Power Dissipation PD 2W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 3.0 3.3 3.6 V Ground Vss 0 0 0 V Input High Voltage VIH 2.0 - +5.5 V Input Low Voltage VIL -0.3 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 220 mA -6 - 200 mA - 4 mA -5 - 220 mA -6 - 200 mA -5 - 220 mA -6 - 200 mA - 600 mA -5 - 220 mA -6 - 200 mA Il(L) -10 10 µA IO(L) -10 10 µA ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 VOH 2.4 - V VOL - 0.4 V ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) URL:www.hbe.co.kr REV.1.0 (August.2002) 3 H ANBit Electronics Co.,Ltd. HANBit HMD4M32M2VE ICC3 : /RAS Only Refresh Current * (/CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE o ( TA=25 C, Vcc = 3.3V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A11) CIN1 - 10 pF Input Capacitance (/W) C IN2 - 14 pF Input Capacitance (/RAS0, /RAS1) CIN3 - 14 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 14 pF Input/Output Capacitance (DQ0-31) CDQ1 - 14 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 3.3V±10%, See notes 1,2.) -5 STANDARD OPERATION SYMBOL MIN -6 MAX MAX tRC Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 3 Transition time (rise and fall) tT 1 /RAS precharge time tRP 30 /RAS pulse width tRAS 50 /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 38 45 ns /CAS pulse width tCAS 8 10K 10 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns 4 104 UNIT Random read or write cycle time URL:www.hbe.co.kr REV.1.0 (August.2002) 84 MIN ns 3 50 ns 1 50 40 10K 60 ns ns 10K ns H ANBit Electronics Co.,Ltd. HANBit HMD4M32M2VE Column address hold time tCAH 8 10 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 ns Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 10 10 ns Write command to /CAS lead time tCWL 8 10 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 8 10 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 5 5 ns /CAS hold time (C-B-R refresh) tCHR 10 10 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA Fast page mode cycle time tPC 28 35 ns /CAS precharge time (Fast page) tCP 8 10 ns /RAS pulse width (Fast page ) tRASP 50 /W to /RAS precharge time (C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns 64 64 35 100K 40 60 100K ns ns ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. URL:www.hbe.co.kr REV.1.0 (August.2002) 5 H ANBit Electronics Co.,Ltd. HANBit HMD4M32M2VE TIMING DIAGRAM Please refer to attached timing diagram chart (I) PACKAGING INFORMATION SIMM Design 107.95 mm 101.19 mm 3.18 ±0.51 R1.57 mm 3.38 mm 19.00 10.16 mm 6.35 mm R1.57±1.0 mm 6.35 mm 2.00 6.35 95.25 mm 5.08 MAX 2.54 mm 0.25 mm MAX MIN 1.27 Gold : 1.04±10 mm 1.27±0.08 mm ORDERING INFORMATION Part Number HMD4M32M2VEG-5 HMD4M32M2VEG-6 URL:www.hbe.co.kr REV.1.0 (August.2002) Density Org. Package 16MByte 4MX 32bit 72 Pin-SIMM 16MByte 4MX 32bit 72 Pin-SIMM 6 Refresh Cycle 4,096 Cycles 64ms Ref. 4,096 Cycles 64ms Ref. Vcc SPEED 3.3V 50ns 3.3V 60ns H ANBit Electronics Co.,Ltd.