HANBit HMN88D Non-Volatile SRAM MODULE 64Kbit (8K x 8-Bit),28Pin DIP, 5V Part No. HMN88D GENERAL DESCRIPTION The HMN88D Nonvolatile SRAM is a 65,536-bit static RAM organized as 8,192 bytes by 8 bits. The HMN88D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN88D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES PIN ASSIGNMENT w Access time : 85, 100, 120, 150 ns w High-density design : 64Kbit Design w Battery internally isolated until power is applied w Industry-standard 28-pin 8K x 8 pinout w Unlimited writes cycles w Data retention in the absence of VCC w 10-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss w Commercial temperature operation NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE NC A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 28-pin Encapsulated Package OPTIONS MARKING w Timing 85 ns - 85 100 ns -100 120 ns -120 150 ns -150 URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 1 HANBit Electronics Co.,Ltd HANBit HMN88D FUNCTIONAL DESCRIPTION The HMN88D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A12) defines which of the 8,192 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN88D operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN88D acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN88D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (tW R) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge. The HMN88D provides full functional capability for VCC greater than 4.5 V and write protects by 4.37 V nominal. Powerdown/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD . When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and all outputs are high impedance. As VCC falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. BLOCK DIAGRAM PIN DESCRIPTION A0-A12 8K x 8 SRAM Block /OE /WE Power A0-A12 : Address Input DQ0-DQ7 /CE : Chip Enable VSS : Ground /CE DQ0-DQ7 : Data In / Data Out /CE Power – Fail Control VCC /WE : Write Enable /OE : Output Enable Lithium Cell VCC: Power (+5V) NC : No Connection URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 2 HANBit Electronics Co.,Ltd HANBit HMN88D TRUTH TABLE MODE /OE /CE /WE I/O OPERATION POWER Not selected X Output disable H H X High Z Standby L H High Z Active Read L L H DOUT Active Write X L L DIN Active ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VCC -0.3V to 7.0V VT -0.3V to 7.0V Operating temperature TOPR 0 to 70°C Storage temperature TSTG -40°C to 70°C Temperature under bias TBIAS -10°C to 70°C TSOLDER 260°C DC voltage applied on VCC relative to VSS DC Voltage applied on any pin excluding VCC relative to VSS Soldering temperature CONDITIONS VT≤ VCC+0.3 For 10 second NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER SYMBOL MIN TYPICAL MAX Supply Voltage VCC 4.5V 5.0V 5.5V Ground VSS 0 0 0 Input high voltage VIH 2.2 - VCC+0.3V Input low voltage VIL -0.3 - 0.8V NOTE: Typical values indicate operation at TA = 25℃ URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 3 HANBit Electronics Co.,Ltd HANBit HMN88D DC ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER Input Leakage Current Output Leakage Current CONDITIONS VIN=VSS to VCC /CE=VIH or /OE=VIH Or /WE=VIL SYMBOL MIN TYP. MAX UNIT ILI - - ± 1 mA ILO - - ± 1 mA Output high voltage IOH=-1.0mA VOH 2.4 - - V Output low voltage IOL= 2.1mA VOL - - 0.4 V Standby supply current /CE=VIH ISB - 4 2 ㎃ Standby supply current 0V≤ VIN≤ 0.2V, ISB1 - 2.5 100 mA ICC - 65 15 ㎃ Power-fail-detect voltage VPFD 4.30 4.37 4.50 V Supply switch-over voltage VSO - 3 - V /CE≥ VCC-0.2V, or VIN≥ VCC-0.2V Operating supply current Min.cycle,duty=100%, /CE=VIL, II/O=0㎃ CAPACITANCE (TA=25℃ , f=1MHz, VCC=5.0V) SYMBOL MAX MIN UNIT Input Capacitance DESCRIPTION Input voltage = 0V CONDITIONS CIN 10 - pF Input/Output Capacitance Output voltage = 0V CI/O 10 - pF CHARACTERISTICS (Test Conditions) PARAMETER Input pulse levels 0 to 3V Input rise and fall times 5 ns Input and output timing 1.5V reference levels Output load (including scope and jig) URL : www.hbe.co.kr Rev. 0.0 (April, 2002) +5V VALUE DOUT (unless otherwise specified) See Figures 1and 2 4 1.9KΩ +5V 100㎊ 1KΩ 1.9KΩ DOUT 5㎊ 1KΩ Figure 1. Figure 2. Output Load A Output Load B HANBit Electronics Co.,Ltd HANBit HMN88D READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER SYMBOL -70 CONDITIONS -85 -120 -150 UNIT MIN MAX MIN MAX MIN MAX MIN MAX 70 - 85 - 120 - 150 - ns Read Cycle Time t RC Address Access Time tACC Output load A - 70 - 85 - 120 - 150 ns Chip enable access time tACE Output load A - 70 - 85 - 120 - 150 ns Output enable to Output valid t OE Output load A - 35 - 45 - 60 - 70 ns Chip enable to output in low Z tCLZ Output load B 5 - 5 - 5 - 10 - ns Output enable to output in low Z tOLZ Output load B 5 - 0 - 0 - 5 - ns Chip disable to output in high Z tCHZ Output load B 0 25 0 35 0 45 0 60 ns Output disable to output high Z tOHZ Output load B 0 25 0 25 0 35 0 50 ns Output hold from address change t OH Output load A 10 - 10 - 10 - 10 - ns WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax ) PARAMETER SYMBOL Write Cycle Time tWC Chip enable to end of write tCW Address setup time Address valid to end of write Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write tAS tAW tWP tWR1 tWR2 Note 1 Note 2 Note 1 Note 1 Note 3 Note 3 tDW tDH1 tDH2 tWZ tOW -70 CONDITIONS Note 4 Note 5 Note 5 -120 -150 UNI Max T MIN MAX MIN MAX MIN MAX Min 70 - 85 - 120 - 150 - ns 65 - 75 - 100 - 100 - ns - 0 - ns - 90 - ns - 90 - ns - 5 - ns - 15 - ns - 50 - ns - 0 - ns - 0 - ns 40 0 50 ns - 5 - ns 0 65 55 5 15 30 Note 4 -85 0 10 0 5 25 - 0 75 65 5 15 35 0 10 0 0 30 - 0 100 85 5 15 45 0 10 0 0 NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE going low and /WE going low. 3. Either tW R1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state. URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 5 HANBit Electronics Co.,Ltd HANBit HMN88D POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V) MIN TYP. MAX UNIT VCC slew, 4.75 to 4.25V PARAMETER SYMBOL tPF CONDITIONS 300 - - ㎲ VCC slew, 4.75 to VSO tFS 10 - - ㎲ VCC slew, VSO to VPFD (max) tPU 0 - - ㎲ 40 80 120 ms 10 - - years 6 - - years 40 100 150 ㎲ Time during which SRAM Chip enable recovery time tCER is write-protected after VCC passes VPFD on power-up. Data-retention time in TA = 25℃ tDR Absence of VCC Data-retention time in TA = 25℃ ; industrial tDR-N Absence of VCC temperature range (-N) only Delay after VCC slews down Write-protect time tW PT past VPFD before SRAM is Write-protected. TIMING WAVEFORM 1,2 - READ CYCLE NO.1 (Address Access)* tRC Address tACC tOH Previous Data Valid DOUT Data Valid *1,3,4 - READ CYCLE NO.2 (/CE Access) tRC /CE tACE tCHZ tCLZ DOUT URL : www.hbe.co.kr Rev. 0.0 (April, 2002) High-Z High-Z 6 HANBit Electronics Co.,Ltd HANBit HMN88D *1,5 - READ CYCLE NO.3 (/OE Access) tRC Address tACC /OE tOE DOUT tOHZ tOLZ Data Valid High-Z High-Z NOTES: 1. /WE is held high for a read cycle. 2. Device is continuously selected: /CE = /OE =VIL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = VIL. 5. Device is continuously selected: /CE = VIL - WRITE CYCLE NO.1 (/WE-Controlled) *1,2,3 tWC Address tAW tWR1 tCW /CE tAS tWP /WE tDW DIN Data-in Valid tWZ DOUT Data Undefined (1) URL : www.hbe.co.kr Rev. 0.0 (April, 2002) tDH1 7 tOW High-Z HANBit Electronics Co.,Ltd HANBit HMN88D - WRITE CYCLE NO.2 (/CE-Controlled) *1,2,3,4,5 tWC Address tAW tAS tWR2 tCW /CE tWP /WE tDH2 tDW Data-in Valid DIN tWZ DOUT High-Z Data Undefined (2) NOTE: 1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tW R2 must be met. 5. Either tDH1 or tDH2 must be met. - POWER-DOWN/POWER-UP TIMING tPF VCC 4.75 VPFD VPFD 4.25 VSO VSO tFS tPU tCER tDR tWPT /CE URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 8 HANBit Electronics Co.,Ltd HANBit HMN88D PACKAGE DIMENSION Dimension Min Max A 1.470 1.500 B 0.710 0.740 C 0.365 0.375 D 0.012 - E 0.008 0.013 F 0.590 0.630 G 0.017 0.023 H 0.090 0.110 I 0.075 0.110 J 0.120 0.150 J A I H G B C D E F ORDERING INFORMATION H M N 8 8 D - 70 I Operating Temp. : Blank = Commercial (0 to 70 °C ) I = Industrial (-40 to 85°C) Speed options : 70 = 70 ns 85 = 85 ns 1 20 = 120 ns 1 50 = 150 ns Dip type package Device : 8K x 8 bit Nonvolatile Timekeeping SRAM HANBit Memory Module URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 9 HANBit Electronics Co.,Ltd