TI BQ4017MC-70

bq4017/bq4017Y
2048Kx8 Nonvolatile SRAM
Features
General Description
➤ Data retention in the absence of
power
The CMOS bq4017 is a nonvolatile
16,777,216-bit static RAM organized
as 2,097,152 words by 8 bits. The
integral control circuitry and lithium energy source provide reliable
nonvolatility coupled with the unlimited write cycles of standard
SRAM.
➤ Automatic write-protection during power-up/power-down cycles
➤ Conventional SRAM operation;
unlimited write cycles
➤ 5-year minimum data retention
in absence of power
➤ Battery internally isolated until
power is applied
Pin Connections
NC
A20
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is
unconditionally write-protected to
prevent an inadvertent write operation.
Pin Names
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VCC
A19
NC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
The bq4017 uses extremely low
standby current CMOS SRAMs, coupled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
The bq4017 has the same interface
as industry-standard SRAMs and
requires no external circuitry.
Block Diagram
A0–A20
Address inputs
DQ0–DQ7
Data input/output
CE
Chip enable input
OE
Output enable input
WE
Write enable input
VCC
Supply voltage input
VSS
Ground
NC
No connect
36-Pin DIP Module
PN401701.eps
Selection Guide
Part
Number
bq4017MC -70
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
70
-5%
Part
Number
bq4017YMC -70
5/95
1
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
70
-10%
bq4017/bq4017Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4017 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4017 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold
VPFD. The bq4017 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4017Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
The internal coin cells used by the bq4017 have an extremely long shelf life. The bq4017 provides data retention for more than 5 years in the absence of system
power.
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs become high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
As shipped from Unitrode, the integral lithium cells are
electrically isolated from the memory. (Self-discharge in
this condition is approximately 0.5% per year.) Following the first application of VCC, this isolation is broken,
and the lithium backup provides data retention on subsequent power-downs.
Truth Table
Mode
CE
WE
OE
I/O Operation
Power
Not selected
H
X
X
High Z
Standby
Output disable
L
H
H
High Z
Active
Read
L
H
L
DOUT
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
TOPR
Operating temperature
0 to +70
°C
TSTG
Storage temperature
-40 to +70
°C
TBIAS
Temperature under bias
-10 to +70
°C
TSOLDER
Soldering temperature
+260
°C
Note:
Conditions
VT ≤ VCC + 0.3
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
2
bq4017/bq4017Y
Recommended DC Operating Conditions (TA = 0 to 70°C)
Symbol
VCC
Parameter
Minimum
Typical
Maximum
Unit
4.5
5.0
5.5
V
bq4017Y
4.75
5.0
5.5
V
bq4017
0
0
0
V
Supply voltage
VSS
Supply voltage
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (TA = 0 to 70°C, VCCmin
Symbol
Notes
Parameter
≤ VCC ≤ VCCmax)
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±4
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±4
µA
CE = VIH or OE = VIH or
WE = VIL
VOH
Output high voltage
2.4
-
-
V
IOH = -1.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 2.1 mA
ISB1
Standby supply current
-
7
17
mA
CE = VIH
ISB2
Standby supply current
-
2.5
5
mA
0V ≤ VIN ≤ 0.2V,
CE ≥ VCC - 0.2V,
or VIN ≥ VCC - 0.2
Min. cycle, duty = 100%,
CE = VIL ,II/O = 0mA,
A19 < VIL or A19 > VIH,
A20 < VIL or A20 > VIH
ICC
Operating supply current
VPFD
Power-fail-detect voltage
VSO
Note:
Supply switch-over voltage
-
75
115
mA
4.55
4.62
4.75
V
bq4017
4.30
4.37
4.50
V
bq4017Y
-
3
-
V
Typical values indicate operation at TA = 25°C, VCC = 5V.
3
bq4017/bq4017Y
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
CI/O
Input/output capacitance
-
-
40
pF
Output voltage = 0V
CIN
Input capacitance
-
-
40
pF
Input voltage = 0V
Note:
These parameters are sampled and not 100% tested.
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 1 and 2
Figure 1. Output Load A
Read Cycle
Figure 2. Output Load B
(TA = 0 to 70°C, VCCmin ≤ VCC ≤ VCCmax)
-70
Symbol
Parameter
Min.
Max.
Unit
Conditions
tRC
Read cycle time
70
-
ns
tAA
Address access time
-
70
ns
Output load A
tACE
Chip enable access time
-
70
ns
Output load A
tOE
Output enable to output valid
-
35
ns
Output load A
tCLZ
Chip enable to output in low Z
5
-
ns
Output load B
tOLZ
Output enable to output in low Z
5
-
ns
Output load B
tCHZ
Chip disable to output in high Z
0
25
ns
Output load B
tOHZ
Output disable to output in high Z
0
25
ns
Output load B
tOH
Output hold from address change
10
-
ns
Output load A
4
bq4017/bq4017Y
1,2
Read Cycle No. 1 (Address Access)
Read Cycle No. 2 (CE Access)
1,3,4
Read Cycle No. 3 (OE Access)
1,5
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
5
bq4017/bq4017Y
Write Cycle
(TA = 0 to 70°C, VCCmin ≤ VCC ≤ VCCmax)
-70
Symbol
Parameter
Min.
Max.
Units
Conditions/Notes
tWC
Write cycle time
70
-
ns
tCW
Chip enable to end of write
65
-
ns
(1)
tAW
Address valid to end of write
65
-
ns
(1)
tAS
Address setup time
0
-
ns
Measured from address valid to beginning of write. (2)
tWP
Write pulse width
55
-
ns
Measured from beginning of write to
end of write. (1)
tWR1
Write recovery time
(write cycle 1)
5
-
ns
Measured from WE going high to
end of write cycle. (3)
tWR2
Write recovery time
(write cycle 2)
15
-
ns
Measured from CE going high to
end of write cycle. (3)
tDW
Data valid to end of write
30
-
ns
Measured to first low-to-high transition of either CE or WE.
tDH1
Data hold time
(write cycle 1)
0
-
ns
Measured from WE going high to
end of write cycle. (4)
tDH2
Data hold time
(write cycle 2)
10
-
ns
Measured from CE going high to
end of write cycle. (4)
tWZ
Write enabled to output in high Z
0
25
ns
I/O pins are in output state. (5)
tOW
Output active from end of write
5
-
ns
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
6
bq4017/bq4017Y
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
7
bq4017/bq4017Y
Power-Down/Power-Up Cycle (TA = 0 to 70°C)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tPF
VCC slew, 4.75 to 4.25 V
300
-
-
µs
tFS
VCC slew, 4.25 to VSO
10
-
-
µs
tPU
VCC slew, VSO to VPFD
(max.)
0
-
-
µs
t
Chip enable recovery time
40
80
120
ms
tDR
Data-retention time in
absence of VCC
5
-
-
years
tWPT
Write-protect time
40
100
150
µs
CER
Notes:
Conditions
Time during which SRAM
is write-protected after
VCC passes VFPD on
power-up.
TA = 25°C. (2)
Delay after VCC slews
down past VPFD before
SRAM is write-protected.
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
8
bq4017/bq4017Y
MC: 36-Pin C-Type Module
36-Pin MC (C-Type Module)
Dimension
Minimum
A
0.365
A1
0.015
B
0.017
C
0.008
D
2.070
E
0.710
e
0.590
G
0.090
L
0.120
S
0.175
All dimensions are in inches.
9
Maximum
0.375
0.023
0.013
2.100
0.740
0.630
0.110
0.150
0.210
bq4017/bq4017Y
Ordering Information
bq4017
MC Temperature:
blank = Commercial (0 to +70°C)
Speed Options:
70 = 70 ns
Package Option:
MC = C-type module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4017 2048K x 8 NVSRAM
10
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