HOLTEK HT46CU25

HT46RU25/HT46CU25
A/D Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0013E HT48 & HT46 LCM Interface Design
- HA0047E An PWM application example using the HT46 series of MCUs
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
at VDD=5V
· 16-level subroutine nesting
· System clock (fSYS): 400kHz~8MHz, 32.768kHz
· 8-channels 12-bit resolution A/D converter
· 48 bidirectional I/O lines (max.)
· 4-channels (6+2)/(7+1)-bit PWM output shared with
· One interrupt input shared with an I/O line
four I/O lines
· One 8-bit and two 16-bit programmable timer/event
· Universal Asynchronous Receiver Transmitter
counter with prescaler and PFD (programmable
frequency divider) function and overflow interrupt
· Bit manipulation instruction
· 16K´16 program memory in two banks (Bank 0, 1)
· 16-bit table read instruction
· 576´8 (192´3) data memory RAM
· 63 powerful instructions
(UART)
(address from 040H~0FFH, bank 0~2)
· All instructions in one or two machine cycles
· On-chip crystal and RC oscillator
· Low voltage reset function
· Watchdog Timer
· I2C Bus (slave mode)
· Supports PFD for sound generation
· 48/56-pin SSOP package
· Real Time Clock (RTC) with 8-bit prescaler
· HALT function and wake-up feature reduce power
consumption
General Description
The HT46RU25/HT46CU25 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46CU25 is fully pin and functionally compatible
with the OTP version HT46RU25 device.
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, UART function, I2C interface, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D
application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
I2C is a trademark of Philips Semiconductors.
Rev. 1.30
1
March 9, 2007
HT46RU25/HT46CU25
Block Diagram
In te rru p t
C ir c u it
S T A C K
P ro g ra m
E P R O M
P ro g ra m
C o u n te r
IN T C
M
M P
M
T M R 0 C
T M R 0
P F D 0
M
M
T M R 1 C
T M R 1
P F D 1
B P
In s tr u c tio n
R e g is te r
T M R 2 C
T M R 2
P r e s c a le r
U
U
X
U
P r e s c a le r
X
X
P A 5
M U X
P G C
P G
A L U
S T A T U S
P F C
S h ifte r
T im in g
G e n e ra to r
O S
R E
V D
V S
O S
S
S
C 1
D
A C C
P o rt F
P F
P W
O S C 2
O S C 4
P o rt G
H A L T
X
U
fS
P o rt D
P D
L V R
U A R T B u s
C 3
fS
Y S
Y S
/4
/4
O S C 3
O S C 4
W D T O S C
X
W D T O S C
P G 0 ~ P G 7
P F 0 ~ P F 7
M
P D C
E N /D IS
Y S
T M R 0
R T C
In s tr u c tio n
D e c o d e r
fS
T M R 1
U
M
T im e
B a s e
Y S
T M R 2
W D T
D A T A
M e m o ry
fS
P C C
P o rt C
P C
P D 0 /P W M 0 ~ P D 3 /P W
P D 4 ~ P D 7
P C
P C
P C
P C
P C
0 /
1 /
2 ~
6 /
7 /
M 3
T X
R X
P C 5
O S C 3
O S C 4
8 -C h a n n e l
A /D C o n v e rte r
P B C
P o rt B
P B
P A C
P A
I2 C B u s
S la v e M o d e
Rev. 1.30
2
P o rt A
P B 0 /A N 0 ~ P B 7 /A N 7
P A
P A
P A
P A
P A
P A
0 ~
3 /
4
5 /
6 /
7 /
P A 2
P F D
IN T
S D A
S C L
March 9, 2007
HT46RU25/HT46CU25
Pin Assignment
P B 5 /A N 5
1
4 8
P B 6 /A N 6
P B 4 /A N 4
2
4 7
P B 7 /A N 7
P A 3 /P F D
3
4 6
P A 4
1
5 6
P B 6 /A N 6
2
5 5
P B 7 /A N 7
P A 3 /P F D
3
5 4
P A 4
P A 2
4
5 3
P A 5 /IN T
P A 1
5
5 2
P A 6 /S D A
P A 0
6
5 1
P A 7 /S C L
P B 3 /A N 3
7
5 0
P F 4
P A 2
4
4 5
P A 5 /IN T
P B 2 /A N 2
8
4 9
P F 5
P A 1
5
4 4
P A 6 /S D A
P B 1 /A N 1
9
4 8
P F 6
P A 0
6
4 3
P A 7 /S C L
P B 0 /A N 0
1 0
4 7
P F 7
P B 3 /A N 3
7
4 2
P F 4
T M R 2
1 1
4 6
O S C 2
P B 2 /A N 2
8
4 1
P F 5
P F 3
1 2
4 5
O S C 1
P B 1 /A N 1
9
4 0
P F 6
P F 2
1 3
4 4
V D D
P B 0 /A N 0
1 0
3 9
P F 7
P F 1
1 4
4 3
R E S
T M R 2
1 1
3 8
O S C 2
P D 7
1 5
4 2
T M R 1
P F 3
1 2
3 7
O S C 1
P D 6
1 6
4 1
P D 3 /P W M 3
P F 2
1 3
3 6
V D D
P D 5
1 7
4 0
P D 2 /P W M 2
P F 1
1 4
3 5
R E S
P D 4
1 8
3 9
P D 1 /P W M 1
P D 7
1 5
3 4
T M R 1
V S S
1 9
3 8
P D 0 /P W M 0
P D 6
1 6
3 3
P D 3 /P W M 3
P F 0
2 0
3 7
P C 7 /O S C 4
P D 5
1 7
3 2
P D 2 /P W M 2
T M R 0
2 1
3 6
P C 6 /O S C 3
P D 4
1 8
3 1
P D 1 /P W M 1
P C 0 /T X
2 2
3 5
P C 5
V S S
1 9
3 0
P D 0 /P W M 0
P C 1 /R X
2 3
3 4
P C 4
P F 0
2 0
2 9
P C 7 /O S C 4
P C 2
2 4
3 3
P C 3
T M R 0
2 1
2 8
P C 6 /O S C 3
P G 0
2 5
3 2
P G 7
P C 0 /T X
2 2
2 7
P C 5
P G 1
2 6
3 1
P G 6
P C 1 /R X
2 3
2 6
P C 4
P G 2
2 7
3 0
P G 5
P C 2
2 4
2 5
P C 3
P G 3
2 8
2 9
P G 4
H T 4 6 R U 2 5 /H T 4 6 C U 2 5
5 6 S S O P -A
H T 4 6 R U 2 5 /H T 4 6 C U 2 5
4 8 S S O P -A
Rev. 1.30
P B 5 /A N 5
P B 4 /A N 4
3
March 9, 2007
HT46RU25/HT46CU25
Pin Description
Pin Name
PA0~PA2
PA3/PFD
PA4
PA5/INT
PA6/SDA
PA7/SCL
PB0/AN0~
PB7/AN7
I/O
Options
Description
Pull-high
Wake-up
I/O
PA3 or PFD
I/O or I2C Bus
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by option (bit option). Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determine by
pull-high options: bit option). The PFD and INT are pin-shared with PA3
and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 cannot be used.
I/O
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and
pull-high resistor are automatically disabled.
Pull-high
I/O
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option).
Pull-high
TX and RX are pin-shared with PC0 and PC1, once the UART Bus function
I/O or UART
is used, the internal registers related to PC0 and PC1 cannot be used.
OSC3/OSC4
Software instructions determine the UART function to be used.
OSC3/OSC4 are pin shared with PC6/PC7. (depending on the OSC type
option)
PD0/PWM0
PD1/PWM1
PD2/PWM2
PD3/PWM3
PD4~PD7
I/O
Pull-high
PWM
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: byte option). The PWM0/PWM1/PWM2/
PWM3 output function are pin-shared with PD0/PD1/PD2/PD3 (depending
on the PWM options).
PF0~PF7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option).
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option).
TMR0
I
¾
Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor)
TMR1
I
¾
Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor).
TMR2
I
¾
Timer/Event Counter 2 Schmitt trigger input (without pull-high resistor).
RES
I
¾
Schmitt trigger reset input, active low
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
OSC1
OSC2
I
O
Crystal
or RC
PC0/TX
PC1/RX
PC2~PC5
PC6/OSC3
PC7/OSC4
PG0~PG7
(56-pin package only)
OSC1 and OSC2 are connected to an RC network or a crystal (by options)
for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
Rev. 1.30
4
March 9, 2007
HT46RU25/HT46CU25
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
¾
1
2
mA
¾
2.5
5
mA
¾
1.5
3
mA
¾
3
6
mA
Conditions
VDD
VDD
IDD1
IDD2
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(Crystal OSC, RC OSC)
¾
3V
5V
3V
5V
No load, fSYS=4MHz,
ADC Off, UART Off
No load, fSYS=4MHz,
ADC Off, UART On
IDD3
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz,
ADC Off, UART Off
¾
4
8
mA
IDD4
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz,
ADC Off, UART On
¾
5
10
mA
IDD5
Operating Current
(fSYS=RTC OSC)
3V
¾
0.3
0.6
mA
¾
0.6
1
mA
Standby Current
(WDT Enabled)
3V
¾
¾
5
mA
¾
¾
10
mA
Standby Current
(WDT Disabled)
3V
¾
¾
1
mA
¾
¾
2
mA
VLVR
Low Voltage Reset Voltage
¾
2.7
3
3.3
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
20
60
100
kW
10
30
50
kW
0
¾
VDD
V
ISTB1
ISTB2
5V
5V
5V
3V
No load, ADC Off,
UART Off
No load, system HALT,
UART Off
No load, system HALT,
UART Off
¾
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
Pull-high Resistance
5V
VAD
A/D Input Voltage
¾
IADC
Additional Power Consumption
if A/D Converter is Used
3V
No load
¾
0.5
1
mA
5V
No load
¾
1.5
3
mA
DNL
ADC Differential Non-Linear
¾
¾
¾
¾
±2
LSB
INL
ADC Integral Non-Linear
¾
¾
¾
±2.5
±4
LSB
Rev. 1.30
¾
5
March 9, 2007
HT46RU25/HT46CU25
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS1
System Clock
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
2.2V~5.5V
¾
32768
¾
Hz
¾
32768
¾
Hz
fSYS2
System Clock
(32768Hz Crystal OSC)
¾
tRTCOSC
RTC Frequency
¾
fTIMER
Timer I/P Frequency
(TMR0, TMR1, TMR2)
tWDTOSC
Min.
Conditions
VDD
¾
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
1
¾
¾
ms
¾
1024
¾
*tSYS
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
80
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tIIC
I2C Bus Clock Period
¾
64
¾
¾
*tSYS
Power-up or Wake-up
from HALT
Connect to external
pull-high resistor 2kW
Note: *tSYS=1/fSYS
Rev. 1.30
6
March 9, 2007
HT46RU25/HT46CU25
Functional Description
Execution Flow
Program Counter - PC
The system clock is derived from either a crystal or an
RC oscillator or an 32768Hz crystal. It is internally divided into four non-overlapping clocks. One instruction
cycle consists of four system clock cycles. Instruction
fetching and execution are pipelined in such a way that a
fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining
scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes
the value of the program counter, two cycles are required to complete the instruction.
The program counter (PC) is 14 bits wide and it controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 16384´16 addresses. After accessing a program memory word to fetch an instruction
code, the value of the PC is incremented by 1. The PC
then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a
subroutine call, an initial reset, an internal interrupt, an
external interrupt, or returning from a subroutine, the PC
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
0
1
1
0
0
UART Bus Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
0
0
I C Bus Interrupt
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Multi-function Interrupt
0
0
0
0
0
0
0
0
0
1
1
0
0
0
2
Skip
Program Counter + 2 (Within the current bank)
Loading PCL
*10
*9
*8
@7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
BP.5 #12 #11 #10
*13
*12
*11
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S13 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*13~*0: Program counter bits
#12~#0: Instruction code bits
1 3 1 2
8 7
P ro g ra m
S13~S0: Stack register bits
@7~@0: PCL bits
0
C o u n te r
B P
.5
B a n k P o in te r (B P )
Rev. 1.30
7
March 9, 2007
HT46RU25/HT46CU25
manages the program transfer by loading the address
corresponding to each instruction.
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
bank has 8192´16 bit and is selected by setting the
bank pointer (BP.5; Bank0, BP=000XXXXXB; Bank1:
BP=001XXXXXB). The JMP and CALL instructions provide only 13 bits of address to allow branching within
any 8K program memory. When doing a JMP or CALL
instruction, the user must ensure that the bank pointer
bit (BP.5) is programmed so that the desire program
memory bank is addressed. If a return from a CALL instruction or interrupt is executed, the entire 14 bit program counter is popped off the stack. Therefore,
manipulation of the BP.5 is not required for the RET or
RETI instructions.
When a control transfer takes place, an additional
dummy cycle is required.
Certain locations in the ROM are reserved for special
usage:
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
· Location 000H
Program Memory - EPROM
Location 000H is reserved for program initialization.
After a chip reset, the program always begins execution at this location.
The program memory (EPROM) is used to store the program instructions, which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 16384´16 bits format which are addressed by the
program counter and table pointer. The ROM memory is
divided into two banks (Bank0 and Bank1). Each ROM
0 0 0 H
0 0 C H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
· Location 004H
· Location 008H
E x te r n a l In te r r u p t S u b r o u tin e
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 008H.
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 0 H
U A R T B u s In te r r u p t S u b r o u tin e
0 1 4 H
I2C
0 1 8 H
B u s In te r r u p t S u b r o u tin e
M u lti- fu n c tio n In te r r u p t S u b r o u tin e
n 0 0 H
· Location 00CH
P ro g ra m
M e m o ry
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 010H
1 F 0 0 H
Location 010H is reserved for the UART Bus interrupt
service program. If the UART Bus interrupt resulting
from transmission flag or reception is completed, and
if the interrupt is enabled and the stack is not full, the
program begins execution at location 010H.
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 F F F H
1 6 b its
N o te : n ra n g e s fro m
0 to 1 F
Program Memory
Table Location
Instruction
*13~*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TBHP
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
111111
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *13~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.30
TBHP: Table pointer higher-order bits
8
March 9, 2007
HT46RU25/HT46CU25
· Location 014H
Data Memory - RAM
This area is reserved for the I2C Bus interrupt service
program. If the I2C Bus interrupt resulting from a slave
address is matched or has completed one byte of data
transfer, and if the interrupt is enabled and the stack is
not full, the program begins execution at location
014H.
The data memory (RAM) has a structure of 628´8 bits,
and is divided into two functional groups, namely; special function registers (52´8 bits) and general purpose
data memory (576´8 bits) most of which are readable/writeable, although some are read only. The general purpose data memory is divided into three banks
(Bank0~Bank2), each bank contains 192´8 bits. Bank0
can be read from and written to by directly addressing or
indirectly addressing mode using MP0, Bank1 and
Bank2 can be read from and written to only by indirect
addressing mode using MP1. The special function registers are overlapped in all banks.
· Location 018H
This area is reserved for the Multi-function interrupt
service program. If a timer interrupt results from a
Timer/Event Counter 2 overflow, or a real time clock
time-out, or Time base time-out, and if the interrupt is
enable and the stack is not full, the program begins
execution at location 018H.
· Table location
The unused space before 40H is reserved for future expansion use and reading these locations returns the result ²00H². The space before 40H is overlapping in each
bank. The general purpose data memory, addressed
from 40H to FFH (Bank0; BP=0 , Bank1; BP=1 or
Bank2; BP=2), is used for data and control information
under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement
and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and
reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers
(MP0;01H/MP1;03H). The space before 40H is overlapping in each bank.
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (page specified
by TBHP) and ²TABRDL [m]² (the last page) transfer
the contents of the lower-order byte to the specified
data memory, and the contents of the higher-order
byte to TBLH (Table Higher-order byte register) (08H).
Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are
all transferred to the lower portion of TBLH. The TBLH
is read only, the higher-order byte table pointer TBHP
(1FH) and the lower-order byte table pointer TBLP
(07H) are read/write registers, indicating the table location. Before accessing the table, the location the location has to be placed in TBHP and TBLP. All the
table related instructions require 2 cycles to complete
the operation. These areas may function as a normal
ROM depending upon the user¢s requirements.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result ²00H².
While writing, it indirectly leads to no operation. The
function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers.
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 16 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack.
Accumulator - ACC
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the RAM and capable
of operating with immediate data. The data movement
between two data memory locations must pass through
the accumulator.
If the stack is full and an enabled interrupt occurs, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is
decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the
programmer to use the structure more easily. However,
when the stack is full, a CALL subroutine instruction can
still be executed which will result in a stack overflow.
Precautions should be taken to avoid such cases which
might cause unpredictable program branching.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
Rev. 1.30
9
March 9, 2007
HT46RU25/HT46CU25
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
· Increment and Decrement (INC, DEC)
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
· Branch decision (SZ, SNZ, SIZ, SDZ)
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
1 C H
P W M 2
1 D H
P W M 3
1 E H
IN T C 1
1 F H
T B H P
2 0 H
H A D R
2 1 H
H C R
2 2 H
H S R
2 3 H
H D R
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
P F
2 9 H
P F C
2 A H
P G
2 B H
P G C
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except
for the TO and PDF flags, bits in the status register can be
altered by instructions similar to other registers. Data
written into the status register does not alter the TO or
PDF flags. Operations related to the status register, however, may yield different results from those intended. The
TO and PDF flags can only be changed by a Watchdog
Timer overflow, chip power-up, or clearing the Watchdog
Timer and executing the ²HALT² instruction.
The Z, OV, AC, and C flags reflect the status of the latest
operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status is important, and if the subroutine is likely to
corrupt the status register, the programmer should take
precautions and save it properly.
S p e c ia l P u r p o s e
D a ta M e m o ry
Interrupts - INTC0, INTC1, MFIC
The device provides one external interrupt, two internal
timer/event counter 0/1 interrupts, UART Bus interrupt,
I 2 C-Bus interrupt, the Multi-function interrupt
(timer/event counter 2 interrupt, real time clock interrupt,
time base interrupt), The interrupt control register 0
(INTC0;0BH), interrupt control register 1 (INTC1;1EH)
and Multi-Function interrupt control register (MFIC;2FH)
contains the interrupt control bits to set the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0, INTC1
and MFIC may be set to allow interrupt nesting. If the
stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the
SP is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
2 C H
2 D H
T M R 2
2 E H
T M R 2 C
2 F H
M F IC
3 0 H
U S R
3 1 H
U C R 1
3 2 H
U C R 2
3 3 H
T X R /R X R
3 4 H
3 5 H
B R G
3 F H
4 0 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(3 B a n k s : B a n k 0 , B a n k 1 , B a n k 2 )
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.30
10
March 9, 2007
HT46RU25/HT46CU25
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
The I2C Bus interrupt is initialized by setting the I2C Bus
interrupt request flag (HIF; bit 5 of the INTC1), caused
by a slave address match (HAAS=²1²) or one byte of
data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to location 014H will occur. The related
interrupt request flag (HIF) will be reset and the EMI bit
cleared to disable further interrupts.
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF;
bit 4 of the INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will be cleared
to disable other interrupts.
The Multi-Function Interrupt (MFI) is initialized by setting the interrupt request flag (MFF; bit 6 of the INTC1),
that is caused by a timer 2 overflow (T2F; bit 4 of the
MFIC), caused by a regular real time clock time-out
(RTF; bit 6 of the MFIC) or caused by a time base
time-out (TBF; bit5 of the MFIC). After the interrupt is enabled (EMFI=1), the stack is not full, and the MFF bit is
set, a subroutine call to location 018H will occur. The related interrupt request flag (MFF) is reset and the EMI bit
is cleared to disable further maskable interrupts. T2F,
TBF and RTF indicate that a related interrupt has occurred, these flags will not be cleared automatically after
reading these flags, they should be cleared by user.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of the INTC0), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 08H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is
cleared to disable further mask-able interrupts.
The Timer/Event Counter 1 and Timer/Event Counter 2
operated in the same manner, The Timer/Event Counter
1 related interrupt request flag is T1F (bit 6 of the INTC0)
and its subroutine call location is 0CH. The Timer/Event
Counter 2 related interrupt request flag are MFF(bit 6 of
the INTC1) and T2F (bit 4 of the MFIC), and its subroutine call location is 018H. The related interrupt request
flag (MFF) will be reset and the EMI bit cleared to disable further interrupts. T2F (bit 4 of the MFIC) will not be
cleared automatically, it should be cleared by user.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The UART Bus interrupt is initialized by setting the
UART Bus interrupt request flag (URIF; bit 4 of the
INTC1), caused by a Transmit enable (TXIF) or one byte
of data receive is completed (RXIF) or transmit Idle
(TIDF) is set or receive idle (RIDF) is set. When the interrupt is enabled, the stack is not full and the TXIF or
RXIF or TIDF or RIDF bit is set, a subroutine call to location 010H will occur. The related interrupt request flag
(URIF) will be reset and the EMI bit cleared to disable
further interrupts.
Rev. 1.30
11
March 9, 2007
HT46RU25/HT46CU25
Priority
Vector
External Interrupt
Interrupt Source
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
UART Bus Interrupt
4
10H
I2C Bus Interrupt
5
14H
Multi-function Interrupt
(Timer/event counter 2 / Real time
clock / Time base overflow)
6
18H
Once the interrupt request flags, composed of EIF, T0F,
T1F, URIF, HIF and MFF, are set, they will remain in the
INTC0 and INTC1 registers until the interrupts are serviced or cleared by a software instruction.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0= disable)
1
EEI
Controls the external interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
0
EURI
1
EHI
2
EMFI
Function
Control the UART interrupt (1=enable; 0=disable)
Control the I2C Bus interrupt (1=enable; 0=disable)
Control the Multi-function interrupt (1=enable; 0=disable)
3, 7
¾
4
URIF
Unused bit, read as ²0²
5
HIF
I2C Bus interrupt request flag (1=active; 0=inactive)
6
MFF
Multi-function interrupt request flag (1=active; 0=inactive)
UART request flag (1=active; 0=inactive)
INTC1 (1EH) Register
Bit No.
Label
0
ET2I
Control the Timer/Event Counter 2 interrupt (1=enable; 0=disable)
Function
1
ETBI
Control the time base interrupt (1=enable; 0=disable)
2
ERTI
Control the real time clock interrupt (1=enable; 0=disable)
3, 7
¾
4
T2F
Unused bit, read as ²0²
Timer/Event Counter 2 interrupt request flag (1=active; 0=inactive)
5
TBF
Time base interrupt request flag (1=active; 0=inactive)
6
RTF
Real time clock interrupt request flag (1=active; 0=inactive)
MFIC (2FH) Register
Rev. 1.30
12
March 9, 2007
HT46RU25/HT46CU25
Oscillator Configuration
get a frequency reference, but two external capacitors
between OSC1 and OSC2 are required (If the oscillating
frequency is less than 1MHz).
There are three oscillator circuits in the microcontroller.
The device provides three oscillator circuits for system
clocks, i.e., RC oscillator, crystal oscillator and 32768Hz
crystal oscillator, determined by options. No matter what
type of oscillator is selected, the signal is used for the
system clock.
There is another oscillator circuit designed for the real
time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected
between OSC3 and OSC4.
The RTC oscillator circuit can be controlled to oscillate
quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon
power on, and then turn it off after 2 seconds.
The HALT mode stops the system oscillator (RC and
crystal oscillator only) and ignores external signal in order to conserve power. The 32768Hz crystal oscillator
still runs at HALT mode. If the 32768Hz crystal oscillator
is selected as the system oscillator, the system oscillator
is not stopped but the instruction execution is stopped.
Since the 32768Hz oscillator is also designed for timing
purposes, the internal timing (RTC, time base, WDT)
operation still runs even if the system enters the HALT
mode.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the system enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of approximately 65ms at 5V. The WDT oscillator can be
disabled by option to conserve power. If the 32768Hz
crystal oscillator is selected as the system oscillator, the
clock source (fS) is implemented by a real time clock oscillator (RTC Oscillator)
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2 with pull-high resistor, which
can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD,
temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive
operations where an accurate oscillator frequency is
desired.
Watchdog Timer - WDT
The WDT clock is sourced from its own dedicated RC
oscillator (WDT oscillator), the instruction clock (system
clock divided by 4) or the RTC oscillator, the choice of
which is determined by configuration options. This timer
is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by
option. If the watchdog timer is disabled, all executions
related to the WDT result in no operation.
If a Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
V
4 7 0 p F
O S C 1
O S C 1
O S C 3
O S C 4
3 2 7 6 8 H z C r y s ta l/R T C
D D
fS
O S C 2
Y S
/4
O S C 2
R C
C r y s ta l O s c illa to r
O s c illa to r
O s c illa to r
System Oscillator
Note:
The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances.
S y s te m
R T C
O S C
C lo c k /4
3 2 7 6 8 H z
W D T O S C
1 2 k H z
R O M
C o d e
O p tio n
fs
D iv id e r
fs/2
8
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
C K
R
T
C K
R
T
T im e
2 1 5/fS
2 1 4/fS
2 1 3/fS
2 1 2/fS
-o
~
~
~
~
u t
2 1
2 1
2 1
2 1
6
5
R e s e t
/fS
/fS
4
/fS
3
/fS
Watchdog Timer
Rev. 1.30
13
March 9, 2007
HT46RU25/HT46CU25
Time Base
Once an internal WDT oscillator (RC oscillator with period 65ms at 5V normally) is selected, it is divided by
212~215 (by option to get the WDT time-out period). The
WDT time-out minimum period is 300ms~600ms. This
time-out period may vary with temperature, VDD and
process variations. By selection from the WDT option,
longer time-out periods can be achieved. If the WDT
time-out is selected at 215, the maximum time-out period
is divided by 215~216 which is about 2.1s~4.3s.
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from 212/fS to 215/fS selected by options. If time
base time-out occurs, the related interrupt request flags
(MFF bit 6 of the INTC1, TBF; bit 5 of the MFIC) are set.
If the interrupts (EMFI and ETBI) are enabled, and the
stack is not full, a subroutine call to location 18H occurs.
TBF will not be cleared automatically, it should be
cleared by user.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Real Time Clock - RTC
The real time clock (RTC) is operated in the same
manner as the time base that is used to supply a regular
internal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming. Writing data to RT2,
RT1 and RT0 (bits 2, 1, 0 of the RTCC; 09H) yields
various time-out periods. If the RTC time-out occurs, the
related interrupt request flags (MFF bit 6 of INTC1, RTF;
bit 6 of MFIC) are set. If the interrupts (EMFI and ERTI)
are enabled, and the stack is not full, a subroutine call to
location 18H occurs. RTF will not be cleared
automatically, it should be cleared by user.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
and only the program counter and stack pointer are reset to zero. To clear the contents of the WDT, three
methods are adopted; external reset (a low level to
RES), software instructions, or a HALT instruction. The
software instructions include CLR WDT and the other
set CLR WDT1 and CLR WDT2. Of these two types of
instruction, only one can be active depending on the
option - ²CLR WDT times selection option². If the ²CLR
WDT² is selected (i.e. CLRWDT times equal one), any
execution of the CLR WDT instruction will clear the
WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the
WDT may reset the chip due of time-out.
Bit No.
Label
0
1
2
RT0
RT1
RT2
3
¾
4
QOSC
5~7
¾
fS
Y S
/4
C o n fig u r a tio n
O p tio n
S e le c t
R T C
O s c illa to r
fS
Unused bit, read as ²0²
32768Hz OSC quick start-up
oscillating
0/1: quick/slow start
Unused bit, read as ²0²
RTCC (09H) Register
If the WDT time-out period is selected at fs/212 (option),
the WDT time-out period ranges from fs/212~fs/213, since
the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2²
instructions only clear the last two stages of the WDT.
W D T O s c illa to r
Function
8 to 1 multiplexer control
inputs to select the real clock
prescaler output
C o n fig u r a tio n O p tio n
D iv id e b y 2 1 2 ~ 2 1 5
T im e B a s e In te r r u p t
2 12/fS ~ 2 15/fS
Time Base
fS
Y S
/4
W D T O s c illa to r
R T C
O s c illa to r
C o n fig u r a tio n
O p tio n
S e le c t
D iv id e b y 2 8 ~ 2
(S e t b y R T C C
R e g is te r s )
fS
1 5
R T C In te rru p t
2 8/fS ~ 2 15/fS
R T 2 ~ R T 0
Real Time Clock
Rev. 1.30
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March 9, 2007
HT46RU25/HT46CU25
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
2 8*
0
0
1
2 9*
0
1
0
210*
11
0
1
1
2 *
1
0
0
212
13
1
0
1
2
1
1
0
214
1
15
1
1
2
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, this will be executed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
Note: ²*² not recommended to be used
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset² that resets only the program counter and SP, leaving the other
circuits in their original state. Some registers remain unaffected during other reset conditions. Most registers are
reset to the ²initial condition² when the reset conditions
are met. Examining the PDF and TO flags, the program
can distinguish between different ²chip resets².
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator is turned off but the WDT oscil-
·
·
·
·
lator keeps running (if the WDT oscillator or the real
time clock is selected).
The contents of the on-chip RAM and registers remain
unchanged.
The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the
real time clock).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
V
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
The system quits the HALT mode by way of an external
reset, an interrupt, an external falling edge signal on port
A or a WDT overflow. An external reset causes a device
initialization and the WDT overflow performs a ²warm
reset². After examining the TO and PDF flags, the cause
for a chip reset can be determined. The PDF flag is
cleared by system power-up or by executing the ²CLR
WDT² instruction and is set when executing the ²HALT²
instruction. On the other hand, the TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, and
leaves the other circuits in their original status.
0 .1 m F *
Reset Circuit
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
Note:
H A L T
W D T
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by option. Awakening from an I/O port stimulus,
the program will resume execution of the next instruction. If it awakens from an interrupt, two sequences may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. But if the interrupt is
enabled and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. If a
wake-up event occurs, it takes 1024 fSYS (system clock
period) to resume normal operation. In other words, a
dummy period is inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
Rev. 1.30
D D
W D T
T im e - o u t
R e s e t
R E S
W a rm
R e s e t
E x te rn a l
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
P o w e r - o n D e te c tio n
Reset Configuration
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
15
March 9, 2007
HT46RU25/HT46CU25
TO
PDF
tents of the lower-order byte buffer to TMR0H (TMR1H)
and TMR0L (TMR1L) registers, respectively. The
Timer/Event Counter 1/0 preload register is changed by
each writing TMR0H (TMR1H) operations. Reading
TMR0H (TMR1H) will latch the contents of the TMR0H
(TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0L (TMR1L) will read the contents of the
lower-order byte buffer. Writing TMR2 makes the starting value be placed in the timer/event counter 2 preload
register and reading TMR2 gets the contents of the
timer/event counter 2. The TMR0C (TMR1C,TMR2C) is
the Timer/Event Counter 0 (1,2) control register, which
defines the operating mode, counting enable or disable
and an active edge.
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from a HALT state or during power up.
Awaking from a HALT state or system power up, an SST
delay is added. An extra SST delay is added during
power up period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset
status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler, Divider
Cleared
WDT
Clear. After a master reset,
WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) and
T2M0, T2M1 (TMR2C) bits define the operation mode.
The event count mode is used to count external events,
which means that the clock source is from an external
(TMR0, TMR1, TMR2) pin. The timer mode functions as
a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width
measurement mode can be used to count the high or
low level duration of the external signal (TMR0, TMR1,
TMR2), and the counting is based on the internal selected clock source.
In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the
timer/event counter and ends at FFFFH. The
Timer/Event counter 2 starts counting at the current
contents in the timer/event counter and ends at FFH.
Once an overflow occurs, the counter is reloaded from
the timer/event counter preload register, and generates
an interrupt request flag (T0F; bit 5 of the INTC0, T1F;
bit 6 of the INTC0, MFF; bit 6 of the INTC1 and T2F; bit 4
of the MFIC).
Timer/Event Counter
Two Timer/Event Counters (TMR0,TMR1, TMR2) are
implemented in the microcontroller. The timer/event
counter 0 contains a 16-bit programmable count-up
counter and the clock may come from an external
source or an internal clock source. An internal clock
source comes from fSYS. The Timer/Event counter 1
contains a 16-bit programmable count-up counter and
the clock may come from an external source or an internal clock source. An internal clock source comes from
fSYS/4. The Timer/Event Counter 2 contains an 8-bit programmable count-up counter and the clock may come
from an external source or an internal clock source. An
internal clock source comes from fSYS. The external
clock input allows the user to count external events,
measure time intervals or pulse widths, or generate an
accurate time base.
In the pulse width measurement mode with the values of
the T0ON/T1ON/T2ON and T0E/T1E/T2E bits equal to
²1², after the TMR0/TMR1/TMR2 has received a transient from low to high (or high to low if the T0E/T1E/T2E
bit is ²0²), it will start counting until the TMR0/TMR1/
TMR2) returns to the original level and resets the
T0ON/T1ON/T2ON (T0ON; bit 4 of the TMR0C, T1ON;
bit 4 of the TMR1C, or T2ON; bit 4 of the TMR2C). The
measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only 1-cycle measurement can be made until the
T0ON/T1ON/T2ON is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and
issues an interrupt request, as in the other two modes,
i.e., event and timer modes.
There are eight registers related to the Timer/Event
Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C
(0EH) and the Timer/Event Counter 1; TMR1H (0FH),
TMR1L (10H), TMR1C (11H) and the Timer/Event
Counter 2; TMR2 (2CH) TMR2C (2DH). Writing TMR0L
(TMR1L) will only put the written data to an internal
lower-order byte buffer (8-bit) and writing TMR0H
(TMR1H) will transfer the specified data and the con-
Rev. 1.30
16
March 9, 2007
HT46RU25/HT46CU25
The registers states are summarized in the following table.
Register
Program
Counter
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
000H
000H
000H
000H
000H
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
00u0 00uu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM3
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
HADR
xxxx xxx-
xxxx xxx-
xxxx xxx-
xxxx xxx-
uuuu uuu-
HCR
0--0 0---
0--0 0---
0--0 0---
0--0 0---
u--u u---
HSR
100- -0-1
100- -0-1
100- -0-1
100- -0-1
uuuu uuuu
HDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
Rev. 1.30
17
March 9, 2007
HT46RU25/HT46CU25
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
Reset
(Power On)
Register
RES Reset
(HALT)
WDT Time-out
(HALT)*
PF
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PFC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PG
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PGC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
TMR2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
MFIC
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
USR
0000 1011
0000 1011
0000 1011
0000 1011
uuuu uuuu
UCR1
0000 00x0
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
UCR2
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR/RXR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu xxxx
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
P W M
(6 + 2 ) o r (7 + 1 )
C o m p a re
fS
T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it
D a ta B u s
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
L o w B y te
B u ffe r
T
T 0 M 1
T 0 M 0
T M R 0
1 6 - B it
P r e lo a d R e g is te r
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
R e lo a d
O v e r flo w
B y te
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r
P F D 0
Timer/Event Counter 0
D a ta B u s
fS
Y S
/4
f IN
L o w B y te
B u ffe r
T
T 1 M 1
T 1 M 0
T M R 1
1 6 - B it
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
R e lo a d
O v e r flo w to In te r r u p t
B y te
1 6 - B it T im e r /E v e n t C o u n te r
P F D 1
Timer/Event Counter 1
Rev. 1.30
18
March 9, 2007
HT46RU25/HT46CU25
fS
Y S
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 2 P S C 2 ~ T 2 P S C 0
(1 /1 ~ 1 /1 2 8 )
D a ta B u s
T
T 2 M 1
T 2 M 0
T M R 2
8 - B it T im e r /E v e n t
C o u n te r P r e lo a d R e g is te r
R e lo a d
T 2 E
T 2 M 1
T 2 M 0
T 2 O N
8 - B it T im e r /E v e n t
C o u n te r (T M R 2 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 2
P F D 0
P F D 1
M
U
X
1 /2
P F D
P A 3 D a ta C T R L
P F D
S o u r c e O p tio n
PFD Source Option
When the timer/event counter (reading TMR0/TMR1/
TMR2) is read, the clock is blocked to avoid errors, as
this may results in a counting error. Blocking of the clock
should be taken into account by the programmer. It is
strongly recommended to load a desired value into the
TMR0/TMR1/TMR2 register first, before turning on the
related timer/event counter, for proper operation since
the initial value of the TMR0/TMR1/TMR2 is unknown.
Due to the timer/event scheme, the programmer should
pay special attention on the instruction to enable then
disable the timer for the first time, whenever there is a
need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function
can be operated normally.
To enable the counting operation, the Timer ON bit
(T0ON; bit 4 of the TMR0C, T1ON; bit 4 of the TMR1C,
or T2ON; bit 4 of the TMR2C) should be set to 1. In the
pulse width measurement mode, the T0ON/T1ON/
T2ON is automatically cleared after the measurement
cycle is completed. But in the other two modes, the
T0ON/T1ON/T2ON can only be reset by instructions.
The overflow of the Timer/Event Counter 0/1/2 is one of
the wake-up sources, and Timer/Event Counter 0/1 can
also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. No matter what the operation mode is, writing a ²0² to ET0I, ET1I or ET2I
disables the related interrupt service. When the PFD
function is selected, executing the ²SET [PA].3² instruction will enable the PFD output and executing the ²CLR
[PA].3² instruction will disable the PFD output.
The bit0~bit2 of the TMR0C/TMR2C (T0PSC2~0/
T2PSC2~0) can be used to define the pre-scaling
stages of the internal clock sources of the timer/event
counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate
the PFD signal. The timer prescaler is also used as the
PWM counter.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues to operate until an overflow occurs.
Rev. 1.30
19
March 9, 2007
HT46RU25/HT46CU25
Bit No.
Label
Function
T0PSC0
T0PSC1
T0PSC2
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T0ON
0
1
2
5
6
7
¾
T0M0
T0M1
Enable/disable timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode, T0M1, T0M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Bit No.
0~2
Label
¾
3
T1E
4
T1ON
5
6
7
¾
T1M0
T1M1
Function
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
Defines the operating mode, T1M1, T1M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Rev. 1.30
20
March 9, 2007
HT46RU25/HT46CU25
Bit No.
Label
Function
T2PSC0
T2PSC1
T2PSC2
Defines the prescaler stages, T2PSC2, T2PSC1, T2PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
T2E
Defines the TMR2 active edge of the timer/event counter:
In Event Counter Mode (T2M1,T2M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T2M1,T2M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T2ON
0
1
2
¾
5
6
7
T2M0
T2M1
Enable/disable timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode, T2M1, T2M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR2C (2EH) Register
Input/Output Ports
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H, 18H, 28H or 2AH) instructions.
There are 48 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, PD, PF and PG,
which are mapped to the data memory of [12H], [14H],
[16H], [18H], [28H] and [2AH] respectively. All of these
I/O ports can be used for input and output operations.
For input operation, these ports are non-latching, that is,
the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H, 16H, 18H, 28H or 2AH).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PFC, PGC) to control the input/output configuration. With this control register, CMOS output or
Schmitt trigger input with or without pull-high resistor
structures can be reconfigured dynamically under software control. To function as an input, the corresponding
latch of the control register must write a ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify- write² instruction.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there¢s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
The PA3 and PA5 are pin-shared with the PFD and INT
pins respectively. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal
generated by the timer/event counter overflow signal.
The input mode always remain in its original functions.
Once the PFD option is selected, the PFD output signal
is controlled by the PA3 data register only. Writing a ²1²
to the PA3 data register will enable the PFD output function and writing ²0² will force the PA3 to remain at ²0².
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H, 19H, 29H and 2BH.
Rev. 1.30
21
March 9, 2007
HT46RU25/HT46CU25
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
W r ite D a ta R e g is te r
P A 0
P A 4
P A 6
P B 0
P C 2
P C 6
P D 0
P D 4
P F 0
P G 0
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D D
P u ll- h ig h
O p tio n
D a ta B it
Q
D
Q
C K
~ P A
, P A
/S D
/A N
~ P C
/O S
/P W
~ P D
~ P F
~ P G
2 , P A 3 /P F D
5 /IN T
A , P A 7 /S C L
0 ~ P B 7 /A N 7
5
C 3 , P C 7 /O S C 4
M 0 ~ P D 3 /P W M 3
7
7
7
S
M
M
[P A 3 , P F D ]
o r [P D 0 ,P W M 0 ]
o r [P D 1 ,P W M 1 ]
o r [P D 2 ,P W M 2 ]
o r [P D 3 ,P W M 3 ]
R e a d D a ta R e g is te r
U
U
X
E N (P F D o r
P W M 0 ~ P W M 3 )
X
S y s te m W a k e -u p
( P A o n ly )
W a k e - u p O p tio n
IN T fo r P A 5 O n ly
Input/Output Ports
V
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
D D
P u ll- h ig h
O p tio n
C o n tr o l B it
Q
S
C h ip R e s e t
P C 0 /T X
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
Q
S
M
F ro m
U A R T T X
M
R e a d D a ta R e g is te r
U
U
X
U A R T E N
X
& T X E N
PC0/TX Input/Output Ports
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
D D
P u ll- h ig h
O p tio n
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P C 1 /R X
D a ta B it
Q
D
C K
S
Q
M
R e a d D a ta R e g is te r
U
X
T o U A R T R X
PC1/RX Input/Output Ports
Rev. 1.30
22
March 9, 2007
HT46RU25/HT46CU25
of the PWM counter comes from fSYS. The PWM registers are four 8-bit registers. The waveforms of the PWM
outputs are as shown. Once the PD0/PD1/PD2/PD3 are
selected as the PWM outputs and the output function of
the PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/
PDC.2/PDC.3 =²0²), writing ²1² to PD0/PD1/PD2/PD3
data register will enable the PWM output function and
writing ²0² will force the PD0/PD1/PD2/PD3 to remain
at ²0².
The I/O functions of PA3 are shown below.
I/O
I/P
Mode (Normal)
Logical
Input
PA3
Note:
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
PA3
Timer
Data
Timer Preload
Value Register
Off
PA3
Pad
State
PFD
Frequency
X
X
0
0
Off
X
1
U
X
On
N
0
0
X
On
N
1
PFD
fTMR/[2´(m-n)]
Note:
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for Timer0, Timer1 PFD,
²256² for Timer2 PFD
²N² is preload value for timer/event counter
²fTMR² is the input clock frequency for the
timer/event counter
PD0
PD1
PD2
PD3
I/P
O/P
(Normal) (Normal)
Logical
Input
Logical
Output
I/P
(PWM)
O/P
(PWM)
Logical
Input
PWM0
PWM1
PWM2
PWM3
i<AC
DC+1
64
i³AC
DC
64
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
i<AC
DC+1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
The microcontroller provides 4 channels (6+2)/(7+1)
(depending on options) bits PWM output shared with
PD0/PD1/PD2/PD3. The PWM channels have their data
registers denoted as PWM0 (1AH), PWM1 (1BH),
PWM2 (1CH) and PWM3 (1DH). The frequency source
Rev. 1.30
Duty Cycle
Modulation cycle i
(i=0~3)
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/
PD2/PD3 is operating in output mode). The I/O functions of PD0/PD1/PD2/PD3 are as shown.
I/O
Mode
AC (0~3)
PWM
Modulation Frequency
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
23
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
March 9, 2007
HT46RU25/HT46CU25
fS
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode
A/D Converter
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is powered on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
START should remain at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
The 8 channels and 12-bit resolution A/D converter are
implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H)
and ACSR (27H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion. Define PB configuration, select the
converted analog channel, and give START bit a raising
edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared. The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
The A/D converter control register is used to control the
Rev. 1.30
24
March 9, 2007
HT46RU25/HT46CU25
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1² when the
START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified,
otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START
bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note
that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required.
Bit No.
0
1
Label
Function
Selects the A/D converter clock source
00= system clock/2
ADCS0
01= system clock/8
ADCS1
10= system clock/32
11= undefined
2~6
¾
Unused bit, read as ²0²
7
TEST
For test mode use only
ACSR (27H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
Defines the analog channel select
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption.
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
Rev. 1.30
25
March 9, 2007
HT46RU25/HT46CU25
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Analog Input Channel Selection
Note:
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11
D10
D9
D8
D7
D6
D5
D4
D0~D11 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
The following programming example illustrates how to setup and implement an A/D conversion. The method of polling
the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
mov
mov
mov
mov
EADI
a,00000001B
ACSR,a
a,00100000B
ADCR,a
:
:
:
Start_conversion:
clr
START
set
START
clr
START
Polling_EOC:
sz
EOCB
jmp
polling_EOC
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
:
:
jmp
start_conversion
Rev. 1.30
; disable ADC interrupt
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
; read conversion result high byte value from the ADRH register
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
; start next A/D conversion
26
March 9, 2007
HT46RU25/HT46CU25
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D
tA D
tA
C S
D C
c lo c k m u s t b e fS
= 3 2 tA D
= 8 0 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
d o n 't c a r e
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR has the
same effect or function with the external RES signal
which performs a chip reset. During HALT state, LVR is
disabled.
V D D
5 .5 V
V
O P R
5 .5 V
V
L V R
3 .0 V
2 .2 V
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
0 .9 V
original state for more than 1ms. If the low voltage
state does not exceed 1ms, the LVR will ignore it and
do not perform a reset function.
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
· The LVR uses the ²OR² function with the external RES
signal to perform a chip reset.
V
D D
5 .5 V
V
L V R D e te c t V o lta g e
L V R
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after a 1ms delay,
the device enters the reset mode.
Rev. 1.30
27
March 9, 2007
HT46RU25/HT46CU25
I2C Bus Serial Interface
so the slave device is working in transmit mode. When
SRW is reset to ²0², it means that the master wants to
write data to the I2C Bus, the slave device must read
data from the bus, so the slave device is working in receive mode. The RXAK bit is reset to ²0² indicates that
an acknowledge signal has been received. In the transmit mode, the transmitter checks the RXAK bit to determine the receiver which wants to receive the next data
byte, so the transmitter continues to write data to the I2C
Bus until the RXAK bit is set to ²1² and the transmitter
releases the SDA line, so that the master can send the
STOP signal to release the bus.
I2C Bus is implemented in the device. The I2C Bus is a
bidirectional two-wire lines. The data line and clock line
are implement in SDA pin and SCL pin. The SDA and
SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively.
Using the I2C Bus, the device has two ways to transfer
data. One is in slave transmit mode, the other is in slave
receive mode. There are four registers related to I2C
Bus; HADR([20H]), HCR([21H]), HSR([22H]),
HDR([23H]). The HADR register is the slave address
setting of the device, if the master sends the calling address which match, it means that this device is selected.
The HCR is I2C Bus control register which defines the
device enable or disable the I2C Bus as a transmitter or
as a receiver. The HSR is I2C Bus status register, it responds with the I2C Bus status. The HDR is input/output
data register, data to transmit or receive must be via the
HDR register.
The HADR bit7-bit1 define the device slave address. At
the beginning of a transfer, the master must select a device by sending the address of the slave device. The bit
0 is unused and is not defined. If the I2C Bus receives a
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is matched, the HAAS status bit is set and generates an I2C Bus interrupt. In the
ISR, the slave device must check the HAAS bit to determine whether the I2C Bus interrupt comes from the
slave address that has matched or completed one 8-bit
data transfer. The last bit of the 8-bit data is read/write
command bit, it responds in SRW bit. The slave will
check the SRW bit to determine whether the master
wants to transmit or receive data. The device checks the
SRW bit to know if it¢s a transmitter or a receiver.
The I2C Bus control register contains three bits. The
HEN bit defines whether to enable or disable the I2C
Bus. If the data wants to transfer via I2C Bus, this bit
must be set. The HTX bit defines whether the I2C Bus is
in transmit or receive mode. If the device is as a transmitter, this bit must be set to ²1². The TXAK defines the
transmit acknowledge signal, when the device received
8-bit data, the device sends this bit to I2C Bus at the 9th
clock. If the receiver wants to continue to receive the
next data, this bit must be reset to ²0² before receiving
data.
The I2C Bus status register contains 5 bits. The HCF bit
is reset to ²0² when one data byte is being transferred. If
one data transfer is completed, this bit is set to ²1². The
HAAS bit is set to ²1² when the address is matched, and
the I2C Bus interrupt request flag is set to ²1². If the interrupt is enabled and the stack is not full, a subroutine call
to location 10H will occur. Writing data to the I2C Bus
control register clears HAAS bit. If the address is not
matched, this bit is reset to ²0². The HBB bit is set to respond when the I2C Bus is busy. It means that a START
signal is detected. This bit is reset to ²0² when the I2C
Bus is not busy. It means that a STOP signal is detected
and the I2C Bus is free. The SRW bit defines the
read/write command bit, if the calling address is
matched. When HAAS is set to ²1², the device checks
the SRW bit to determine whether the device is working
in transmit or receive mode. When the SRW bit is set to
²1², it means that the master wants to read data from the
I2C Bus, the slave device must write data to the I2C Bus,
Rev. 1.30
Bit7~Bit1
Bit0
Slave Address
¾
²¾² means undefined
HADR (20H) Register
The HDR register is the I2C Bus input/output data register. Before transmitting data, the HDR must write the
data which needs to be transmitted. Before receiving
data, the device must dummy read data from the HDR.
Transmitting or Receiving data from the I2C Bus must be
via the HDR register.
At the beginning of the transfer of the I2C Bus, the device must initialize the bus, the following are the notes
for initializing the I2C Bus:
Note:
1: Write the I2C Bus address register (HADR) to
define its own slave address.
2: Set HEN bit of the I2C Bus control register
(HCR) bit 0 to enable the I2C Bus.
3: Set EHI bit of the interrupt control register 1
(INTC1) bit 0 to enable the I2C Bus interrupt.
28
March 9, 2007
HT46RU25/HT46CU25
Bit No.
Label
0~2
¾
3
TXAK
4
HTX
5~6
¾
7
HEN
Function
Unused bit, read as ²0²
Enable/disable transmit acknowledge
(0=acknowledge; 1=don¢t acknowledge)
Defines the transmit/receive mode
(0=receive mode; 1=transmit)
Unused bit, read as ²0²
Enable/disable I2C Bus function
(0=disable; 1=enable)
HCR (21H) Register
Bit No.
Label
Function
0
RXAK
RXAK is cleared to ²0² when the master receives an 8-bit data and acknowledgment at the 9th
clock, RXAK is set to ²1² means not acknowledged.
1
¾
2
SRW
3~4
¾
5
HBB
HBB is set to ²1² when I2C Bus is busy and HBB is cleared to ²0² means that the I2C Bus is
not busy.
6
HAAS
HAAS is set to ²1² when the calling address has matched, and I2C Bus interrupt will occur
and HCF is set.
7
HCF
HCF is cleared to ²0² when one data byte is being transferred, HCF is set to ²1² indicating
8-bit data communication has been finished.
Unused bit, read as ²0²
SRW is set to ²1² when the master wants to read data from the I2C Bus, so the slave must
transmit data to the master. SRW is cleared to ²0² when the master wants to write data to the
I2C Bus, so the slave must receive data from the master.
Unused bit, read as ²0²
HSR (22H) Register
S ta rt
W r ite S la v e
A d d re s s to H A D R
S E T H E N
D is a b le
Rev. 1.30
I2C B u s
In te rru p t= ?
E n a b le
C L R E H I
P o ll H IF to d e c id e
w h e n to g o to I2C B u s IS R
S E T E H I
W a it fo r In te r r u p t
G o to M a in P r o g r a m
G o to M a in P r o g r a m
29
March 9, 2007
HT46RU25/HT46CU25
S ta rt
N o
N o
R e a d fro m
Y e s
H A A S = 1
?
Y e s
Y e s
H T X = 1
?
H D R
R E T I
Y e s
S E T H T X
C L R H T X
C L R T X A K
W r ite to H D R
D u m m y R e a d
F ro m H D R
R E T I
R E T I
R X A K = 1
?
N o
C L R H T X
C L R T X A K
W r ite to H D R
D u m m y R e a d
fro m H D R
R E T I
N o
S R W = 1
?
R E T I
S C L
S ta rt
S R W
S la v e A d d r e s s
0
1
S D A
1
1
0
1
0
1
D a ta
S C L
1
0
0
1
A C K
0
A C K
0
1
0
S to p
0
S D A
S = S
S A =
S R =
M = S
D = D
A = A
P = S
S
ta rt (1
S la v e
S R W
la v e d
a ta (8
C K (R
to p (1
S A
b it)
A d d r e s s ( 7 b its )
b it ( 1 b it)
e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
b its )
X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
b it)
S R
M
D
A
D
A
S
S A
S R
M
D
A
D
A
P
I2C Communication Timing Diagram
Rev. 1.30
30
March 9, 2007
HT46RU25/HT46CU25
Start Signal
Acknowledge Bit
The START signal is generated only by the master device. The other device in the bus must detect the START
signal to set the I2C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high.
One of the slave device generates an acknowledge signal,
when the slave address is matched. The master device
can check this acknowledge bit to know if the slave device
accepts the calling address. If no acknowledge bit, the
master must send a STOP bit and end the communication.
When the I2C Bus status register bit 6 HAAS is high, it
means the address is matched, so the slave must check
the SRW as a transmitter (set HTX) to ²1² or as a receiver (clear HTX) to ²0².
S C L
S D A
Start Bit
S C L
Slave Address
S D A
The master must select a device for transferring the
data by sending the slave device address after the
START signal. All device in the I2C Bus will receive the
I2C Bus slave address (7 bits) to compare with its own
slave address (7 bits). If the slave address is matched,
the slave device will generate an interrupt and save the
subsequent bit (8th bit) to the SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device
also sets the status flag (HAAS), when the slave address is matched.
Stop Bit
Data Byte
The data is 8 bits and is sent after the slave device has
acknowledged the slave address. The first bit is MSB
and the 8th bit is LSB. The receiver sends the acknowledge signal (²0²) and continues to receive the next one
byte data. If the transmitter checks and there¢s no acknowledge signal, then it release the SDA line, and the
master sends a STOP signal to release the I2C Bus. The
data is stored in the HDR register. The transmitter must
write data to the HDR before transmitting data and the
receiver must read data from the HDR after receiving
data.
In interrupt subroutine, check the HAAS bit to know
whether the I2C Bus interrupt comes from a slave address that is matched or a data byte transfer is completed. When the slave address is matched, the device
must be in transmit mode or receive mode and write
data to HDR or dummy read from HDR to release the
SCL line.
S C L
SRW Bit
S D A
The SRW bit means that the master device wants to
read from or write to the I2C Bus. The slave device
check this bit to understand itself if it is a transmitter or a
receiver. The SRW bit is set to ²1² means that the master wants to read data from the I2C Bus, so the slave device must write data to a bus as a transmitter. The SRW
is cleared to ²0² means that the master wants to write
data to the I2C Bus, so the slave device must read data
from the I2C Bus as a receiver.
Rev. 1.30
S ta r t b it
S to p b it
D a ta
s ta b le
D a ta
a llo w
c h a n g e
Data Timing Diagram
Receive Acknowledge Bit
When the receiver wants to continue to receive the next
data byte, it generates an acknowledge bit (TXAK) at
the 9th clock. The transmitter checks the acknowledge
bit (RXAK) to continue to write data to the I2C Bus or
change to receive mode and a dummy reads the HDR
register to release the SDA line and the master sends
the STOP signal.
31
March 9, 2007
HT46RU25/HT46CU25
zero. Similarly, the RX pin is the UART receiver pin,
which can also be used as a general purpose I/O pin,
if the pin is not configured as a receiver, which occurs
if the RXEN bit in the UCR2 register is equal to zero.
Along with the UARTEN bit, the TXEN and RXEN bits,
if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on
the RX pin.
UART Bus Serial Interface
The HT46RU25/HT46CU25 devices contain an integrated full-duplex asynchronous serial communications
UART interface that enables communication with external devices that contain a serial interface. The UART
function has many features and can transmit and receive data serially by transferring a frame of data with
eight or nine data bits per transmission as well as being
able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own
internal interrupt which can be used to indicate when a
reception occurs or when a transmission terminates.
· UART data transfer scheme
The block diagram shows the overall data transfer
structure arrangement for the UART. The actual data
to be transmitted from the MCU is first transferred to
the TXR register by the application program. The data
will then be transferred to the Transmit Shift Register
from where it will be shifted out, LSB first, onto the TX
pin at a rate controlled by the Baud Rate Generator.
Only the TXR register is mapped onto the MCU Data
Memory, the Transmit Shift Register is not mapped
and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the
external RX pin, from where it is shifted in, LSB first, to
the Receiver Shift Register at a rate controlled by the
Baud Rate Generator. When the shift register is full,
the data will then be transferred from the shift register
to the internal RXR register, where it is buffered and
can be manipulated by the application program. Only
the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data
transmission and reception, although referred to in the
text, and in application programs, as separate TXR
and RXR registers, only exists as a single shared register in the Data Memory. This shared register known
as the TXR/RXR register is used for both data transmission and data reception.
· UART features
The integrated UART function contains the following
features:
¨
Full-duplex, asynchronous communication
¨
8 or 9 bits character length
¨
Even, odd or no parity options
¨
One or two stop bits
¨
Baud rate generator with 8-bit prescaler
¨
Parity, framing, noise and overrun error detection
¨
Support for interrupt on address detect
(last character bit=1)
¨
Separately enabled transmitter and receiver
¨
2-byte Deep Fifo Receive Data Buffer
¨
Transmit and receive interrupts
¨
Interrupts can be initialized by the following
conditions:
-
Transmitter Empty
-
Transmitter Idle
-
Receiver Full
-
Receiver Overrun
-
Address Mode Detect
· UART status and control registers
· UART external pin interfacing
There are five control registers associated with the
UART function. The USR, UCR1 and UCR2 registers
control the overall function of the UART, while the
BRG register controls the Baud rate. The actual data
to be transmitted and received on the serial interface
is managed through the TXR/RXR data registers.
To communicate with an external serial interface, the
internal UART has two external pins known as TX and
RX. The TX pin is the UART transmitter pin, which can
be used as a general purpose I/O pin if the pin is not
configured as a UART transmitter, which occurs when
the TXEN bit in the UCR2 control register is equal to
T r a n s m itte r S h ift R e g is te r
M S B
R e c e iv e r S h ift R e g is te r
L S B
T X P in
C L K
T X R
R e g is te r
M S B
R X P in
L S B
C L K
B a u d R a te
G e n e ra to r
M C U
R X R
R e g is te r
B u ffe r
D a ta B u s
UART Data Transfer Scheme
Rev. 1.30
32
March 9, 2007
HT46RU25/HT46CU25
· USR register
RXIF flag is cleared when the USR register is read
with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available.
The USR register is the status register for the UART,
which can be read by the program to determine the
present status of the UART. All flags within the USR
register are read only.
Further explanation on each of the flags is given below:
¨
¨
¨
TXIF
The TXIF flag is the transmit data register empty
flag. When this read only flag is ²0² it indicates that
the character is not transferred to the transmit shift
registers. When the flag is ²1² it indicates that the
transmit shift register has received a character from
the TXR data register. The TXIF flag is cleared by
reading the UART status register (USR) with TXIF
set and then writing to the TXR data register. Note
that when the TXEN bit is set, the TXIF flag bit will
also be set since the transmit buffer is not yet full.
TIDLE
The TIDLE flag is known as the transmission complete flag. When this read only flag is ²0² it indicates
that a transmission is in progress. This flag will be
set to ²1² when the TXIF flag is ²1² and when there
is no transmit data, or break character being transmitted. When TIDLE is ²1² the TX pin becomes idle.
The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character,
or a break is queued and ready to be sent.
RXIF
The RXIF flag is the receive register status flag.
When this read only flag is ²0² it indicates that the
RXR read data register is empty. When the flag is
²1² it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt
is generated if RIE=1 in the UCR2 register. If one or
more errors are detected in the received word, the
appropriate receive-related flags NF, FERR, and/or
PERR are set within the same clock cycle. The
b 7
P E R R
¨
RIDLE
The RIDLE flag is the receiver status flag. When
this read only flag is ²0² it indicates that the receiver
is between the initial detection of the start bit and
the completion of the stop bit. When the flag is ²1² it
indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next
start bit, the RIDLE bit is ²1² indicating that the
UART is idle.
¨
OERR
The OERR flag is the overrun error flag, which indicates when the receiver buffer has overflowed.
When this read only flag is ²0² there is no overrun error. When the flag is ²1² an overrun error occurs
which will inhibit further transfers to the RXR receive
data register. The flag is cleared by a software sequence, which is a read to the status register USR
followed by an access to the RXR data register.
¨
FERR
The FERR flag is the framing error flag. When this
read only flag is ²0² it indicates no framing error.
When the flag is ²1² it indicates that a framing error
has been detected for the current character. The
flag can also be cleared by a software sequence
which will involve a read to the USR status register
followed by an access to the RXR data register.
¨
NF
The NF flag is the noise flag. When this read only
flag is ²0² it indicates a no noise condition. When
the flag is ²1² it indicates that the UART has detected noise on the receiver input. The NF flag is set
during the same cycle as the RXIF flag but will not
be set in the case of an overrun. The NF flag can be
cleared by a software sequence which will involve a
read to the USR status register, followed by an access to the RXR data register.
b 0
N F
F E R R
O E R R
R ID L E
R X IF
T ID L E
T X IF
U S R
R e g is te r
T r a n s m it d a ta r e g is te r e m p ty
1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r
0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r
T r a n s m is s io n id le
1 : n o tr a n s m is s io n in p r o g r e s s
0 : tr a n s m is s io n in p r o g r e s s
R e c e iv e R X R r e g is te r s ta tu s
1 : R X R r e g is te r h a s a v a ila b le d a ta
0 : R X R r e g is te r is e m p ty
R e c e iv e r s ta tu s
1 : r e c e iv e r is id le
0 : d a ta b e in g r e c e iv e d
O v e rru n e rro r
1 : o v e rru n e rro r d e te c te d
0 : n o o v e rru n e rro r d e te c te d
F r a m in g e r r o r fla g
1 : fr a m in g e r r o r d e te c te d
0 : n o fr a m in g e r r o r
N o is e fla g
1 : n o is e d e te c te d
0 : n o n o is e d e te c te d
P a r ity e r r o r fla g
1 : p a r ity e r r o r d e te c te d
0 : n o p a r ity e r r o r d e te c te d
Rev. 1.30
33
March 9, 2007
HT46RU25/HT46CU25
¨
used, if the bit is equal to ²0² then only one stop bit
is used.
PERR
The PERR flag is the parity error flag. When this
read only flag is ²0² it indicates that a parity error
has not been detected. When the flag is ²1² it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode
(odd or even) is selected. The flag can also be
cleared by a software sequence which involves a
read to the USR status register, followed by an access to the RXR data register.
· UCR1 register
The UCR1 register together with the UCR2 register
are the two UART control registers that are used to set
the various options for the UART function, such as
overall on/off control, parity control, data transfer bit
length etc.
Further explanation on each of the bits is given below:
¨
TX8
This bit is only used if 9-bit data transfers are used,
in which case this bit location will store the 9th bit of
the transmitted data, known as TX8. The BNO bit is
used to determine whether data transfers are in
8-bit or 9-bit format.
¨
RX8
This bit is only used if 9-bit data transfers are used,
in which case this bit location will store the 9th bit of
the received data, known as RX8. The BNO bit is
used to determine whether data transfers are in
8-bit or 9-bit format.
¨
TXBRK
The TXBRK bit is the Transmit Break Character bit.
When this bit is ²0² there are no break characters
and the TX pin operates normally. When the bit is
²1² there are transmit break characters and the
transmitter will send logic zeros. When equal to ²1²
after the buffered data has been transmitted, the
transmitter output is held low for a minimum of a
13-bit length and until the TXBRK bit is reset.
¨
STOPS
This bit determines if one or two stop bits are to be
used. When this bit is equal to ²1² two stop bits are
b 7
U A R T E N
¨
PRT
This is the parity type selection bit. When this bit is
equal to ²1² odd parity will be selected, if the bit is
equal to ²0² then even parity will be selected.
¨
PREN
This is parity enable bit. When this bit is equal to ²1²
the parity function will be enabled, if the bit is equal
to ²0² then the parity function will be disabled.
¨
BNO
This bit is used to select the data length format,
which can have a choice of either 8-bits or 9-bits. If
this bit is equal to ²1² then a 9-bit data length will be
selected, if the bit is equal to ²0² then an 8-bit data
length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store
the 9th bit of the received and transmitted data respectively.
¨
UARTEN
The UARTEN bit is the UART enable bit. When the
bit is ²0² the UART will be disabled and the RX and
TX pins will function as General Purpose I/O pins.
When the bit is ²1² the UART will be enabled and
the TX and RX pins will function as defined by the
TXEN and RXEN control bits. When the UART is
disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition,
the baud rate counter value will be reset. When the
UART is disabled, all error and status flags will be
reset. The TXEN, RXEN, TXBRK, RXIF, OERR,
FERR, PERR, and NF bits will be cleared, while the
TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the
UARTEN bit is cleared, all pending transmissions
and receptions will be terminated and the module
will be reset as defined above. When the UART is
re-enabled it will restart in the same configuration.
b 0
B N O
P R E N
P R T
S T O P S
T X B R K
R X 8
T X 8
U C R 1 R e g is te r
T r a n s m it d a ta b it 8 ( w r ite o n ly )
R e c e iv e d a ta b it 8 ( r e a d o n ly )
T r a n s m it b r e a k c h a r a c te r
1 : tr a n s m it b r e a k c h a r a c te r s
0 : n o b re a k c h a ra c te rs
D e fin e s th e n u m b e r o f s to p b its
1 : tw o s to p b its
0 : o n e s to p b it
P a r ity ty p e b it
1 : o d d p a r ity fo r p a r ity g e n e r a to r
0 : e v e n p a r ity fo r p a r ity g e n e r a to r
P a r ity e n a b le b it
1 : p a r ity fu n c tio n e n a b le d
0 : p a r ity fu n c tio n d is a b le d
N u m b e r o f d a ta tr a n s fe r b its
1 : 9 - b it d a ta tr a n s fe r
0 : 8 - b it d a ta tr a n s fe r
U A R T e n a b le b it
1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s
0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s
Rev. 1.30
34
March 9, 2007
HT46RU25/HT46CU25
· UCR2 register
to ²0² and if the MCU is in the Power Down Mode,
any edge transitions on the RX pin will not wake-up
the device.
The UCR2 register is the second of the two UART
control registers and serves several purposes. One of
its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver
as well as enabling the various UART interrupt
sources. The register also serves to control the baud
rate speed, receiver wake-up enable and the address
detect enable.
Further explanation on each of the bits is given below:
¨
ADDEN
The ADDEN bit is the address detect mode bit.
When this bit is ²1² the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which
corresponds to RX8 if BNO=1, has a value of ²1²
then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be
generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the
value of BNO. If the address bit is ²0² an interrupt
will not be generated, and the received data will be
discarded.
¨
TEIE
This bit enables or disables the transmitter empty
interrupt. If this bit is equal to ²1² when the transmitter empty TXIF flag is set, due to a transmitter
empty condition, the UART interrupt request flag
will be set. If this bit is equal to ²0² the UART interrupt request flag will not be influenced by the condition of the TXIF flag.
¨
¨
TIIE
This bit enables or disables the transmitter idle interrupt. If this bit is equal to ²1² when the transmitter
idle TIDLE flag is set, the UART interrupt request
flag will be set. If this bit is equal to ²0² the UART interrupt request flag will not be influenced by the
condition of the TIDLE flag.
BRGH
The BRGH bit selects the high or low speed mode
of the Baud Rate Generator. This bit, together with
the value placed in the BRG register, controls the
Baud Rate of the UART. If this bit is equal to ²1² the
high speed mode is selected. If the bit is equal to ²0²
the low speed mode is selected.
¨
¨
RIE
This bit enables or disables the receiver interrupt. If
this bit is equal to ²1² when the receiver overrun
OERR flag or receive data available RXIF flag is
set, the UART interrupt request flag will be set. If
this bit is equal to ²0² the UART interrupt will not be
influenced by the condition of the OERR or RXIF
flags.
¨
WAKE
This bit enables or disables the receiver wake-up
function. If this bit is equal to ²1² and if the MCU is in
the Power Down Mode, a low going edge on the RX
input pin will wake-up the device. If this bit is equal
RXEN
The RXEN bit is the Receiver Enable Bit. When this
bit is equal to ²0² the receiver will be disabled with
any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX
pin can be used as a general purpose I/O pin. If the
RXEN bit is equal to ²1² the receiver will be enabled
and if the UARTEN bit is equal to ²1² the RX pin will
be controlled by the UART. Clearing the RXEN bit
during a transmission will cause the data reception
to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose
I/O pin.
b 7
T X E N
b 0
R X E N
B R G H
A D D E N
W A K E
R IE
T IIE
T E IE
U C R 2 R e g is te r
T r a n s m itte r e m p ty in te r r u p t e n a b le
1 : T X IF in te r r u p t r e q u e s t e n a b le
0 : T X IF in te r r u p t r e q u e s t d is a b le
T r a n s m itte r id le in te r r u p t e n a b le
1 : T ID L E in te r r u p t r e q u e s t e n a b le
0 : T ID L E in te r r u p t r e q u e s t d is a b le
R e c e iv e r in te r r u p t e n a b le
1 : R X IF in te r r u p t r e q u e s t e n a b le
0 : R X IF in te r r u p t r e q u e s t d is a b le
D e fin e s th e R X w a k e u p e n a b le
1 : R X w a k e u p e n a b le ( fa llin g e d g e )
0 : R X w a k e u p d is a b le
A d d re s s d e te c t m o d e
1 : e n a b le
0 : d is a b le
H ig h b a u d r a te s e le c t b it
1 : h ig h s p e e d
0 : lo w s p e e d
R e c e iv e r e n a b le b it
1 : r e c e iv e r e n a b le
0 : r e c e iv e r d is a b le
T r a n s m itte r e n a b le b it
1 : tr a n s m itte r e n a b le
0 : tr a n s m itte r d is a b le
Rev. 1.30
35
March 9, 2007
HT46RU25/HT46CU25
¨
TXEN
The TXEN bit is the Transmitter Enable Bit. When
this bit is equal to ²0² the transmitter will be disabled
with any pending transmissions being aborted. In
addition the buffer will be reset. In this situation the
TX pin can be used as a general purpose I/O pin. If
the TXEN bit is equal to ²1² the transmitter will be
enabled and if the UARTEN bit is equal to ²1² the
TX pin will be controlled by the UART. Clearing the
TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter.
If this occurs, the TX pin can be used as a general
purpose I/O pin.
By programming the BRGH bit which allows selection
of the related formula and programming the required
value in the BRG register, the required baud rate can
be setup. Note that because the actual baud rate is
determined using a discrete value, N, placed in the
BRG register, there will be an error associated between the actual and requested value. The following
example shows how the BRG register value N and the
error value can be calculated.
Calculating the register and error values
For a clock frequency of 8MHz, and with BRGH set to
²0² determine the BRG register value N, the actual
baud rate and the error value for a desired baud rate
of 9600.
From the above table the desired baud rate BR
fSYS
=
[64 (N+1)]
fSYS
Re-arranging this equation gives N =
-1
(BRx64)
8000000
- 1 = 12.0208
Giving a value for N =
(9600x 64)
· Baud rate generator
To setup the speed of the serial data communication,
the UART function contains its own dedicated baud
rate generator. The baud rate is controlled by its own
internal free running 8-bit timer, the period of which is
determined by two factors. The first of these is the
value placed in the BRG register and the second is the
value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator
is to be used in a high speed mode or low speed
mode, which in turn determines the formula that is
used to calculate the baud rate. The value in the BRG
register determines the division factor, N, which is
used in the following baud rate calculation formula.
Note that N is the decimal value placed in the BRG
register and has a range of between 0 and 255.
UCR2 BRGH Bit
Baud Rate
0
1
fSYS
[64 (N+1)]
fSYS
[16 (N+1)]
To obtain the closest value, a decimal value of 12
should be placed into the BRG register. This gives an
actual or calculated baud rate value of
8000000
BR =
= 9615
[64(12+1)]
Therefore the error is equal to = 0.16%
The following tables show actual values of baud rate and error values for the two values of BRGH.
Baud
Rate
K/BPS
Baud Rates for BRGH=0
fSYS=8MHz
fSYS=7.159MHz
fSYS=4MHz
fSYS=3.579545MHz
BRG
Kbaud
Error
BRG
Kbaud
Error
BRG
Kbaud
Error
BRG
Kbaud
Error
0.3
¾
¾
¾
¾
¾
¾
207
0.300
0.00
185
0.300
0.00
1.2
103
1.202
0.16
92
1.203
0.23
51
1.202
0.16
46
1.19
-0.83
2.4
51
2.404
0.16
46
2.38
-0.83
25
2.404
0.16
22
2.432
1.32
4.8
25
4.807
0.16
22
4.863
1.32
12
4.808
0.16
11
4.661
-2.9
9.6
12
9.615
0.16
11
9.322
-2.9
6
8.929
-6.99
5
9.321
-2.9
19.2
6
17.857
-6.99
5
18.64
-2.9
2
20.83
8.51
2
18.643
-2.9
38.4
2
41.667
8.51
2
37.29
-2.9
1
¾
¾
1
¾
¾
57.6
1
62.5
8.51
1
55.93
-2.9
0
62.5
8.51
0
55.93
-2.9
115.2
0
125
8.51
0
111.86
-2.9
¾
¾
¾
¾
¾
¾
Baud Rates and Error Values for BRGH = 0
Rev. 1.30
36
March 9, 2007
HT46RU25/HT46CU25
Baud
Rate
K/BPS
Baud Rates for BRGH=1
fSYS=8MHz
fSYS=7.159MHz
fSYS=4MHz
fSYS=3.579545MHz
BRG
Kbaud
Error
BRG
Kbaud
Error
BRG
Kbaud
Error
BRG
Kbaud
Error
0.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
1.2
¾
¾
¾
¾
¾
¾
207
1.202
0.16
185
1.203
0.23
2.4
207
2.404
0.16
185
2.405
0.23
103
2.404
0.16
92
2.406
0.23
4.8
103
4.808
0.16
92
4.811
0.23
51
4.808
0.16
46
4.76
-0.83
9.6
51
9.615
0.16
46
9.520
-0.832
25
9.615
0.16
22
9.727
1.32
19.2
25
19.231
0.16
22
19.454
1.32
12
19.231
0.16
11
18.643
-2.9
38.4
12
38.462
0.16
11
37.287
-2.9
6
35.714
-6.99
5
37.286
-2.9
57.6
8
55.556
-3.55
7
55.93
-2.9
3
62.5
8.51
3
55.930
-2.9
115.2
3
125
8.51
3
111.86
-2.9
1
125
8.51
1
111.86
-2.9
250
1
250
0
¾
¾
¾
0
250
0
¾
¾
¾
Baud Rates and Error Values for BRGH = 1
· Setting up and controlling the UART
¨
¨
Clearing the UARTEN bit will disable the TX and RX
pins and allow these two pins to be used as normal
I/O pins. When the UART function is disabled the
buffer will be reset to an empty condition, at the
same time discarding any remaining residual data.
Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF,
OERR, FERR, PERR and NF being cleared while
bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG
registers will remain unaffected. If the UARTEN bit
in the UCR1 register is cleared while the UART is
active, then all pending transmissions and receptions will be immediately suspended and the UART
will be reset to a condition as defined above. If the
UART is then subsequently re-enabled, it will restart
again in the same configuration.
Introduction
For data transfer, the UART function utilizes a
non-return-to-zero, more commonly known as
NRZ, format. This is composed of one start bit, eight
or nine data bits, and one or two stop bits. Parity is
supported by the UART hardware, and can be
setup to be even, odd or no parity. For the most
common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as
the default setting, which is the setting at power-on.
The number of data bits and stop bits, along with the
parity, are setup by programming the corresponding
BNO, PRT, PREN, and STOPS bits in the UCR1
register. The baud rate used to transmit and receive
data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received
LSB first. Although the UART¢s transmitter and receiver are functionally independent, they both use
the same data format and baud rate. In all cases
stop bits will be used for data transmission.
¨
Enabling/disabling the UART
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1
register. As the UART transmit and receive pins, TX
and RX respectively, are pin-shared with normal I/O
pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two
pins. If the UARTEN, TXEN and RXEN bits are set,
then these two I/O pins will be setup as a TX output
pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being
transmitted on the TX pin then it will default to a
logic high value.
Rev. 1.30
37
Data, parity and stop bit selection
The format of the data to be transferred, is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UCR1 register.
The BNO bit controls the number of data bits which
can be set to either 8 or 9, the PRT bit controls the
choice of odd or even parity, the PREN bit controls
the parity on/off function and the STOPS bit decides
whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an
address character. The number of stop bits, which
can be either one or two, is independent of the data
length.
March 9, 2007
HT46RU25/HT46CU25
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
¨
Example of 8-bit Data Formats
1
8
0
0
1
1
7
0
1
1
7
1
0
1
1
1
Example of 9-bit Data Formats
1
9
0
0
1
1
8
0
1
1
1
8
11
0
1
Transmitting data
When the UART is transmitting data, the data is
shifted on the TX pin from the shift register, with the
least significant bit first. In the transmit mode, the
TXR register forms a buffer between the internal
bus and the transmitter shift register. It should be
noted that if 9-bit data format has been selected,
then the MSB will be taken from the TX8 bit in the
UCR1 register. The steps to initiate a data transfer
can be summarized as follows:
-
Make the correct selection of the BNO, PRT,
PREN and STOPS bits to define the required
word length, parity type and number of stop bits.
-
Setup the BRG register to select the desired baud
rate.
-
Set the TXEN bit to ensure that the TX pin is used
as a UART transmitter pin and not as an I/O pin.
-
Access the USR register and write the data that is
to be transmitted into the TXR register. Note that
this step will clear the TXIF bit.
-
This sequence of events can now be repeated to
send additional data.
Transmitter Receiver Data Format
The following diagram shows the transmit and receive
waveforms for both 8-bit and 9-bit data formats.
· UART transmitter
Data word lengths of either 8 or 9 bits, can be selected
by programming the BNO bit in the UCR1 register.
When BNO bit is set, the word length will be set to 9
bits. In this case the 9th bit, which is the MSB, needs
to be stored in the TX8 bit in the UCR1 register. At the
transmitter core lies the Transmitter Shift Register,
more commonly known as the TSR, whose data is obtained from the transmit data register, which is known
as the TXR register. The data to be transmitted is
loaded into this TXR register by the application program. The TSR register is not written to with new data
until the stop bit from the previous transmission has
been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data
from the TXR register, if it is available. It should be
noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area
and as such is not available to the application program
for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN
bit is set, but the data will not be transmitted until the
TXR register has been loaded with data and the baud
rate generator has defined a shift clock source. However, the transmission can also be initiated by first
loading data into the TXR register, after which the
TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a
transfer to the TXR register will result in an immediate
transfer to the TSR. If during a transmission the TXEN
bit is cleared, the transmission will immediately cease
and the transmitter will be reset. The TX output pin will
then return to having a normal general purpose I/O pin
function.
It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the
following software sequence:
1. A USR register access
2. A TXR register write execution
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is
empty and that other data can now be written into
the TXR register without overwriting the previous
data. If the TEIE bit is set then the TXIF flag will generate an interrupt.
During a data transmission, a write instruction to the
TXR register will place the data into the TXR register, which will be copied to the shift register at the
end of the present transmission. When there is no
data transmission in progress, a write instruction to
the TXR register will place the data directly into the
shift register, resulting in the commencement of
data transmission, and the TXIF bit being immediately set. When a frame transmission is complete,
which happens after stop bits are sent or after the
break frame, the TIDLE bit will be set. To clear the
TIDLE bit the following software sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared
by the same software sequence.
P a r ity B it
S ta r t B it
B it 0
B it 1
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
S to p B it
N e x t
S ta rt
B it
8 -B it D a ta F o r m a t
P a r ity B it
S ta r t B it
B it 0
B it 1
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
B it 8
S to p B it
N e x t
S ta rt
B it
9 -B it D a ta F o r m a t
Rev. 1.30
38
March 9, 2007
HT46RU25/HT46CU25
¨
-
Transmit break
If the TXBRK bit is set then break characters will be
sent on the next transmission. Break character
transmission consists of a start bit, followed by 13´
N ¢0¢ bits and stop bits, where N=1, 2, etc. If a break
character is to be transmitted then the TXBRK bit
must be first set by the application program, then
cleared to generate the stop bits. Transmitting a
break character will not generate a transmit interrupt. Note that a break condition length is at least 13
bits long. If the TXBRK bit is continually kept at a
logic high level then the transmitter circuitry will
transmit continuous break characters. After the application program has cleared the TXBRK bit, the
transmitter will finish transmitting the last break
character and subsequently send out one or two
stop bits. The automatic logic highs at the end of the
last break character will ensure that the start bit of
the next frame is recognized.
At this point the receiver will be enabled which will
begin to look for a start bit.
When a character is received the following sequence of events will occur:
Introduction
The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length
will be set to 9 bits with the MSB being stored in the
RX8 bit of the UCR1 register. At the receiver core lies
the Receive Serial Shift Register, commonly known
as the RSR. The data which is received on the RX
external input pin, is sent to the data recovery block.
The data recovery block operating speed is 16 times
that of the baud rate, while the main receive serial
shifter operates at the baud rate. After the RX pin is
sampled for the stop bit, the received data in RSR is
transferred to the receive data register, if the register
is empty. The data which is received on the external
RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been
placed onto the RX pin. It should be noted that the
RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as
such is not available to the application program for
direct read/write operations.
¨
Receiving data
When the UART receiver is receiving data, the data
is serially shifted in on the external RX input pin,
LSB first. In the read mode, the RXR register forms
a buffer between the internal bus and the receiver
shift register. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO while a third byte can continue to be received.
Note that the application program must ensure that
the data is read from RXR before the third byte has
been completely shifted in, otherwise this third byte
will be discarded and an overrun error OERR will be
subsequently indicated. The steps to initiate a data
transfer can be summarized as follows:
-
Make the correct selection of BNO, PRT, PREN
and STOPS bits to define the word length, parity
type and number of stop bits.
-
Setup the BRG register to select the desired baud
rate.
Rev. 1.30
-
The RXIF bit in the USR register will be set when
RXR register has data available, at least one
more character can be read.
-
When the contents of the shift register have been
transferred to the RXR register, then if the RIE bit
is set, an interrupt will be generated.
-
If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following
software sequence:
1. A USR register access
2. An RXR register read execution
· UART receiver
¨
Set the RXEN bit to ensure that the RX pin is used
as a UART receiver pin and not as an I/O pin.
¨
¨
39
Receive break
Any break character received by the UART will be
managed as a framing error. The receiver will count
and expect a certain number of bit times as specified by the values programmed into the BNO and
STOPS bits. If the break is much longer than 13 bit
times, the reception will be considered as complete
after the number of bit times specified by BNO and
STOPS. The RXIF bit is set, FERR is set, zeros are
loaded into the receive data register, interrupts are
generated if appropriate and the RIDLE bit is set. If
a long break signal has been detected and the receiver has received a start bit, the data bits and the
invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking
for the next start bit. The receiver will not make the
assumption that the break condition on the line is
the next start bit. A break is regarded as a character
that contains only zeros with the FERR flag set. The
break character will be loaded into the buffer and no
further data will be received until stop bits are received. It should be noted that the RIDLE read only
flag will go high when the stop bits have not yet
been received. The reception of a break character
on the UART registers will result in the following:
-
The framing error flag, FERR, will be set.
-
The receive data register, RXR, will be cleared.
-
The OERR, NF, PERR, RIDLE or RXIF flags will
possibly be set.
Idle status
When the receiver is reading data, which means it
will be in between the detection of a start bit and the
reading of a stop bit, the receiver status flag in the
USR register, otherwise known as the RIDLE flag,
will have a zero value. In between the reception of a
stop bit and the detection of the next start bit, the
RIDLE flag will have a high value, which indicates
the receiver is in an idle condition.
March 9, 2007
HT46RU25/HT46CU25
¨
-
Receiver interrupt
The read only receive interrupt flag RXIF in the USR
register is set by an edge generated by the receiver.
An interrupt is generated if RIE=1, when a word is
transferred from the Receive Shift Register, RSR, to
the Receive Data Register, RXR. An overrun error
can also generate an interrupt if RIE=1.
No interrupt will be generated. However this bit
rises at the same time as the RXIF bit which itself
generates an interrupt.
Note that the NF flag is reset by a USR register read
operation followed by an RXR register read
operation.
¨
Framing Error - FERR Flag
The read only framing error flag, FERR, in the USR
register, is set if a zero is detected instead of stop
bits. If two stop bits are selected, both stop bits must
be high, otherwise the FERR flag will be set. The
FERR flag is buffered along with the received data
and is cleared on any reset.
¨
Parity Error - PERR Flag
The read only parity error flag, PERR, in the USR
register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity
is enabled, PREN = 1, and if the parity type, odd or
even is selected. The read only PERR flag is buffered along with the received data bytes. It is
cleared on any reset. It should be noted that the
FERR and PERR flags are buffered along with the
corresponding word and should be read before
reading the data word.
· Managing receiver errors
Several types of reception errors can occur within the
UART module, the following section describes the
various types and how they are managed by the
UART.
¨
Overrun Error - OERR flag
The RXR register is composed of a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO register, while a third byte can continue to be
received. Before this third byte has been entirely
shifted in, the data should be read from the RXR
register. If this is not done, the overrun error flag
OERR will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
-
The OERR flag in the USR register will be set.
-
The RXR contents will not be lost.
-
The shift register will be overwritten.
· UART interrupt scheme
The UART internal function possesses its own internal interrupt and independent interrupt vector. Several
individual UART conditions can generate an internal
UART interrupt. These conditions are, a transmitter
data register empty, transmitter idle, receiver data
available, receiver overrun, address detect and an RX
pin wake-up. When any of these conditions are created, if the UART interrupt is enabled and the stack is
not full, the program will jump to the UART interrupt
vector where it can be serviced before returning to the
main program. Four of these conditions, have a corresponding USR register flag, which will generate a
UART interrupt if its associated interrupt enable flag in
-
An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the
USR register followed by a read to the RXR register.
¨
Noise Error - NF Flag
Over-sampling is used for data recovery to identify
valid incoming data and noise. If noise is detected
within a frame the following will occur:
-
The read only noise flag, NF, in the USR register
will be set on the rising edge of the RXIF bit.
-
Data will be transferred from the Shift register to
the RXR register.
U S R
R e g is te r
U C R 2 R e g is te r
0
T E IE
T r a n s m itte r E m p ty
F la g T X IF
1
IN T C 1
R e g is te r
U A R T In te rru p t
R e q u e s t F la g
U R F
0
T IIE
T r a n s m itte r Id le
F la g T ID L E
1
R e c e iv e r O v e r r u n
F la g O E R R
R e c e iv e r D a ta
A v a ila b le R X IF
E M I
0
R IE
O R
E U R I
IN T C 0
R e g is te r
1
0
A D D E N
1
0
1
R X P in
W a k e -u p
0
W A K E
R X 7 if B N O = 0
R X 8 if B N O = 1
1
U C R 2 R e g is te r
UART Interrupt Scheme
Rev. 1.30
40
March 9, 2007
HT46RU25/HT46CU25
the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable bits,
while the two receiver interrupt conditions have a
shared enable bit. These enable bits can be used to
mask out individual UART interrupt sources.
The address detect condition, which is also a UART
interrupt source, does not have an associated flag,
but will generate a UART interrupt when an address
detect condition occurs if its function is enabled by
setting the ADDEN bit in the UCR2 register. An RX pin
wake-up, which is also a UART interrupt source, does
not have an associated flag, but will generate a UART
interrupt if the microcontroller is woken up by a low going edge on the RX pin, if the WAKE and RIE bits in
the UCR2 register are set. Note that in the event of an
RX wake-up interrupt occurring, there will be a delay
of 1024 system clock cycles before the system resumes normal operation.
Note that the USR register flags are read only and
cannot be cleared or set by the application program,
neither will they be cleared when the program jumps
to the corresponding interrupt servicing routine, as is
the case for some of the other interrupts. The flags will
be cleared automatically when certain actions are
taken by the UART, the details of which are given in
the UART register section. The overall UART interrupt
can be disabled or enabled by the EURI bit in the
INTC1 interrupt control register to prevent a UART interrupt from occurring.
ADDEN
0
0
1
Ö
1
Ö
0
X
1
Ö
ADDEN Bit Function
· UART operation in power down mode
When the MCU is in the Power Down Mode the UART
will cease to function. When the device enters the
Power Down Mode, all clock sources to the module
are shutdown. If the MCU enters the Power Down
Mode while a transmission is still in progress, then the
transmission will be terminated and the external TX
transmit pin will be forced to a logic high level. In a
similar way, if the MCU enters the Power Down Mode
while receiving data, then the reception of data will
likewise be terminated. When the MCU enters the
Power Down Mode, note that the USR, UCR1, UCR2,
transmit and receive registers, as well as the BRG
register will not be affected.
The UART function contains a receiver RX pin
wake-up function, which is enabled or disabled by the
WAKE bit in the UCR2 register. If this bit, along with
the UART enable bit, UARTEN, the receiver enable
bit, RXEN and the receiver interrupt bit, RIE, are all
set before the MCU enters the Power Down Mode,
then a falling edge on the RX pin will wake-up the
MCU from the Power Down Mode. Note that as it
takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any
data received during this time on the RX pin will be ignored.
For a UART wake-up interrupt to occur, in addition to
the bits for the wake-up being set, the global interrupt
enable bit, EMI, and the UART interrupt enable bit,
EURI must also be set. If these two bits are not set
then only a wake up event will occur and no interrupt
will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal
microcontroller resumes, the UART interrupt will not
be generated until after this time has elapsed.
· Address detect mode
Setting the Address Detect Mode bit, ADDEN, in the
UCR2 register, enables this special mode. If this bit is
enabled then an additional qualifier will be placed on
the generation of a Receiver Data Available interrupt,
which is requested by the RXIF flag. If the ADDEN bit
is enabled, then when data is available, an interrupt
will only be generated, if the highest received bit has a
high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt
generation. This highest address bit is the 9th bit if
BNO=1 or the 8th bit if BNO=0. If this bit is high, then
the received word will be defined as an address rather
than data. A Data Available interrupt will be generated
every time the last bit of the received word is set. If the
ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF
flag is set, irrespective of the data last bit status. The
address detect mode and parity enable are mutually
exclusive functions. Therefore if the address detect
mode is enabled, then to ensure correct operation, the
parity function should be disabled by resetting the parity enable bit to zero.
Rev. 1.30
Bit 9 if BNO=1, UART Interrupt
Bit 8 if BNO=0
Generated
41
March 9, 2007
HT46RU25/HT46CU25
Options
The following shows the kinds of options in the device. ALL the options must be defined to ensure a proper functioning
system.
Options
OSC type selection.
This option is to determine whether an RC or crystal or 32768Hz crystal oscillator is chosen as a system clock.
If 32768Hz crystal oscillator is chosen as system clock or as fS, the PC6 and PC7 will be used as oscillator pins.
WDT, RTC and Time Base clock source selection.
There are three types of selections: system clock/4 or RTC OSC or WDT OSC.
WDT enable/disable selection.
WDT can be enabled or disabled by option.
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² instruction can clear
the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² instructions have been executed,
then WDT can be cleared.
Time Base time-out period selection.
The Time Base time-out period ranges from 212/fS to 215/fS. fS means the clock source selected by options.
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the
device from a HALT by a falling edge. (Bit option)
Pull-high selection.
This option is to determine whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA and
PB are bit option; PC, PD, PF and PG are port option.
PFD selection.
PA3: level output or PFD0 (Timer0) output or PFD1 (Timer1)
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
PD2: level output or PWM2 output
PD3: level output or PWM3 output
WDT time-out period selection.
212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS.
I2C Bus function: enable or disable
LVR selection.
LVR has enable or disable options
Rev. 1.30
42
March 9, 2007
HT46RU25/HT46CU25
Application Circuits
V
D D
0 .0 1 m F *
V D D
1 0 0 k W
P A 0 ~ P A 2
P A 3 /P F D
0 .1 m F
R E S
1 0 k W
P A 4
P A 5 /IN T
0 .1 m F *
V S S
P A 6 /S D A
P A 7 /S C L
~
P B 0 /A N 0
O S C
C ir c u it
O S C 1
O S C 2
S e e R ig h t S id e
3 2 7 6 8 H z
P B 7 /A N 7
P C 0 /T X
P C 1 /R X
P C 2 ~ P C 5
V
P C 6 /O S C 3
O S C 3
4 7 0 p F
P C 7 /O S C 4
R
~
P D 0 /P W M 0
O S C 4
O S C
P D 3 /P W M 3
C 1
P D 4 ~ P D 7
T M R 0
P F 0 ~ P F 7
T M R 1
P G 0 ~ P G 7
T M R 2
D D
C 2
H T 4 6 R U 2 5 /H T 4 6 C U 2 5
O S C 1
fS
Y S
/4
R C S y s te m O s c illa to r
3 0 k W < R O S C < 7 5 0 k W
O S C 2
O S C 1
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
O S C C ir c u it
The following table shows the C1 and C2 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
4MHz Crystal
0pF
4MHz Resonator
10pF
3.58MHz Crystal
0pF
3.58MHz Resonator
25pF
2MHz Crystal & Resonator
25pF
1MHz Crystal
35pF
480kHz Resonator
300pF
455kHz Resonator
300pF
429kHz Resonator
300pF
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.30
43
March 9, 2007
HT46RU25/HT46CU25
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.30
44
March 9, 2007
HT46RU25/HT46CU25
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.30
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
45
March 9, 2007
HT46RU25/HT46CU25
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
46
March 9, 2007
HT46RU25/HT46CU25
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
47
March 9, 2007
HT46RU25/HT46CU25
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
48
March 9, 2007
HT46RU25/HT46CU25
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
49
March 9, 2007
HT46RU25/HT46CU25
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
50
March 9, 2007
HT46RU25/HT46CU25
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
51
March 9, 2007
HT46RU25/HT46CU25
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
52
March 9, 2007
HT46RU25/HT46CU25
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
53
March 9, 2007
HT46RU25/HT46CU25
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
54
March 9, 2007
HT46RU25/HT46CU25
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
55
March 9, 2007
HT46RU25/HT46CU25
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
56
March 9, 2007
HT46RU25/HT46CU25
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
57
March 9, 2007
HT46RU25/HT46CU25
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
58
March 9, 2007
HT46RU25/HT46CU25
Package Information
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
F
E
Symbol
Rev. 1.30
a
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
59
March 9, 2007
HT46RU25/HT46CU25
56-pin SSOP (300mil) Outline Dimensions
2 9
5 6
B
A
2 8
1
C
C '
G
H
D
Symbol
Rev. 1.30
a
F
E
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
720
¾
730
D
89
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
60
March 9, 2007
HT46RU25/HT46CU25
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.30
61
March 9, 2007
HT46RU25/HT46CU25
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32±0.3
P
Cavity Pitch
16±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
12±0.1
B0
Cavity Width
16.2±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.30
0.35±0.05
25.5
62
March 9, 2007
HT46RU25/HT46CU25
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holmate.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
63
March 9, 2007