HY62UF16403A Series 256Kx16bit full CMOS SRAM Document Title 256K x16 bit 2.7 ~ 3.3V Super Low Power FCMOS Slow SRAM Revision History Revision No History Draft Date Remark 09 Marking Information add tBLZ / tOLZ value is changed Output Load is redefined Isb, Isb1, Vdr, Iccdr are redefined Dec.18.2000 Final 10 Changed Logo Mar.23.2001 Final 11 Changed Isb1 values Jun.07.2001 Final This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.11 / Jun.01 Hynix Semiconductor HY62UF16403A Series DESCRIPTION FEATURES The HY62UF16403A is a high speed, super low power and 4Mbit full CMOS SRAM organized as 256K words by 16bits. The HY62UF16403A uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup -. 1.2V(min) data retention • Standard pin configuration -. 48-ball uBGA Voltage (V) Product No. Speed (ns) Operation Current/Icc(mA) HY62UF16403A 2.7~3.3 55/70/85 HY62UF16403A-I 2.7~3.3 55/70/85 Note 1. Blank : Commercial, I : Industrial 2. Current value is max. 5 5 PIN CONNECTION H /OE A0 A1 A2 NC /UB A3 A4 /CS IO1 IO10 IO11 A5 A6 IO2 IO3 Vss IO12 A17 A7 IO4 Vcc Vcc IO13 NC A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 IO16 NC A12 A13 /WE IO8 NC A9 A10 A11 A8 NC uBGA ROW DECODER A0 MEMORY ARRAY 256K x 16 A17 I/O1 I/O8 DATA I/O BUFFER G IO9 6 WRITE DRIVER F 5 BLOCK DECODER E 4 PRE DECODER D 3 ADD INPUT BUFFER C /LB 0~70 -40~85(I) BLOCK DIAGRAM COLUMN DECODER B 2 Temperature (°C) SENSE AMP A 1 Standby Current(uA) LL SL 15 6 15 6 I/O9 I/O16 /CS /OE /LB /UB /WE PIN DESCRIPTION Pin Name /CS /WE /OE /LB /UB Rev.11 / Jun.01 Pin Function Chip Select Write Enable Output Enable Lower Byte Control (I/O1~I/O8) Upper Byte Control (I/O9~I/O16) Pin Name I/O1~I/O16 A0~A17 Vcc Vss NC Pin Function Data Inputs/Outputs Address Inputs Power (2.7~3.3V) Ground No Connection 2 HY62UF16403A Series ORDERING INFORMATION Part No. HY62UF16403ALLM HY62UF16403ASLM HY62UF16403ALLM-I HY62UF16403ASLM-I Speed 55/70/85 55/70/85 55/70/85 55/70/85 Power LL-part SL-part LL-part SL-part Temp. I I Package uBGA uBGA uBGA uBGA Note 1. Blank : Commercial, I : Industrial ABSOLUTE MAXIMUM RATINGS (1) Symbol VIN, VOUT Vcc TA Parameter Input/Output Voltage Power Supply Operating Temperature TSTG PD TSOLDER Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to 3.6 -0.3 to 4.6 0 to 70 -40 to 85 -55 to 150 1.0 260 • 10 Unit V V °C °C °C W °C•sec Remark HY62UF16403A HY62UF16403A-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS /WE /OE /LB /UB H X X X X X L H H L H L L L X X H L X L H L L H L X H X L H L L H L L Mode I/O Pin I/O1~I/O8 I/O9~I/O16 Power Deselected High-Z High-Z Standby Output Disabled High-Z High-Z Active DOUT High-Z DOUT DIN High-Z DIN High-Z DOUT DOUT High-Z DIN DIN Read Write Active Active Note: 1. H=VIH, L=VIL, X=don't care (VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16. Rev.11 / Jun.01 2 HY62UF16403A Series RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.31. Typ 3.0 0 - Max. 3.3 0 Vcc+0.3 0.6 Unit V V V V Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns 2. Undershoot is sampled, not 100% tested. DC ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C / -40°C to 85°C (I) Sym Parameter ILI Input Leakage Current ILO Output Leakage Current Icc Operating Power Supply Current ICC1 ISB Average Operating Current Standby Current (TTL Input) ISB1 Standby Current (CMOS Input) VOL VOH Output Low Output High Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS = VIH or /OE = VIH or /WE = VIL or /UB = VIH , /LB = VIH /CS = VIL, VIN = VIH or VIL, II/O = 0mA /CS = VIL, VIN = VIH or VIL, Cycle Time = Min, 100% Duty, II/O = 0mA /CS < 0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS = VIH or /UB, /LB = VIH VIN = VIH or VIL /CS > Vcc - 0.2V or SL /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or LL VIN < Vss + 0.2V IOL = 2.1mA IOH = -1.0mA Min -1 -1 Typ1. - Max 1 1 Unit uA uA 5 mA 50 mA 5 mA 0.5 mA 0.2 6 uA 0.2 15 uA - 0.4 - V V 2.4 Note 1. Typical values are at Vcc = 3.0V TA = 25°C 2. Typical values are not 100% tested CAPACITANCE (Temp = 25°C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance(Add, /CS,/LB,/UB, /WE, /OE) COUT Output Capacitance(I/O) Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF Note : These parameters are sampled and not 100% tested Rev.11 / Jun.01 3 HY62UF16403A Series AC CHARACTERISTICS TA = 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified 55ns # Symbol Parameter Min. Max. READ CYCLE 1 tRC Read Cycle Time 55 2 tAA Address Access Time 55 3 tACS Chip Select Access Time 55 4 tOE Output Enable to Output Valid 30 5 tBA /LB, /UB Access Time 55 6 tCLZ Chip Select to Output in Low Z 10 7 tOLZ Output Enable to Output in Low Z 5 8 tBLZ /LB, /UB Enable to Output in Low Z 10 9 tCHZ Chip Deselection to Output in High Z 0 30 10 tOHZ Out Disable to Output in High Z 0 30 11 tBHZ /LB, /UB Disable to Output in High Z 0 30 12 tOH Output Hold from Address Change 10 WRITE CYCLE 13 tWC Write Cycle Time 55 14 tCW Chip Selection to End of Write 50 15 tAW Address Valid to End of Write 50 16 tBW /LB, /UB Valid to End of Write 50 17 tAS Address Set-up Time 0 18 tWP Write Pulse Width 45 19 tWR Write Recovery Time 0 20 tWHZ Write to Output in High Z 0 20 21 tDW Data to Write Time Overlap 25 22 tDH Data Hold from Write Time 0 23 tOW Output Active from End of Write 5 - 70ns Min. Max. 85ns Min Max. Unit 70 10 5 10 0 0 0 10 70 70 35 70 30 30 30 - 85 10 5 10 0 0 0 10 85 85 40 85 30 30 30 - ns ns ns ns ns ns ns ns ns ns ns ns 70 60 60 60 0 50 0 0 30 0 5 20 - 85 70 70 70 0 60 0 0 35 0 5 25 - ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA = 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load AC TEST LOADS VTM=2.8V 1029 Ohm DOUT CL(1) 1728 Ohm Note 1. Including jig and scope capacitance. Rev.11 / Jun.01 4 HY62UF16403A Series TIMING DIAGRAM READ CYCLE 1 (Note 1,4) tRC ADDR tAA tOH tACS /CS tCHZ(3) tBA /UB ,/ LB Data Out tBHZ(3) tOE /OE High-Z tCLZ(3) tOLZ(3) tBLZ(3) tOHZ(3) Data Valid READ CYCLE 2 (Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3(Note 1,2,4) /CS /UB, /LB tACS tCLZ(3) Data Out tCHZ(3) Data Valid Notes: 1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and /UB and/or /LB . 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active Rev.11 / Jun.01 5 HY62UF16403A Series WRITE CYCLE 1 (1,4,8) (/WE Controlled) tWC ADDR tWR(2) tCW /CS tAW tBW /UB,/LB tWP /WE tAS Data In tDW High-Z tDH Data Valid tWHZ(3,7) tOW (5) (6) Data Out WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled) tWC ADDR tAS tWR(2) tCW /CS tAW tBW /UB,/LB tWP /WE tDW Data In Data Out Rev.11 / Jun.01 High-Z tDH Data Valid High-Z 6 HY62UF16403A Series Notes: 1. A write occurs during the overlap of a low /WE, a low /CS and a low /UB and/or /LB . 2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active DATA RETENTION ELECTRIC CHARACTERISTIC TA=0°C to 70°C /-40°C to 85°C (I) Symbol Parameter VDR Iccdr tCDR tR Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time Test Condition /CS > Vcc - 0.2V or /UB, /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS > Vcc - 0.2V or /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or VIN < Vss + 0.2V Min 1.2 Typ1. - Max 3.3 Unit V SL - 0.1 3 uA LL - 0.1 10 uA 0 - - ns tRC - - ns See Data Retention Timing Diagram Notes: 1. Typical values are under the condition of TA = 25°C. 2. Typical value are sampled and not 100% tested DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 2.7V tCDR tR VIH VDR /CS >VCC-0.2V /CS VSS Rev.11 / Jun.01 7 HY62UF16403A Series PACKAGE INFORMATION 48ball Micro Ball Grid Array Package(M) BOTTOM VIEW TOP VIEW B A A1 CORNER INDEX AREA 6 5 4 3 2 1 A A B C D C C1 E 3.0 X 5.0 MIN FLAT AREA F G C1/2 H B1/2 B1 SIDE VIEW 5 E1 E2 C E SEATING PLANE A 4 r 3 D(DIAMETER) Symbol A B B1 C C1 D E E1 E2 r Rev.11 / Jun.01 Min. 8.3 7.1 0.3 0.85 0.6 0.2 - Typ. 0.75 3.75 8.4 5.25 7.2 0.35 0.9 0.65 0.25 - Max. 8.5 7.3 0.4 0.95 0.7 0.3 0.08 Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION. 8 HY62UF16403A Series MARKING INFORMATION Package uBGA Marking Example H Y U s s t x x x F x 6 4 3 A c y y w w p K O R x Index • HYUF643A : Part Name • c : Power Consumption -L -S • ss : Low Low Power : Super Low Power : Speed - 55 - 70 - 85 : 55ns : 70ns : 85ns • t : Temperature -C -I • yy : Year (ex : 00 = year 2000, 01= year 2001) • ww : Work Week ( ex : 12 = work week 12 ) • p : Process Code • xxxxx : Lot No. • KOR : Origin Country Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item Rev.11 / Jun.01 : Industrial ( -0 ~ 70 °C ) : Industrial ( -40 ~ 85 °C ) 9