HY62UF16804A Series 512Kx16bit full CMOS SRAM Document Title 512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM Revision History Revision No History Draft Date Remark 04 Initial Revision History Insert Revised - Reliability Spec Deleted Jul.02.2000 Preliminary 05 Change AC Characteristics - tBLZ : 5/5/5 ---> 10/10/10 Oct.23.2000 Preliminary 06 Part Number is changed - HY62UF16803A --> HY62UF16804A Nov.13.2000 Preliminary 07 Marking Instruction is inserted Dec.5.2000 Preliminary 08 Test Condition Changed - ILO / ISB / ISB1 / VDR / ICCDR Marking Istruction Inserted Dec.16.2000 Preliminary 09 Change Logo - Hyundai à Hynix Apr.28.2001 10 Change DC Parameter - Isb1(LL) : 40uA à - Isb1(Typ) : 8uA à - Icc : 5mA à - Icc1(1us) : 8mA à - Icc1(Min) : 50mA à Change Data Retention - IccDR(LL) : 25uA à Change AC Parameter - tOE : 35ns à : 40ns à - tCW : 50ns à - tAW : 50ns à - tBW : 50ns à - tWP : 45ns à - tCHZ : 30ns à - tOHZ : 30ns à - tBHZ : 30ns à Jan.28.2002 25uA 1uA 4mA 4mA 40mA 15uA 25ns@55ns 35ns@70ns 45ns@55ns 45ns@55ns 45ns@55ns 40ns@55ns 20ns@55ns , 30ns à 25ns@70ns 20ns@55ns , 30ns à 25ns@70ns 20ns@55ns , 30ns à 25ns@70ns This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.10 /Jan2002 Hynix Semiconductor HY62UF16804A DESCRIPTION FEATURES The HY62UF16804A is a high speed, super low power and 8Mbit full CMOS SRAM organized as 524,288 words by 16bits. The HY62UF16804A uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly wellsuited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(LL/SL-part) - 1.2V(min) data retention • Standard pin configuration - 48-uBGA Product Voltage Speed No. (V) (ns) HY62UF16804A-C 2.7~3.3 55/70/85 HY62UF16804A-I 2.7~3.3 55/70/85 Note 1. C : Commercial, I : Industrial 2. Current value is max. Operation Current/Icc(mA) 4 4 PIN CONNECTION ( Top View ) /CS IO1 IO10 IO11 A5 A6 IO2 IO3 Vss IO12 A17 A7 IO4 Vcc A8 A10 A13 IO15 IO14 A14 A15 IO6 IO7 A0 A3 A5 IO16 NC A12 A13 /WE IO8 A18 A8 A9 A10 A11 NC A11 ADD INPUT BUFFER Vcc IO13 Vss A16 IO5 Vss BLOCK DECODER A14 MEMORY ARRAY 512K x 16 I/O1 I/O8 DATA I/O BUFFER A4 WRITE DRIVER IO9 /UB A3 SENSE AMP NC COLUMN DECODER A2 ROW DECODER PRE DECODER A1 ADD INPUT BUFFER /OE A0 Temperature (°C) 0~70 -40~85 BLOCK DIAGRAM A1,A2 A4,A6~A7 A9 A12 A15~A18 ADD INPUT BUFFER /LB Standby Current(uA) LL SL 25 8 25 8 I/O9 I/O16 /CS /OE /LB /UB /WE PIN DESCRIPTION Pin Name /CS /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Lower Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Rev.10/Jan. 2002 Pin Name I/O1~I/O16 A0~A18 Vcc Vss NC Pin Function Data Inputs / Outputs Address Inputs Power(2.7V~3.3V) Ground No Connection 2 HY62UF16804A ORDERING INFORMATION Part No. Speed HY62UF16804A-DMC 55/70/85 HY62UF16804A-SMC 55/70/85 HY62UF16804A-DMI 55/70/85 HY62UF16804A-SMI 55/70/85 Note 1. C : Commercial, I : Industrial Power LL-part SL-part LL-part SL-part Package uBGA uBGA uBGA uBGA Temp. C C I I ABSOLUTE MAXIMUM RATINGS (1) Symbol VIN, VOUT Vcc Parameter Input/Output Voltage Power Supply TA Operating Temperature TSTG PD TSOLDER Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to Vcc+0.3V -0.3 to 3.6 0 to 70 -40 to 85 -55 to 150 1.0 260 • 10 Unit V V °C °C °C W °C • sec Remark HY62UF16804A-C HY62UF16804A-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS /WE /OE /LB /UB Mode H X L L L X X H H H X X H H L L X X H X L H L L H L L Deselected Deselected Output Disabled Output Disabled Read L X H L X L H L L H L Write I/O1~I/O8 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O I/O9~I/O16 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Power Standby Standby Active Active Active Active Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O1 -I/O8. When /UB is LOW, data is written or read to the upper byte, I/O9 -I/O16. Rev.10/Jan. 2002 2 HY62UF16804A RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.3(1) Typ. 3.0 0 - Max. 3.3 0 Vcc+0.3 0.6 Unit V V V V Note : 1. VIL = -1.5V for pulse width less than 30ns DC ELECTRICAL CHARACTERISTICS Vcc = 2.7V~3.3V, TA = 0°C to 70°C/ -40°C to 85°C Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc Vss < VOUT < Vcc, /CS = VIH or ILO Output Leakage Current /OE = VIH or /WE = VIL, /UB = /LB = VIH Operating Power Supply /CS = VIL, VIN = VIH or VIL, II/O = 0mA Icc Current Cycle Time=Min,100% duty, Average Operating II/O = 0mA, /CS = VIL,VIN = VIH or VIL Icc1 Current Cycle time = 1us, 100% duty, II/O = 0mA, /CS < 0.2V, VIN<0.2V /CS = VIH or /UB=/LB= VIH, TTL Standby Current ISB (TTL Input) VIN = VIH or VIL /CS > Vcc - 0.2V or SL Standby Current /UB=/LB > Vcc-0.2V, ISB1 (CMOS Input) VIN > Vcc-0.2V or LL VIN < Vss+0.2V VOL Output Low Voltage IOL = 2.1mA VOH Output High Voltage IOH = -1.0mA Min. -1 Typ. - Max. 1 Unit uA -1 - 1 uA - - 4 mA - - 40 mA - - 4 mA - - 0.5 mA - - 8 uA - 1 25 uA 2.4 - 0.4 - V V Max. 8 10 Unit pF pF Note : Typical values are at Vcc = 3.0V, TA = 25°C CAPACITANCE (Temp = 25°C, f = 1.0MHz) Symbol Parameter CIN Input Capacitance(Add, /CS, /LB, /UB /WE, /OE) COUT Output Capacitance(I/O) Condition VIN = 0V VI/O = 0V Note : These parameters are sampled and not 100% tested Rev.10/Jan. 2002 3 HY62UF16804A AC CHARACTERISTICS Vcc = 2.7V~3.3V, TA = 0°C to 70°C/ -40°C to 85°C unless otherwise specified -55 -70 # Symbol Parameter Max. Min. Max. Min. READ CYCLE 1 tRC Read Cycle Time 55 70 2 tAA Address Access Time 55 70 3 tACS Chip Select Access Time 55 70 4 tOE Output Enable to Output Valid 25 35 5 tBA /LB, /UB Access Time 55 70 6 tCLZ Chip Select to Output in Low Z 10 10 7 tOLZ Output Enable to Output in Low Z 5 5 8 tBLZ /LB, /UB Enable to Output in Low Z 10 10 9 tCHZ Chip Deselection to Output in High Z 0 20 0 25 10 tOHZ Out Disable to Output in High Z 0 20 0 25 11 tBHZ /LB, /UB Disable to Output in High Z 0 20 0 25 12 tOH Output Hold from Address Change 10 10 WRITE CYCLE 13 tWC Write Cycle Time 55 70 14 tCW Chip Selection to End of Write 45 60 15 tAW Address Valid to End of Write 45 60 16 tBW /LB, /UB Valid to End of Write 45 60 17 tAS Address Set-up Time 0 0 18 tWP Write Pulse Width 40 50 19 tWR Write Recovery Time 0 0 20 tWHZ Write to Output in High Z 0 20 0 25 21 tDW Data to Write Time Overlap 25 30 22 tDH Data Hold from Write Time 0 0 23 tOW Output Active from End of Write 5 5 - -85 Min Max. Unit 85 10 5 10 0 0 0 10 85 85 45 85 30 30 30 - ns ns ns ns ns ns ns ns ns ns ns ns 85 70 70 70 0 55 0 0 35 0 5 30 - ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA = 0°C to 70°C / -40°C to 85°C, unless otherwise specified PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW Output Load Other Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load AC TEST LOADS VTM = 2.8V 1029 Ohm DOUT CL(1) 1728 Ohm Note 1. Including jig and scope capacitance Rev.10/Jan. 2002 4 HY62UF16804A TIMING DIAGRAM READ CYCLE 1(Note 1,4) tRC ADDR tAA tOH tACS /CS tCHZ(3) tBA /UB ,/ LB Data Out tBHZ(3) tOE /OE High-Z tOLZ(3) tBLZ(3) tCLZ(3) tOHZ(3) Data Valid READ CYCLE 2(Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3(Note 1,2,4) /CS /UB, /LB tACS tCLZ(3) Data Out tCHZ(3) Data Valid Notes: 1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and /or /LB 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active Rev.10/Jan. 2002 5 HY62UF16804A WRITE CYCLE 1 (1,4,8) (/WE Controlled) tWC ADDR tWR(2) tCW /CS tAW tBW /UB,/LB tWP /WE tAS Data In tDW High-Z tDH Data Valid tWHZ(3,7) tOW (5) (6) Data Out WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled) tWC ADDR tCW tAS tWR(2) /CS tAW tBW /UB,/LB tWP /WE tDW Data In Data Out Rev.10/Jan. 2002 High-Z tDH Data Valid High-Z 6 HY62UF16804A Notes: 1. A write occurs during the overlap of a low / WE, a low /CS1 and low /UB and /or /LB. 2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured +200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active DATA RETENTION ELECTRIC CHARACTERISTIC TA = 0°C to 70°C / -40°C to 85°C Symbol Parameter VDR Vcc for Data Retention ICCDR Data Retention Current TCDR TR Chip Deselect to Data Retention Time Operating Recovery Time Test Condition /CS > Vcc - 0.2V or /UB=/LB > Vcc-0.2V, VIN > Vcc-0.2V or VIN < Vss+0.2V Vcc=1.5V, /CS > Vcc - 0.2V or /UB=/LB > Vcc-0.2V, VIN > Vcc-0.2V or VIN < Vss+0.2V Min Typ Max Unit 1.2 - 3.3 V LL - - 15 uA SL - - 8 uA 0 - - ns tRC(2) - - ns See Data Retention Timing Diagram Notes: 1. Typical values are under the condition of TA = 25°C . 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 2.7V tCDR tR VIH VDR /CS or /UB & /LB /CS>Vcc-0.2V or /UB=/LB > Vcc-0.2V Vss Rev.10/Jan. 2002 7 HY62UF16804A PACKAGE INFORMATION 48ball Micro Ball Grid Array Package(M) BOTTOM VIEW TOP VIEW B A A1 CORNER INDEX AREA 6 5 4 3 2 1 A A B C D C C1 E 3.0 X 5.0 MIN FLAT AREA F G C1/2 H B1/2 B1 SIDE VIEW 5 E1 E2 C E SEATING PLANE A 4 r 3 D(DIAMETER) Note Symbol A B B1 C C1 D E E1 E2 r Rev.10/Jan. 2002 Min. 0.3 0.85 0.6 0.2 - Typ. 0.75 3.75 7.4 5.25 8.5 0.35 0.9 0.65 0.25 - Max. 0.4 0.95 0.7 0.3 0.08 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION. 8 HY62UF16804A MARKING INSTRUCTION Package uBGA Marking Example H Y U F c s s t x x x x 6 8 0 4 A y w w p K O R x Index • HYUF6804A : Part Name • c : Power Consumption -D -S • ss : Low Low Power : Super Low Power : Speed - 55 - 70 - 85 : 55ns : 70ns : 85ns • t : Temperature -C -I • y : Year (ex : 0 = year 2000, 1= year 2001) • ww : Work Week ( ex : 12 = work week 12 ) • p : Process Code • xxxxx : Lot No. • KOR : Origin Country Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item Rev.10/Jan. 2002 : Commercial ( -0 ~ 70 °C ) : Industrial ( -40 ~ 85 °C ) 9