TM ICmic This X24C01 device has been acquired by IC Microsystems from Xicor, Inc. IC MICROSYSTEMS X24C01 1K 128 x 8 Bit 2 Serial E PROM FEATURES DESCRIPTION •2.7V to 5.5V Power Supply •Low Power CMOS The X24C01 is a CMOS 1024 bit serial E PROM, internally organized as 128 x 8. The X24C01 features a —Active Current Less Than 1 mA —Standby Current Less Than 50 µA •Internally Organized 128 x 8 serial interface and software protocol allowing operation on a simple two wire bus. •2 Wire Serial Interface Xicor E PROMs are designed and tested for applications requiring extended endurance. Inherent data 2 2 —Bidirectional Data Transfer Protocol •Four Byte Page Write Mode •Self Timed Write Cycle retention is greater than 100 years. —Typical Write Cycle Time of 5 ms •High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years •8-Pin Mini-DIP, 8-PIN MSOP, and 8-PIN SOIC Packages FUNCTIONAL DIAGRAM (8) V CC (4) V SS (5) SDA H.V. GENERATION TIMING & CONTROL START CYCLE START STOP LOGIC CONTROL LOGIC 2 INC LOAD (6) SCL E PROM 32 X 32 XDEC WORD ADDRESS COUNTER R/W YDEC 8 CK PIN D DATA REGISTER OUT D OUT ACK 3837 FHD F01 © Xicor, 1991 Patents Pending 3837-1.2 7/28/97 T1/C0/D0 SH 1 Characteristics subject to change without notice X24C01 PIN DESCRIPTIONS PIN CONFIGURATION Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. DIP PLASTIC Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be NC NC NC wire-ORed with any number of open drain or open collector outputs. V SS 1 8 2 7 3 X24C01 4 V CC NC 6 SCL SDA 5 3837 FHD F02 An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph. SOIC/MSOP NC NC PIN NAMES Symbol NC Description NC VSS VCC SDA SCL V SS No Connect Ground Supply Voltage Serial Data Serial Clock 1 8 2 7 3 X24C01 4 6 5 V CC NC SCL SDA 3837 FHD F03 3837 PGM T01 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 5V VCC x 0.1 to VCC x 0.9 2190Ο 10 ns OUTPUT VCC x 0.5 100pF 3837 PGM T02 3837 FHD F16 2 X24C01 DEVICE OPERATION The X24C01 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are re- onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a served for indicating start and stop conditions. Refer to Figures 1 and 2. master and the device being controlled is the slave. The master will always initiate data transfers and provide the Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is clock for both transmit and receive operations. Therefore, the X24C01 will be considered a slave in all applications. HIGH. The X24C01 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 3837 FHD F06 3 X24C01 The X24C01 will respond with an acknowledge after recognition of a start condition, a seven bit word address Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when and a R/W bit. If a write operation has been selected, the X24C01 will respond with an acknowledge after each SCL is HIGH. The stop condition is also used by the X24C01 to place the device in the standby power mode byte of data is received. after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. In the read mode the X24C01 will transmit eight bits of data, release the SDA line and monitor the line for an Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C01 will continue to transmit data. If an acknowledge is not detected, the X24C01 will terminate further data trans- release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW missions. The master must then issue a stop condition to return the X24C01 to the standby power mode and to acknowledge that it received the eight bits of data. Refer to Figure 3. place the device into a known state. Figure 2. Definition of Start and Stop SCL SDA START CONDITION STOP CONDITION 3837 FHD F07 Figure 3. Acknowledge Response From Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 3837 FHD F08 4 X24C01 WRITE OPERATIONS the page address. The X24C01 is capable of a four byte page write operation. It is initiated in the same manner as Byte Write To initiate a write operation, the master sends a start condition followed by a seven bit word address and a write bit. The X24C01 responds with an acknowledge, then waits for eight bits of data and then responds with an the byte write operation, but instead of terminating the transfer of data after the first data byte, the master can acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C01 After the receipt of each data byte, the two low order address bits are internally incremented by one. The high begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the X24C01 order five bits of the address remain constant. If the master should transmit more than four data bytes prior inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 4 for the address, acknowledge and data transfer sequence. to generating the stop condition, the address counter will “roll over” and the previously transmitted data will be Page Write The most significant five bits of the word address define Refer to Figure 5 for the address, acknowledge and data transfer sequence. transmit up to three more bytes. After the receipt of each data byte, the X24C01 will respond with an acknowledge. overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Figure 4. Byte Write S T BUS ACTIVITY: SDA LINE WORD A ADDRESS (n) R T S T DATA n O P P S L R A S / C K B M S BUS ACTIVITY: X24C01 B A C K W 3837 FHD F09 Figure 5. Page Write S T BUS ACTIVITY: A R WORD ADDRESS (n) DATA n DATA n+1 S T DATA n+3 O P T SDA LINE BUS ACTIVITY: X24C01 S P M S B L R A S / C B WK A C A C A C K K K 3837 FHD F10 5 X24C01 Figure 6. ACK Polling Sequence Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop WRITE OPERATION COMPLETED condition is issued to indicate the end of the host’s write operation the X24C01 initiates the internal write cycle. ENTER ACK POLLING ACK polling can be initiated immediately. This involves issuing the start condition followed by the word address for a write operation. If the X24C01 is still busy with the write operation no ACK will be returned. If the X24C01 ISSUE START has completed the write operation an ACK will be returned and the controller can then proceed with the next read or write operation. ISSUE SLAVE ADDRESS AND R/W = 0 READ OPERATIONS ISSUE STOP Read operations are initiated in the same manner as write operations with exception that the R/W bit of the ACK RETURNED? word address is set to a one. There are two basic read operations: byte read and sequential read. NO YES It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read NEXT OPERATION operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth NO A WRITE? clock cycle and then issue a stop condition. YES ISSUE STOP Byte Read To initiate a read operation, the master sends a start condition followed by a seven bit word address and a read bit. The X24C01 responds with an acknowledge and then transmits the eight bits of data. The read PROCEED PROCEED operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. 3837 FHD F11 Refer to Figure 7 for the start, word address, read bit, acknowledge and data transfer sequence. Figure 7. Byte Read S T BUS ACTIVITY: MASTER WORD A ADDRESS n R SDA LINE S BUS ACTIVITY: X24C01 S T O P T P L R A S / C K B M S B W 6 DATA n 3837 FHD F12 X24C01 The data output is sequential, with the data from address n followed by the data from n + 1. The address counter Sequential Read Sequential read is initiated in the same manner as the byte read. The first data byte is transmitted as with the for read operations increments all address bits, allowing the entire memory contents to be serially read during byte read mode, however, the master now responds with an acknowledge, indicating it requires additional one operation. At the end of the address space (address 127) the counter “rolls over” to zero and the X24C01 data. The X24C01 continues to output data for each acknowledge received. The read operation is termi- continues to output data for each acknowledge received. Refer to Figure 8 for the address, acknowledge nated by the master; by not responding with an acknowledge and by issuing a stop condition. and data transfer sequence. Figure 8. Sequential Read BUS ACTIVITY: ADDRESS A C A C A C K K K S T O P SDA LINE P A BUS ACTIVITY: X24C01 R / C WK DATA n DATA n+1 DATA n+2 DATA n+x 3837 FHD F13 Figure 9. Typical System Configuration V CC PULL-UP RESISTORS SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ MASTER TRANSMITTER RECEIVER MASTER TRANSMITTER/ RECEIVER 3837 FHD F14 7 X24C01 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. –65°C to +135°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ............................ –1.0V to +7.0V D.C. Output Current ............................................ 5 mA Lead Temperature (Soldering, ............................. 300°C 10 Seconds) This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial Industrial Military 0°C –40°C –55°C 70°C +85°C +125°C Supply Voltage Limits X24C01 X24C01-3.5 X24C01-3 X24C01-2.7 4.5V to 5.5V 3.5V to 5.5V 3.0V to 5.5V 2.7V to 5.5V D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Limits Symbol ICC(1) ICC(2) ISB1(1) Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current ISB2(1) ILI ILO VlL(2) VIH(2) VOL VCC Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Min. Max. Units 1 2 100 mA 50 10 10 VCC x 0.3 –1.0 VCC x 0.7VCC + 0.5 0.4 Test Conditions SCL = VCC x 0.1/VCC x 0.9 Levels @ 100 KHz, SDA = Open ∝A SCL = SDA = VCC, VCC = 5V ± 10% ∝A ∝A ∝A SCL = SDA = VCC, VCC = 2.7V V V V VIN = GND to VCC VOUT = GND to VCC IOL = 2.1 mA 3837 PGM T03 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O CIN(3) (3) Parameter Input/Output Capacitance (SDA) Input Capacitance (SCL) Max. Units 8 6 pF pF Test Conditions VI/O = 0V VIN = 0V 3837 PGM T05 Notes: (1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. 8 X24C01 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Read & Write Cycle Limits Symbol fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH Parameter Min. Max. Units SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 0 100 100 KHz ns 0.3 4.7 3.5 ∝s ∝s ∝s ∝s ∝s ∝s ∝s 4.0 4.7 4.0 4.7 0 250 ns ∝s 1 300 ns ∝s 4.7 300 ns 3837 PGM T06 POWER-UP TIMING Symbol Parameter Max. Units tPUR(4) tPUW(4) Power-up to Read Operation Power-up to Write Operation 1 5 ms ms 3837 PGM T07 Bus Timing t t F t HIGH t LOW R SCL t SU:STA t HD:STA t t HD:DAT SU:DAT t SU:STO SDA IN t t AA DH t BUF SDA OUT 3837 FHD F04 Note: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 9 X24C01 WRITE CYCLE LIMITS Symbol t Parameter (5) Min. Typ. Write Cycle Time (6) WR Max. Units 10 ms 5 3837 PGM T08 The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C01 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its word address. Write Cycle Timing SCL SDA ACK 8th BIT WORD n t WR STOP CONDITION START CONDITION X24C01 ADDRESS 3837 FHD F05 Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. SYMBOL TABLE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors WAVEFORM RESISTANCE (KΟ) 120 V R MIN 100 80 = R MAX = CC MAX I OL MIN =2.6KΟ t R C BUS MAX. RESISTANCE 60 40 20 MIN. RESISTANCE 0 0 20 40 60 INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Changing: State Not Known Allowed 80100120 N/A BUS CAPACITANCE (pF) 3837 FHD F15 10 Center Line is High Impedance X24C01 PACKAGING INFORMATION 8-LEAD PLASTIC IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.092 (2.34) DIA. NOM. 0.255 (6.47) 0.245 (6.22) PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.060 (1.52) 0.020 (0.51) 0.140 (3.56) 0.130 (3.30) SEATING PLANE 0.020 (0.51) 0.015 (0.38) 0.150 (3.81) 0.125 (3.18) 0.062 (1.57) 0.058 (1.47) 0.110 (2.79) 0.090 (2.29) 0.015 (0.38) MAX. 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0° 15° TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 11 X24C01 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.027 (0.683) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS) 3926 FHD F22 12 X24C01 PACKAGING INFORMATION 8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M 0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) TYP R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 0.007 (0.18) 0.005 (0.13) 7° TYP 0.008 (0.20) 0.004 (0.10) 0.150 (3.81) REF. 0.193 (4.90) REF. NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 3003 ILL 01 13 X24C01 ORDERING INFORMATION X24C01 P T G -V Device VCC Limits Blank = 4.5V to 5.5V 3.5 = 3.5V to 5.5V 3 = 3.0V to 5.5V 2.7 = 2.7V to 5.5V G=RoHS Compliant Lead Free package Blank = Standard package. Non lead free Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC M = 8-Lead MSOP Part Mark Convention X24C01 XG Blank = 8-Lead SOIC P = 8-Lead Plastic DIP M = 8-Lead MSOP G = RoHS compliant lead free X Blank = 4.5V to 5.5V, 0°C to +70°C F = 2.7V to 5.5V, 0°C to +70°C G = 2.7V to 5.5V, –40°C to +85°C I = 4.5V to 5.5V, –40°C to +85°C B = 3.5V to 5.5V, 0°C to +70°C C = 3.5V to 5.5V, –40°C to +85°C D = 3.0V to 5.5V, 0°C to +70°C E = 3.0V to 5.5V, –40°C to +85°C M = 4.5V to 5.5V, –55°C to +125°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 14