Recommended System Management Alternative: X4163 X24C16 16K 2048 x 8 Bit Serial EEPROM DESCRIPTION • 2.7V to 5.5V power supply • Low power CMOS —Active read current less than 1 mA —Active write current less than 3 mA —Standby current less than 1µA • Internally organized 2048 x 8 • 2-wire serial interface —Bidirectional data transfer protocol • Sixteen byte page write mode —Minimizes total write time per byte • Self-timed write cycle —Typical write cycle time of 5 ms • High reliability —Endurance: 1,000,000 cycles —Data retention: 100 years • Packages —14-lead TSSOP —8-lead SOIC The X24C16 is a CMOS 16,384 bit serial EEPROM, internally organized 2048 X 8. The X24C16 features a serial interface and software protocol allowing operation on a simple two wire bus. Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct s FEATURES The X24C16 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology. The X24C16 utilizes Xicor’s proprietary Direct Write™ cell providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. BLOCK DIAGRAM (8) VCC (4) VSS (7) TEST (5) SDA H.V. Generation Timing & Control START Cycle START STOP Logic Control Logic (6) SCL Slave Address Register +Comparator LOAD (3) A2 (2) A1 (1) A0 or Word Address Counter R/W Y Dec 8 ic X REV 1.1.1 12/8/00 INC EEPROM 128 X 128 X Dec CK PIN Data Register DOUT DOUT ACK www.xicor.com Characteristics subject to change without notice. 1 of 14 X24C16 PIN DESCRIPTIONS PIN CONFIGURATION Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Address (A0, A1, A2) The A0, A1 and A2 inputs are unused by the X24C16, however, they must be tied to VSS to insure proper device operation. Symbol A0–A2 SDA SCL TEST VSS VCC NC 8 VCC 2 7 TEST A2 3 6 SCL VSS 4 5 SDA X24C16 14-Lead TSSOP An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the PullUp Resistor selection graph at the end of this data sheet. PIN NAMES 1 A1 Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. A0 s 8-Lead SOIC A0 1 14 VCC A1 2 13 TEST NC 3 12 NC NC 4 X24C16 11 NC NC 5 10 NC A2 6 9 SCL VSS 7 8 SDA DEVICE OPERATION Description The X24C16 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master, and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C16 will be considered a slave in all applications. Address Inputs Serial Data Serial Clock Hold at VSS Ground Supply Voltage No Connect Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. X ic or Figure 1. Data Validity REV 1.1.1 12/8/00 SCL SDA Data Stable Data Change www.xicor.com Characteristics subject to change without notice. 2 of 14 X24C16 Figure 2. Definition of Start and Stop s SCL Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct SDA START Bit STOP Bit Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C16 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C16 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. The X24C16 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C16 will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the X24C16 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C16 will continue to transmit data. If an acknowledge is not detected, the X24C16 will terminate further data transmissions. The master must then issue a stop condition to return the X24C16 to the standby power mode and place the device into a known state. Figure 3. Acknowledge Response from Receiver SCL from Master 1 8 9 or Data Output from Transmitter X ic Data Output from Receiver REV 1.1.1 12/8/00 START Acknowledge www.xicor.com Characteristics subject to change without notice. 3 of 14 X24C16 Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C16 this is fixed as 1010[B]. WRITE OPERATIONS Figure 4. Slave Addressing High Order Word Address Device Type Identifier 1 0 Following the start condition, the X24C16 monitors the SDA bus, comparing the slave address being transmitted with its slave address (device type). Upon a correct compare, the X24C16 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C16 will execute a read or write operation. s DEVICE ADDRESSING 1 0 A2 A0 A1 R/W The next three bits of the slave address field are the bank select bits. They are used by the host to toggle between the eight 256 x 8 banks of memory. These are, in effect, the most significant bits for the word address. The next three bits of the slave address are an extension of the array’s address and are concatenated with the eight bits of address in the word address field, providing direct access to the whole 2048 x 8 array. Byte Write For a write operation, the X24C16 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 2048 words in the array. Upon receipt of the word address the X24C16 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C16 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C16 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence. Figure 5. Byte Write Bus Activity: Master SDA Bus S T A R T Slave Address Word Address S T O P Data S P A C K Bus Activity: X24C16 A C K A C K Figure 6. Page Write Bus Activity: Master SDA Line Word Address (n) S T O P Data n + 15 Data n + 1 Data n P A C K A C K A C K A C K A C K Note: In this example n = xxxx 000 (B); x = 1 or 0 X ic Slave Address S or Bus Activity: X24C16 S T A R T REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 4 of 14 X24C16 Flow 1. ACK Polling Sequence s Write Operation Completed Enter ACK Polling Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct Page Write The X24C16 is capable of a 16 byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the X24C16 will respond with an acknowledge. After the receipt of each word, the four low order address bits are internally incremented by one. The high order seven bits of the address remain constant. If the master should transmit more than sixteen words prior to generating the stop condition, the address counter will “roll over” and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Issue START Issue Slave Address and R/W = 0 NO YES Next Operation a Write? NO YES Issue Byte Address Issue STOP PROCEED PROCEED X ic or Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the X24C16 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C16 is still busy with the write operation, no ACK will be returned. If the X24C16 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Refer to Flow 1. ACK Returned? Issue STOP REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 5 of 14 X24C16 Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C16 and then by the eight bit word. The read operation is terminated by the master by not responding with an acknowledge, and issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence. s READ OPERATIONS It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle, or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Current Address Read Internally, the X24C16 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the X24C16 issues an acknowledge and transmits the eight bit word. The read operation is terminated by the master by not responding with an acknowledge, and issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer. Figure 7. Current Address Read Bus Activity: Master SDA Line S T A R T Slave Address Data S S T O P P A C K Bus Activity: X24C16 Figure 8. Random Read Bus Activity: Master SDA Line Bus Activity: X24C16 S T A R T S or Slave Address Data n A C K A C K S T O P P S Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C16 continues to output data for each acknowledge received. The read operation is terminated by the master by not responding with an acknowledge, and then issuing a stop condition. A C K The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 2047), the counter “rolls over” to 0 and the X24C16 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence. X ic S T A R T Word Address n Slave Address REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 6 of 14 X24C16 Figure 9. Sequential Read Bus Activity: Master A C K Slave Address A C K A C K S T O P P Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct A C K s SDA Line Bus Activity: X24C16 Data n Data n+1 Data n+2 Data n+x Figure 10. Typical System Configuration VCC Pull-Up Resistors SDA SCL Slave Receiver Slave Transmitter/ Receiver Master Transmitter Master Transmitter/ Receiver X ic or Master Transmitter/ Receiver REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 7 of 14 X24C16 COMMENT Temperature under bias ........................–65 to +135°C Storage temperature .............................–65 to +150°C Voltage on any pin with respect to VSS .......–1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct s ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. Max. Supply Voltage Limits 0°C +70°C X24C16–2.5 2.5V to 5.5V –40°C +85°C D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Unit Test Conditions mA SCL = VCC X 0.1/VCC X 0.9 Levels @ 100 kHz, SDA = Open, All Other Inputs = GND or VCC – 0.3V ICC1 VCC supply current (read) 1 ICC2 VCC supply current (write) 3 ISB1(1) VCC standby current X24C16 150 ISB2(1) VCC standby current X24C16-3 50 µA SCL = SDA = VCC – 0.3V, All Other Inputs = GND or VCC, VCC = 3.3V ±10% ISB3(1) VCC standby current X24C16-2.5 1 µA SCL = SDA = VCC – 0.3V, All Other Inputs = GND or VCC, VCC = 2.5V ISB4(1) VCC standby current X24C16-1.8 1 µA SCL = SDA = VCC – 0.3V, All Other Inputs = GND or VCC, VCC = 1.8V ILI Input leakage current 10 µA VIN = GND to VCC ILO Output leakage current VOUT = GND to VCC VlL(2) Input low voltage VIH(2) Input high voltage VOL Output low voltage µA SCL = SDA = VCC – 0.3V, All Other Inputs = GND or VCC, VCC = 5V 10 µA VCC x 0.3 V VCC x 0.7 VCC + 0.5 V –1.0 0.4 V IOL = 3mA CAPACITANCE TA = +25°C, f = 1.0 MHz, VCC = 5V Symbol Parameter CI/O Unit Test Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V ic CIN(3) Max. or (3) X Notes: (1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 8 of 14 X24C16 A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC X 0.5 5V s 1533Ω Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct Output 100pF A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol Parameter fSCL SCL clock frequency Min. Max. Unit 0 400 kHz 100 ns 3.5 µs TI Noise suppression time constant at SCL, SDA inputs tAA SCL low to SDA data out valid 0.3 tBUF Time the bus must be free before a new transmission can start 4.7 µs Start condition hold time 4.0 µs tLOW Clock low period 4.7 µs tHIGH Clock high period 4.0 µs tSU:STA Start condition setup time (for a repeated start condition) 4.7 µs tHD:DAT Data in hold time 0 µs tSU:DAT Data in setup time 250 ns tHD:STA tR SDA and SCL rise time 1 µs tF SDA and SCL fall time 300 ns tSU:STO tDH Stop condition setup time 4.7 µs Data out hold time 300 ns POWER-UP TIMING(4) Symbol tPUR tPUW Max. Unit Power-up to read operation 1 ms Power-up to write operation 5 ms (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. X ic or Note: Parameter REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 9 of 14 X24C16 Bus Timing tHIGH tF tLOW tR tHD:STA SDA IN tHD:DAT tAA SDA OUT tSU:DAT tSU:STO Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct tSU:STA s SCL tDH tBUF Write Cycle Limits Symbol (6) tWC Parameter Min. Write Cycle Time Typ.(5) Max. Unit 5 10 ms Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X24C16 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Bus Timing SCL 8th Bit SDA ACK Word n tWC X24X16 Address START Condition X ic or STOP Condition REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 10 of 14 X24C16 SYMBOL TABLE WAVEFORM 120 V RMin. = CC Max. =1.8KΩ IOL Min. 80 60 40 20 0 RMAX.= tR CBUS OUTPUTS Must be steady Will be steady Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct Resistance (KΩ) 100 INPUTS s Guidelines for Calculating Typical Values of Bus Pull-Up Resistors Max. Resistance Min. Resistance 0 20 40 60 80 100 120 Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X ic or Bus Capacitance (pF) May change from Low to High REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 11 of 14 X24C16 PACKAGING INFORMATION Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct s 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0° - 8° 0.050"Typical 0.050" Typical 0.0075 (0.19) 0.010 (0.25) 0.250" 0.030" Typical 8 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) X ic or 0.016 (0.410) 0.037 (0.937) REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 12 of 14 X24C16 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct s .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) X ic or See Detail “A” REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 13 of 14 X24C16 Ordering Information X24C16 X X -X Sy Int st eg F em ra or te a M d an S mo ag olu re em tio en n u t P se ro du ct s VCC Range 2.7 = 2.7V to 5.5V Device Temperature Range Blank = Commercial = 0°C to +70°C I = –40°C to +85°C Package S8 = 8-Lead SOIC V14 = 14-Lead TSSOP Part Mark Convention X24C16 X S8 = 8-Lead SOIC V14 = 14-Lead TSSOP X AB = 2.7V to 5.5V, 0°C to +70°C AD = 2.7V to 5.5V, –40°C to +85°C LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS or Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY ic In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. X Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1.1 12/8/00 www.xicor.com Characteristics subject to change without notice. 14 of 14