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CDS-1402
14-Bit, Very Fast Settling
Correlated Double Sampling Circuit
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Use with 10 to 14-bit A/D converters
5 Megapixels/second minimum throughput (14 bits)
±2.5V input/output ranges, Gain = –1
Low noise, 200µVrms
Two independent S/H amplifiers
Gain matching between S/H's
Offset adjustments for each S/H
Four external A/D control lines
Small package, 24-pin ceramic DDIP
Low power, 350mW
Low cost
INPUT/OUTPUT CONNECTIONS
GENERAL DESCRIPTION
The CDS-1402 is an application-specific, correlated double
sampling (CDS) circuit designed for electronic-imaging
applications that employ CCD's (charge coupled devices) as
their photodetector. The CDS-1402 has been optimized for
use in digital video applications that employ 10 to 14-bit A/D
converters. The low-noise CDS-1402 can accurately
determine each pixel's true video signal level by sequentially
sampling the pixel's offset signal and its video signal and
subtracting the two. The result is that the consequences of
residual charge, charge injection and low-frequency "kTC"
noise on the CCD's output floating capacitor are effectively
eliminated. The CDS-1402 can also be used as a dual
sample-hold amplifier in a data acquisition system.
DO NOT CONNECT
2
1
2
3
4
5
6
7
8
9
10
11
12
OFFSET ADJUST V1
DO NOT CONNECT
ANALOG INPUT 1
ANALOG INPUT 2
ANALOG GROUND
S/H1 OUT
S/H1 ROUT
S/H2 SUMMING NODE
OFFSET ADJUST V2
DO NOT CONNECT
S/H1 COMMAND
S/H2 COMMAND
FUNCTION
24
23
22
21
20
19
18
17
16
15
14
13
+5V ANALOG SUPPLY
ANALOG GROUND
V OUT
ANALOG GROUND
A/D CLOCK2
A/D CLOCK2
A/D CLOCK1
A/D CLOCK1
+5V DIGITAL SUPPLY
DIGITAL GROUND
ANALOG GROUND
–5V ANALOG SUPPLY
500Ω
50Ω
CH
500Ω
ANALOG INPUT 1
PIN
(continued on page 3)
100kΩ
1
FUNCTION
and four control lines for triggering the A/D converter used in
conjunction with the CDS-1402. The CDS circuit's "pingpong" timing approach (the offset signal of the "n+1" pixel can
be acquired while the video output of the "nth" pixel is being
converted) guarantees a minimum throughput, in a 14-bit
application, of 5MHz. In other words, the true video signal
(minus offset) will be available
The CDS-1402 contains two sample-hold amplifiers and
appropriate support/control circuitry. Features include
independent offset-adjust capability for each S/H,
adjustment for matching gain between the two S/H's,
OFFSET ADJUST V1
PIN
–
3
S/H 1
7
S/H1 ROUT
6
S/H1 OUT
+
OPTIONAL
OFFSET ADJUST V2 9
100kΩ
450Ω
8
500Ω
S/H2
SUMMING NODE
DO NOT CONNECT 10
CH
500Ω
ANALOG INPUT 2
4
–
S/H 2
22 V OUT
+
S/H1 COMMAND 11
18 A/D CLOCK 1
S/H2 COMMAND 12
19 A/D CLOCK 2
17 A/D CLOCK 1
20 A/D CLOCK 2
5, 14, 21, 23
ANALOG GROUND
24
+5V ANALOG
SUPPLY
13
–5V ANALOG
SUPPLY
16
+5V DIGITAL
SUPPLY
15
DIGITAL
GROUND
Figure 1. CDS-1402 Functional Block Diagram
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) • Tel: (508) 339-3000 Fax: (508) 339-6356 • For immediate assistance: (800) 233-2765
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CDS-1402
PHYSICAL/ENVIRONMENTAL
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+5V Analog Supply (Pin 24)
–5V Analog Supply (Pin 13)
+5V Digital Supply (Pin 16)
Digital Inputs (Pins 11, 12)
Analog Inputs (Pins 3, 4)
Lead Temperature (10 seconds)
LIMITS
UNITS
0 to +6.3
0 to –6.3
–0.3 to +6
–0.3 to +VDD +0.3
±3.2
+300
Volts
Volts
Volts
Volts
Volts
°C
PARAMETERS
MIN.
TYP.
MAX.
UNITS
0
–55
—
—
+70
+125
°C
°C
—
—
–65
5
22
—
—
—
+150
°C/W
°C/W
°C
Operating Temp. Range, Case
CDS-1402MC
CDS-1402MM
Thermal Impedance
θjc
θca
Storage Temperature Range
Package Type
Weight
24-pin, metal-sealed, ceramic DDIP
0.42 ounces(12 grams)
FUNCTIONAL SPECIFICATIONS
(TA = +25°C, ±VCC = ±5V, +VDD = +5V, pixel rate = 5MHz, and a minimum warmup time of 2 minutes unless otherwise noted.)
+25°C
0 to +70°C
–55 to +125°C
ANALOG INPUTS ➀
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
Input Voltage Range
Input Resistance
Input Capacitance
±2.5
—
—
—
500
7
—
—
15
±2.5
—
—
—
500
7
—
—
15
±2.5
—
—
—
500
7
—
—
15
Volts
Ohms
pF
+2.0
—
—
—
—
—
—
—
—
+0.8
+10
–10
+2.0
—
—
—
—
—
—
—
—
+0.8
+10
–10
+2.0
—
—
—
—
—
—
—
—
+0.8
+10
–10
Volts
Volts
µA
µA
—
—
—
—
—
—
—
—
—
5
±3
±0.5
±5
±3
±0.5
±5
±3
±0.5
±10
—
±10
±1
±25
±10
±1
±25
±10
±1.5
±25
—
—
—
—
—
—
—
—
—
—
5
±4
±0.7
±10
±4
±0.7
±10
±4
±0.5
±10
—
±10
±1
±25
±10
±1
±25
±10
±1.5
±25
—
—
—
—
—
—
—
—
—
—
5
±5
±0.75
±15
±5
±0.75
±15
±5
±0.75
±15
—
±10
±1
±25
±10
±1
±25
±10
±1.5
±30
—
mV
%
mV
mV
%
mV
mV
%
mV
MSPS
—
—
—
—
—
24
8
±500
10
5
—
—
—
—
—
—
—
—
—
—
24
8
±500
10
5
—
—
—
—
—
—
—
—
—
—
24
8
±500
10
5
—
—
—
—
—
MHz
MHz
V/µs
ns
ps rms
—
50
100
—
60
100
—
75
100
ns
—
—
—
—
—
—
20
200
72
200
±3.2
±10
—
—
—
—
—
±25
—
—
—
—
—
—
20
200
72
200
±3.2
±10
—
—
—
—
—
±25
—
—
—
—
—
—
20
200
72
200
±3.2
±15
—
—
—
—
—
±25
ns
µVrms
dB
ns
V
mV/µs
±2.5
—
—
—
0.5
—
—
—
±20
±2.5
—
—
—
0.5
—
—
—
±20
±2.5
—
—
—
0.5
—
—
—
±20
Volts
Ohms
mA
+3.9
—
—
—
—
—
—
—
—
+0.4
–4
+4
+3.9
—
—
—
—
—
—
—
—
+0.4
–4
+4
+3.9
—
—
—
—
—
—
—
—
+0.4
–4
+4
Volts
Volts
mA
mA
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
PERFORMANCE
Sample Mode Offset Error - S/H1
Gain Error - S/H1
Pedestal - S/H1
Sample Mode Offset Error - S/H2
Gain Error - S/H2
Pedestal - S/H2
Sample Mode Offset Error - CDS
Differential Gain Error - CDS
Pedestal - CDS
Pixel Rate (14-bit settling) ➁
Input Bandwidth, ±2.5V
Small Signal (–20dB input)
Large Signal (–0.5dB input)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time ➀
(to ±0.01%, 5V step)
Hold Mode Settling Time
(to ±0.15mV)
Noise
Feedthrough Rejection
Overvoltage Recovery Time
S/H Saturation Voltage
Droop Rate
ANALOG OUTPUTS ➂
Output Voltage Range
Output Impedance
Output Current
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
➀ Pins 3 and 4.
➁ See Figure 4 for relationship between input voltage, accuracy, and acquisition time.
2
➂ Pins 6 and 22.
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CDS-1402
+25°C
POWER REQUIREMENTS
Power Supply Ranges
+5V Analog Supply
–5V Analog Supply
+5V Digital Supply
Power Supply Currents
+5V Analog Supply
–5V Analog Supply
+5V Digital Supply
Power Dissipation
Power Supply Rejection
0 to +70°C
–55 to +125°C
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
+4.75
–4.75
+4.75
+5.0
–5.0
+5.0
+5.25
–5.25
+5.25
+4.75
–4.75
+4.75
+5.0
–5.0
+5.0
+5.25
–5.25
+5.25
+4.75
–4.75
+4.75
+5.0
–5.0
+5.0
+5.25
–5.25
+5.25
Volts
Volts
Volts
—
—
—
—
—
+35
–35
+2
350
60
+50
–50
+5
500
—
—
—
—
—
—
+35
–35
+2
350
60
+50
–50
+5
500
—
—
—
—
—
—
+35
–35
+2
350
60
+50
–50
+5
500
—
mA
mA
mA
mW
dB
GENERAL DESCRIPTION (continued)
FUNCTIONAL DESCRIPTION
at the output of the CDS-1402 every 200ns. This correlates
with the fact that an acquisition time of 100ns is required for
each internal S/H amplifier (5V step acquired to ±0.01%
accuracy). The input and output of the CDS-1402 can swing
up to ±2.5 Volts.
Correlated Double Sampling
All photodetector elements (photodiodes, photomultiplier tubes,
focal plane arrays, charge coupled devices, etc.) have unique
output characteristics that call for specific analog-signalprocessing (ASP) functions at their outputs. Charge coupled
devices (CCD’s), in particular, display a number of unique
characteristics. Among them is the fact that the "offset error"
associated with each individual pixel (i.e., the apparent
photonic content of that pixel after having had no light incident
upon it) changes each and every time that particular pixel is
accessed.
The functionally complete CDS-1402 is packaged in a single,
24-pin, ceramic DDIP. It operates from ±5V analog and +5V
digital supplies and typically consumes 350mW. Though the
CDS-1402's approach to CDS appears straightforward (see
Funtional Description ), the circuit actually exploits an elegant
architecture whose tradeoffs enable it to offer wide-bandwidth,
low-noise and high-throughput combinations unachievable until
now. The CDS-1402, a generic type of circuit, can be used
with most 10 to 14-bit A/D converters. However, DATEL offers
A/D converters optimized for use with CDS-1402.
Most of us think of an offset as a constant parameter that
either can be compensated for (by performing an offset
adjustment) or can be measured, recorded, and subtracted
from subsequent readings to yield more accurate data.
Contending with an offset that varies from reading to reading
requires measuring and recording (or capturing and storing)
the offset each and every time, so it can be subtracted from
each subsequent data reading.
TECHNICAL NOTES
The "double sampling" aspect of CDS refers to the operation of
sampling and storing/recording a given pixel’s offset and then
sampling the same pixel’s output an instant later (with both the
offset and the video signal present) and subsequently
subtracting the two values to yield what is referred to as the
"valid video" output for that pixel.
1. To achieve specified performance, all power supply pins
should be bypassed with 2.2µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. All ANALOG
GROUND (pins 5, 14, 21 and 23) and DIGITAL GROUND
(pin 15) pins should be tied to a large analog ground plane
beneath the package.
The "correlated" in CDS refers to the fact that the two samples
must be taken close together in time because the offset is
constantly varying. Reasons for this phenomena are
discussed below.
2. In the CDS configuration, to avoid saturation of the S/H
amplifiers, the maximum analog inputs and conditions are
as follows:
ANALOG INPUT 1 < ±3.2V
(ANALOG INPUT 1 – ANALOG INPUT 2) < ±3.2V
At the output of all CCD's, transported pixel charge (electrons)
is converted to a voltage by depositing the charge onto a
capacitor (usually called the output or "floating" capacitor).
The voltage that develops across this capacitor is obviously
proportional to the amount of deposited charge (i.e., the
number of electrons) according to ∆V = ∆Q/C. Once settled,
the resulting capacitor voltage is buffered and brought to the
CCD’s output pin as a signal whose amplitude is proportional
to the total number of photons incident upon the relevant pixel.
3. The combined video and reference/offset signal from the
CCD array must be applied to S/H2, while the reference/
offset signal is applied to S/H1.
4. To use as a CDS circuit, tie pin 8 (S/H2 SUMMING NODE)
to either pin 6 (S/H1 OUT), through a 100 Ohm
potentiometer, or directly to pin 7 (S/H1 ROUT). In both
cases, the CCD's output is tied to pins 3 (ANALOG INPUT
1) and 4 (ANALOG INPUT 2). As shown in Figure 5, the
100Ω potentiometer is for gain matching.
After the output signal has been recorded, the floating
capacitor is discharged ("reset", "clamped", "dumped") and
made ready to accept charge from the next pixel. This is when
the problems begin. (This is a somewhat oversimplified
explanation in that the floating capacitor is not usually
"discharged" but, in fact, "recharged" to some predetermined
dc voltage, usually called the "reference level". The pixel offset
appears as an output deviation from that reference level.)
5. To use as a dual S/H, leave pin 7 (S/H1 ROUT) and pin 8
(S/H2 SUMMING NODE) floating. Pin 6 (S/H1 OUT) will
be the output of S/H1 and pin 22 (V OUT) will be the output
of S/H2.
6. See Figure 4 for acquisition time versus accuracy and input
voltage step amplitude.
3
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CDS-1402
The fourth major contributor to pixel offset is a low-frequency
noise component (usually called 1/f noise or pink noise)
associated with the CCD's output buffer amplifier.
The floating capacitor is normally discharged (charged) via a
shunt switch (typically a FET structure) that has a non-zero
"on" resistance. When the switch is on, its effective series
resistance exhibits thermal noise (Johnson noise) due to the
random motion of thermally energized charge. Because the
shunt switch is in parallel with the floating capacitor, the
instantaneous value of the thermal noise (expressed in either
Volts or electrons) appears across the cap. When the shunt
switch is opened, charge/voltage is left on the floating cap.
Due to all of these contributing factors, "pixel offsets" vary from
sample to sample in an inconsistent, unpredictable manner.
Traditional Approach to CDS
There are a number of techniques for dealing with the varyingoffset idiosyncrasy of CCD's. The most prevalent has been
what can be called the "sample-sample-subtract" technique.
This approach requires the use of two high-speed sample-hold
(S/H) amplifiers and a difference amplifier. The first S/H is
used to acquire and hold a given pixel's offset. Immediately
after that, the second S/H acquires and holds the same pixel’s
offset+video signal. After both the S/H outputs have fully
settled, the difference amplifier subtracts the offset from the
offset+video yielding the valid video signal.
The magnitude of this "captured noise voltage" is a function of
absolute temperature (T), the value of the floating capacitor
(C) and Boltzman’s constant (k). It is commonly referred to as
"kTC" noise.
The second contributor to the constantly varying pixel offsets
is the fact that, at high pixel rates, the floating capacitor never
has time to fully discharge (charge) during the period in which
its shunt switch is closed. There is always some "residual"
charge left on the cap, and the amount of this charge varies as
a function of what was the total charge held during the
previous pixel. This amount of residual charge is, in fact,
deterministic (if you know the previous charge and the number
of time constants in the discharge period), however, it is less
of a contributor than "kTC" noise.
CDS-1402 Approach (See Figure 1)
The DATEL CDS-1402 takes a slightly different, though clearly
superior, approach to CDS. It can be called the "samplesubtract-sample" approach.
The third major contributor to pixel offset is the fact that as the
shunt FET is turned off, the voltage across (and the charge
stored on) its parasitic junction capacitances changes. The
result is an "injection" of excess charge onto the floating cap
causing a voltage step normally called a "pedestal".
Note that the CDS-1402 has been configured to offer the
greatest amount of user flexibility. Its two S/H circuits function
independently. They have separate input and output pins.
Each has its own independent control lines. The control-line
signals are delayed, buffered, and brought back out of the
RESET N+1
RESET N
(CCD OUTPUT)
ANALOG INPUT FOR CDS
(Pins 3 and 4 are tied together)
OFFSET N
OFFSET +
VIDEO N
100ns typ.
OFFSET N+1
HOLD
S/H1 (Pin 11)
S/H2 (Pin 12)
100ns typ.
HOLD
30ns typ.
A/D CLOCK 1 (Pin 17)
A/D CLOCK 1 (Pin 18)
30ns typ.
A/D CLOCK 2 (Pin 19)
A/D CLOCK 2 (Pin 20)
VOLTAGE OUTPUT (Pin 22)
VIDEO SIGNAL N-1
VIDEO SIGNAL N
NOTE: Not Drawn to Scale
Figure 2. CDS-1402 Typical Timing Diagram
4
OFFSET +
VIDEO N+1
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CDS-1402
package so they can be used to control other circuit functions.
Each S/H has two pins for offset adjusting (if required), one for
current and one for voltage.
Timing Notes
See Figure 2, Typical Timing Diagram. It is advisable that
neither of the CDS-1402's S/H amplifiers be in their sample/
track mode when large, high-speed transients (normally
associated with clock edges) are occurring throughout the
system. This could result in the S/H amplifiers being driven
into saturation, and they may not recover in time to accurately
acquire their next signal.
In normal operation, the output signal of the CCD is applied
simultaneously to the inputs (pins 3 and 4) of both S/H
amplifiers. S/H1 will normally be used to capture and hold
each pixel’s offset signal. Therefore, S/H1 is initially in its
signal-acquisition mode (logic "1" applied to pin 11, S/H1
COMMAND). This is also called the sample or track mode.
Following a brief interval during which the output of the CCD
and the output of S/H1 are allowed to settle, S/H1 is driven into
its hold mode by applying a logic "0" to pin 11. S/H1 is now
holding the pixel's offset value.
For example, S/H1 should not be commanded into the sample
mode until all transients associated with the opening of the
shunt switch have begun to decay. Similarly, S/H2 should not
be driven into the sample mode until all transients associated
with the clocking of pixel charge onto the output capacitor
have begun to decay. Therefore, it is generally not a good
practice to use the same clock edge to drive S/H1 into hold
(holding the offset) and S/H2 into sample (to acquire the offset
+ video signal).
In most straightforward configurations, the output of S/H1 is
connected to the summing node of S/H2 by connecting pin 7
(S/H1 ROUT) to pin 8 (S/H2 SUMMING NODE).
When the offset+video signal appears at the output of the CCD,
S/H2 is driven into its signal acquisition mode by applying a
logic "1" to pin 12 (S/H2 COMMAND).
S/H's that are in their signal-acquisition modes should be left
there as long as possible (so all signals can settle) and be
driven into their hold modes before any system transients
occur. In Figure 2, S/H1 is driven into the sample mode
shortly after the transient from the shunt switch has begun to
decay. S/H1 is then kept in the sample mode while the offset
signal and the S/H output settle. S/H1 is driven into hold just
prior to the system clock pulse(s) that transfers the next pixel
charge onto the output capacitor.
S/H2 employs a current-summing architecture that subtracts
the output of S/H1 (the offset) from the output of the CCD
(offset+video) while acquiring only the difference signal (i.e.,
the valid video). A logic "0" subsequently applied to pin 12
drives S/H2 into its hold mode, and after a brief transient
settling time, the valid video signal appears at pin 22 (V OUT).
(CCD OUTPUT)
ANALOG INPUT
FOR CDS
(Pins 3 and 4 are tied together)
OFFSET (N+1)
OFFSET (N+2)
OFFSET +
VIDEO (N+1)
OFFSET +
VIDEO (N+2)
100ns
S/H1
S/H2
100ns
30ns typ.
START CONVERT
35ns typ.
150ns
EOC
10ns min.
OUTPUT
DATA
DATA N VALID
DATA N-1 VALID
50ns max.
Figure 3. CDS-1402 in Front of DATEL's ADC-944 at fCLK = 4MHz
5
DATA N+1 VALID
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CDS-1402
As soon as the transients/noise associated with the charge
transport begins to decay, S/H2 can be driven into the sample
mode. S/H2 can then be left in the sample mode until just
before the reset pulse for the output capacitor.
sampling type, system timing should be such that the A/D's
input S/H amplifier is acquiring the output of the CDS-1402 at
the same time the output is settling to its final value.
For most sampling A/D's, the rising edge of the start-convert
pulse drives the internal S/H into the hold mode under the
assumption the S/H has already fully acquired and is tracking
the input signal. In this case, the same edge can not be used
to drive S/H2 into the hold mode and simultaneously initiate
the A/D conversion. The output of S/H2 needs time to settle its
sample-to-hold switching transient, and the input S/H of the
A/D needs time to fully acquire its new input signal.
In Figure 2, S/H's 1 and 2 both have the same acquisition time.
If the pixel-to-pixel amplitude variation of offset signals is much
less than that of video signals, it may not be necessary for the
allocated acquisition time of S/H1 to be as long as that of S/H2.
As shown in the plot (Figure 4) of acquisition times vs. input
signal step size, the S/H's internal to the CDS-1402 acquire
smaller-amplitude signals quicker than they acquire largeramplitude signals. In "maximum-throughput" applications,
assuming "asymmetric" timing can be accommodated, each
S/H should only be given the time it requires, and no more, to
acquire its input signal. Leaving a S/H amp in the sample
mode for a longer period of time has little added benefit.
As shown in Figure 1, output line A/D CLOCK1 (pin 18) is a
slightly delayed version of the signal applied to pin 11 (S/H1
COMMAND), and A/D CLOCK1 (pin 17) is its complement.
A/D CLOCK2 (pin 19) is a delayed version of the signal applied
to pin 12 (S/H2 COMMAND), and A/D CLOCK2 (pin 20) is its
complement. Any one of these signals, as appropriate, may be
used to trigger the A/D conversion.
As an example, the graph shows that it takes 32ns to acquire a
500mV step to within 10mV of accuracy and 73ns to acquire a
500mV step to within 0.5mV of accuracy. The figures in this
graph are typical values at room temperature.
Figure 3 is a typical timing diagram for a CDS-1402 in front of
DATEL's 14-bit, 5MHz sampling A/D, the ADS-944.
The CDS-1402 brings out 4 control lines that can be used to
trigger an A/D converter connected to its output. If the A/D is a
105
105
u
q
c
A
Acquisition Time (ns)
100
±0.5mV accuracy
95
95
90
90
85
80
1mV accuracy
±1mV accuracy
2mV accuracy
±2mV accuracy
5mV accuracy
±5mV accuracy
75
75
70
70
65
65
60
60
10mV accuracy
±10 mV accuracy
55
55
50
50
45
40
35
35
30
30
1
2
3
4
i
0
i
s
Input Step Size (Volts)
n
o
i
t
Figure 4. Acquisition Time versus Accuracy and Step Size
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CDS-1402
CALIBRATION PROCEDURE
Offset Adjust (Figure 5)
Offset and pedestal errors may be compensated for by
applying external voltages to pin 1 (OFFSET ADJUST V1) and/
or pin 9 (OFFSET ADJUST V2) using either voltage-output
DAC’s or potentiometers configured to appear as voltage
sources.
The sensitivity of the voltage offset adjustments is 5mV per Volt.
Pins 1 and 9 should be left open (floating) when not being used
for offset adjustment.
Gain Matching Adjustment (Differential Gain)
between S/H1 and S/H2
The user can adjust the gain matching (differential gain)
between S/H1 and S/H2 by leaving pin 7 (S/H1 ROUT) floating
(open) and connecting a 100 Ohm potentiometer between pin
6 (S/H1 OUT) and pin 8 (S/H2 SUMMING NODE). Note, offset
adjustment should take place before gain matching adjustment.
1. Connect pin 8 (S/H2 SUMMING NODE) either directly to pin
7 (S/H1 ROUT) or through a 100 Ohm potentiometer to pin
6 (S/H1 OUT).
2. Tie pins 3 (ANALOG INPUT 1) and 4 (ANALOG INPUT 2) to
pin 5 (ANALOG GROUND).
3. Adjust OFFSET ADJUST V1 (while S/H1 is in the hold
mode) until pin 6 (S/H1 OUT) equals 0V.
Apply a full-scale input to both pin 3 (ANALOG INPUT 1) and
pin 4 (ANALOG INPUT 2). Adjust the 100 Ohm potentiometer (with both S/H's in the sample mode) until pin 22
(V OUT) is 0V.
4. Adjust OFFSET ADJUST V2 (while S/H2 is in the hold
mode) until pin 22 (V OUT) equals 0V.
If gain matching adjustment is not required, leave pin 6 (S/H1
OUT) floating (open) and tie pin 7 (S/H1 ROUT) to pin 8 (S/H2
SUMMING NODE).
5. To negate the effect of output droop on the offset-adjust
process, each S/H must be continually switched between its
sample and hold modes and adjusted so its output equals
zero immediately after going into the hold mode.
+5V
1
OFFSET ADJUST V1
–5V
+5V ANALOG SUPPLY
24
+5V
0.1µF
+
2.2µF
0.1µF
+
2.2µF
CDS-1402
2
3
4
5
DO NOT CONNECT
ANALOG GROUND
23
22
ANALOG INPUT 1
V OUT
ANALOG INPUT 2
ANALOG GROUND
ANALOG GROUND
A/D CLOCK 2
21
20
19
A/D CLOCK 2
6
18
S/H1 OUT
7
100Ω
A/D CLOCK 1
S/H1 ROUT
A/D CLOCK 1
8
S/H2 SUMMING NODE
+5V DIGITAL SUPPLY
17
16
+5V
9
+5V
OFFSET ADJUST V2
DIGITAL GROUND
15
–5V
10
11
12
ANALOG GROUND
DO NOT CONNECT
14
S/H1 COMMAND
–5V ANALOG SUPPLY
S/H2 COMMAND
13
–5V
2.2µF
0.1µF
+
Figure 5. CDS-1402 Typical Connection Diagram
7
®
®
CDS-1402
MECHANICAL DIMENSIONS INCHES (mm)
1.31 MAX.
(33.27)
24-Pin DDIP
Versions
24
Dimension Tolerances (unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)
13
Lead Material: Kovar alloy
0.80 MAX.
(20.32)
1
Lead Finish: 50 microinches (minimum) gold plating
over 100 microinches (nominal) nickel plating
12
0.100 TYP.
(2.540)
1.100
(27.940)
0.235 MAX.
(5.969)
PIN 1 INDEX
0.200 MAX.
(5.080)
0.010
(0.254)
0.190 MAX.
(4.826)
0.100
(2.540)
SEATING
PLANE
0.025
(0.635)
0.040
(1.016)
0.018 ±0.002
(0.457)
+0.002
–0.001
0.600 ±0.010
(15.240)
0.100
(2.540)
1.31 MAX.
(33.02)
24-Pin
Surface Mount
Versions
Dimension Tolerances (unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)
13
24
Lead M aterial: Kovar alloy
0.80 MAX.
(20.32)
1
0.210 MAX.
(5.334)
Lead Finish: 50 microinches (minimum) gold plating
over 100 microinches (nominal) nickel plating
12
0.020 TYP.
(0.508)
0.060 TYP.
(1.524)
0.130 TYP.
(3.302)
PIN 1
INDEX
0.100
(2.540)
0.100 TYP.
(2.540)
0.020
(0.508)
0.015
(0.381)
MAX. radius
for any pin
0.010 TYP.
(0.254)
0.040
(1.016)
ORDERING INFORMATION
MODEL
OPERATING
TEMP. RANGE
24-PIN
PACKAGE
CDS-1402MC
CDS-1402MM
0 to +70°C
–55 to +125°C
DDIP
DDIP
ACCESSORIES
HS-24
Heat Sink for all CDS-1402 DDIP models
Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket),
24 required. For MIL-STD-883 product specifcation or availability of surface mount packaging, contact DATEL.
®
®
INNOVATION and EXCELLENCE
ISO 9001
R
E
G
I
S
T
E
R
E
D
DS-0345
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765
Fax: (508) 339-6356
Internet: www.datel.com E-mail:[email protected]
Data Sheet Fax Back: (508) 261-2857
08/96
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01
DATEL GmbH München, Germany Tel: 89-544334-0
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.