ETC KL5BUDV003

KL5BUDV003
USB2.0 to PCI BUS
General Description
The Kawasaki KL5KBUDV003 is a high performance device that transfers data between the USB2.0
high-speed BUS and the PCI 33MHz, 32 bit BUS. This 1 chip solution has USB 2.0 transceiver
embedded reducing space and cost. The KL5KBUDV003 is an ideal solution to convert a PCI device to a
USB2.0 Transceiver, HS_SIE USB2.0 Transceiver interface, 4 sets of high-speed bulk packet size
buffers, PCI interface and PCI master 2DMA channel support.
Features
•
33MHz PCI interface
•
•
USB 2.0 standard embedded transceiver.
•
30MHz USB 2.0 SIE BUS for High-Speed SIE
•
Up to 5 endpoints
operation
•
PCI interface for Target and Master (2
USB basic operation and transaction
control
•
Double packet buffer - 512x2 HS, 64Bx2 FS
•
Internal DMA operation between the High-Speed
•
Page and Descriptor DMA Modes
SIE and Double Buffer
•
USB data access by PCI target or DMA
•
High-Speed chirp protocol
•
0.18u Std cell technology
•
High-Speed/Full-Speed compatibility
•
Vdd = 3.3V, Ta = 0~70°C
DMA) modes
Block Diagram
KL5BUDV003
HS D+
USB 2.0 SIE to PCI interface
HS DRpu
RPU_EN
USB 2.0
Transceiver
SIE 16 b
PCI 32 b
HS_SIE
USB 2.0 D+
30 MHz
USB 2.0 D-
DBUF
PCI IF
Rs
33 MHz
Rs
Clock
Generator
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
1
KL5BUDV003
USB2.0 to PCI BUS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
GND
XOUT
XIN
VDD
misc8
misc7
misc6
GND
VDD18
misc5
misc4
misc3
misc2
misc1
VBDET
CKOUT
GND
VDD18
GND
VDD
GND
AD[0]
VDD
AD[1]
AD[2]
GND
AD[3]
GND
VDD18
AD[4]
GND
VDD
AD[5]
AD[6]
AD[7]
GND
Pin Diagram 144LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
KL5BUDV003
108 CBEN[0]
107 AD[8]
106 GND
105 VDD
104 AD[9]
103 AD[10]
102 AD[11]
101 GND
100 VDD18
99 GND
98 AD[12]
97 AD[13]
96 GND
95 VDD
94 AD[14]
93 AD[15]
92 GND
91 VDD18
90 GND
89 VDD
88 CBEN[1]
87 GND
86 PAR
85 STOPN
84 GND
83 VDD
82 DEVSELN
81 GND
80 VDD18
79 TRDYN
78 IRDYN
77 GND
76 FRAMEN
75 CBEN[2]
74 GND
73 VDD
GND
AD[31]
AD[30]
AD[29]
VDD
GND
AD[28]
VDD18
GND
AD[27]
GND
AD[26]
AD[25]
AD[24]
VDD
GND
VDD
GND
VDD18
GND
CBEN[3]
IDSEL
AD[23]
GND
AD[22]
AD[21]
AD[20]
VDD18
GND
VDD
GND
AD[19]
AD[18]
GND
AD[17]
AD[16]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P_MODE[0]
P_MODE[1]
P_MODE[2]
TESTI[0]
TESTI[1]
VDD18
GND
AVDD
GND
AVDD
GND
REXT
RPU_ENA
AVDD
GND
GND
FSDP
HSDP
HSDM
FSDM
GND
GND
AVDD
VDD
GND
VDD18
GND
TESTI[2]
TESTI[3]
VDD
GND
INTAN
RSTN
CLK
GNTN
REQN
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
2
KL5BUDV003
USB2.0 to PCI BUS
Logical Pin Out
Current Consumption
USB
PCI BUS
AD[31:0]
Operating conditions:VBDET
input clock = 48MHz±50ppm, Vdd = 3.3V±0.3V, Ta
= 0~70°C
CBEN[3:0]
REXT
PAR
Operation
High Speed
HSDP
Full
operation
IDSEL
120mA
HSDM
FRAMEN
Idle
Stand-by
RPU ENA
FSDP
70mA
KL5BUDV003
DEVSELN
IRDYN
200µA
TRDYN
STOPN
FSDM
XIN
REQN
XOUT
GNTN
CKOUT
INTAN
RSTN
CLK
Misc BUS
PMODE[2:0]
TEST[3:0]
misc[1:2}
misc[7:3}
misc[8]
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
3
KL5BUDV003
USB2.0 to PCI BUS
Pin Description (PCI Mode)
Pin #
QFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
I/O
Pin Name
I
I
I
I
I
------O
O
---I/O
I/O
I/O
I/O
-------I
I
--O
I
I
I
O
-I/O
I/O
I/O
--I/O
--I/O
--
P_MODE[0]
P_MODE[1]
P_MODE[2]
TEST[0]
TEST[1]
VDD18
GND
AVDD
GND
AVDD
GND
REXT
RPU_ENA
AVDD
GND
GND
FSDP
HSDP
HSDM
FSDM
GND
GND
AVDD
VDD
GND
VDD18
GND
TEST[2]
TEST[3]
VDD
GND
INTAN
RSTN
CLK
GNTN
REQN
GND
AD[31]
AD[30]
AD[29]
VDD
GND
AD[28]
VDD18
GND
AD[27]
GND
Description
Burst Length select flag
Burst Length select flag
Burst Length select flag
LSI shipment test input and mode pin
LSI shipment test input and mode pin
1.8V power pin
Ground
3.3V power pin
Ground
3.3V power pin
Ground
USB100uA fixed reference bias current pin
USB External pull up resistor source drive pin
3.3V power pin
Ground
Ground
USB FS_XVR DP pin
USB HS_XVR DP pin
USB HS_XVR DM pin
USB FS_XVR DM pin
Ground
Ground
3.3V power pin
3.3V power pin
Ground
1.8V power pin
Ground
LSI shipment test input and mode pin
LSI shipment test input and mode pin
3.3V power pin
Ground
PCI interrupt signal
PCI bus asynchronous reset input
PCI clock input
PCI bus grant signal
PCI bus request signal
Ground
PCI address data bus
PCI address data bus
PCI address data bus
3.3V power pin
Ground
PCI address data bus
1.8V power pin
Ground
PCI address data bus
Ground
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
4
KL5BUDV003
USB2.0 to PCI BUS
Pin #
QFP
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
I/O
Pin Name
I/O
I/O
I/O
------I/O
I
I/O
-I/O
I/O
I/O
----I/O
I/O
-I/O
I/O
--I/O
I/O
-I/O
I/O
--I/O
--I/O
I/O
-I/O
----I/O
I/O
--I/O
I/O
AD[26]
AD[25]
AD[24]
VDD
GND
VDD
GND
VDD18
GND
CBEN[3]
IDSEL
AD[23]
GND
AD[22]
AD[21]
AD[20]
VDD18
GND
VDD
GND
AD[19]
AD[18]
GND
AD[17]
AD[16]
VDD
GND
CBEN[2]
FRAMEN
GND
IRDYN
TRDYN
VDD18
GND
DEVSELN
VDD
GND
STOPN
PAR
GND
CBEN[1]
VDD
GND
VDD18
GND
AD[15]
AD[14]
VDD
GND
AD[13]
AD[12]
Description
PCI address data bus
PCI address data bus
PCI address data bus
3.3V power pin
Ground
3.3V power pin
Ground
1.8V power pin
Ground
Bus command byte enable signal
Device-select signal during configuration
PCI address data bus
Ground
PCI address data bus
PCI address data bus
PCI address data bus
1.8V power pin
Ground
3.3V power pin
Ground
PCI address data bus
PCI address data bus
Ground
PCI address data bus
PCI address data bus
3.3V power pin
Ground
Bus command byte enable signal
Cycle-frame signal
Ground
Initiator RDY signal
Target RDY signal
1.8V power pin
Ground
Device-select signal
3.3V power pin
Ground
Target termination signal
Even parity flag
3.3V power pin
Bus command byte enable signal
3.3V power pin
Ground
1.8V power pin
Ground
PCI address data bus
PCI address data bus
3.3V power pin
Ground
PCI address data bus
PCI address data bus
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
5
KL5BUDV003
USB2.0 to PCI BUS
Pin #
QFP
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
I/O
Pin Name
---I/O
I/O
I/O
--I/O
I/O
-I/O
I/O
I/O
--I/O
--I/O
-I/O
I/O
-I/O
-----O
I
I
I
I/O
I/O
I/O
--I/O
I/O
O
-I
O
--
GND
VDD18
GND
AD[11]
AD[10]
AD[9]
VDD
GND
AD[8]
CBEN[0]
GND
AD[7]
AD[6]
AD[5]
VDD
GND
AD[4]
VDD18
GND
AD[3]
GND
AD[2]
AD[1]
VDD
AD[0]
GND
VDD
GND
VDD18
GND
CKOUT
VBDET
misc1
misc2
misc3
misc4
misc5
VDD18
GND
misc6
misc7
misc8
VDD
XIN
XOUT
GND
Description
Ground
1.8V power pin
Ground
PCI address data bus
PCI address data bus
PCI address data bus
3.3V power pin
Ground
PCI address data bus
Bus command byte enable signal
Ground
PCI address data bus
PCI address data bus
PCI address data bus
3.3V power pin
Ground
PCI address data bus
1.8V power pin
Ground
PCI address data bus
Ground
PCI address data bus
PCI address data bus
3.3V power pin
PCI address data bus
Ground
3.3V power pin
Ground
1.8V power pin
Ground
USB CKOUT pin
USB Vbus level detect pin
LSI shipment test pin
LSI shipment test pin
LSI shipment test pin
LSI shipment test pin
LSI shipment test pin
1.8V power pin
Ground
LSI shipment test pin
LSI shipment test pin
LSI shipment test pin
3.3V power pin
USB Connect to external crystal oscillator
USB Connect to external crystal oscillator
Ground
Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the
information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice
form Kawasaki LSI
July 2002 • Copyright 2002 • Kawasaki LSI • Printed in U.S.A
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
Ver. 2.0
6