ETC ISD2560PI

®
ISD2500 Series
Single-Chip Voice Record/Playback Devices
32-*, 40-*, 48-*, 64-*, 60-, 75-,
90-, and 120-Second Durations
FEATURES
•
•
•
•
•
•
•
Easy-to-use single-chip voice Record/
Playback solution
High-quality, natural voice/audio
reproduction
Manual switch or microcontroller compatible Playback can be edge- or levelactivated
Single-chip durations of 32*, 40*, 48*, 64*,
60, 75, 90, and 120 seconds
Directly cascadable for longer durations
Automatic Power-Down (Push-Button
Mode)
– Standby current 1 µA (typical)
•
•
•
•
•
•
•
•
Fully addressable to handle multiple
messages
100-year message retention (typical)
100,000 record cycles (typical)
On-chip clock source
No algorithm development required
Single +5 volt power supply
Available in die form, DIP, SOIC, and
TSOP packaging
Industrial temperature (-40°C to +85°C)
versions available
1
Zero-power message storage
– Eliminates battery backup circuits
ISD2500 SERIES SUMMARY
Part
Number
Duration
(Seconds)
Input Sample
Rate (KHz)
Typical Filter
Pass Band (KHz)
ISD2560
60
8.0
3.4
ISD2575
75
6.4
2.7
ISD2590
90
5.3
2.3
ISD25120
120
4.0
1.7
ISD2532*
32
8.0
3.4
ISD2540*
40
6.4
2.7
ISD2548*
48
5.3
2.3
ISD2564*
64
4.0
1.7
Information Storage Devices, Inc.
*
Advance information: ISD2532/40/48/64 devices.
1–79
ISD2500 Series
GENERAL DESCRIPTION
DETAILED DESCRIPTION
Information Storage Devices' ISD2500 ChipCorder® Series provides high-quality, single-chip
Record/Playback solutions for 32- to 120-second
messaging applications. The CMOS devices
include an on-chip oscillator, microphone preamplifier, automatic gain control, antialiasing filter,
smoothing filter, speaker amplifier, and high density multi-level storage array. In addition, the
ISD2500 is microcontroller compatible, allowing
complex messaging and addressing to be
achieved.
Speech/Sound Quality
Recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage.
This unique, single-chip solution is made possible
through ISD's patented multilevel storage technology. Voice and audio signals are stored directly
into memory in their natural form, providing highquality, solid-state voice reproduction.
The speech samples are stored directly into onchip nonvolatile memory without the digitization
and compression associated with other solutions.
Direct analog storage provides a very true, natural
sounding reproduction of voice, music, tones, and
sound effects not available with most solid-state
digital solutions.
The ISD2500 Series includes devices offered at
4.0, 5.3, 6.4, and 8.0 KHz sampling frequencies,
allowing the user a choice of speech quality
options. Increasing the duration within a product
series decreases the sampling frequency and
bandwidth, which affects sound quality. Please
refer to the ISD2500 Series Summary table on
page 1-79 to compare filter pass band and product
durations.
Duration
To meet end system requirements, the ISD2500
Series offers single-chip solutions at 32*, 40*, 48*,
64*, 60, 75, 90, and 120 seconds. Parts may also
be cascaded together for longer durations.
ISD2560/75/90/120 DEVICE BLOCK DIAGRAM
Internal Clock
Timing
XCLK
Sampling Clock
Amp
ANA IN
ANA OUT
MIC
PreAmp
MIC REF
Analog Transceivers
480 K Cell
Nonvolatile
Multilevel Storage
Array
5-Pole Active
Smoothing Filter
SP+
Mux
Automatic
Gain Control
(AGC)
AGC
Power Conditioning
VCCA VSSA VSSD VCCD
1–80
R
5-Pole Active
Antialiasing Filter
Decoders
-1
Product Data Sheets
*
Amp
SP–
Address Buffers
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
Advance information: ISD2532/40/48/64 devices.
Device Control
PD OVF P/R
CE EOM AUX IN
ISD2500 Series
Product Data Sheets
ISD2532/40/48/64* DEVICE BLOCK DIAGRAM
Internal Clock
Timing
XCLK
Sampling Clock
5-Pole Active
Antialiasing Filter
ANA OUT
MIC
PreAmp
MIC REF
R
Analog Transceivers
Decoders
Amp
ANA IN
256 K Cell
Nonvolatile
Multilevel Storage
Array
5-Pole Active
Smoothing Filter
SP+
Mux
Automatic
Gain Control
(AGC)
AGC
Power Conditioning
VCCA VSSA VSSD VCCD
Amp
SP–
Address Buffers
A0 A1 A2 A3 A4 A5
EEPROM Storage
One of the benefits of ISD’s ChipCorder technology is the use of on-chip nonvolatile memory,
providing zero-power message storage. The message is retained for up to 100 years typically
without power. In addition, the device can be rerecorded typically over 100,000 times.
Microcontroller Interface
In addition to its simplicity and ease of use, the
ISD2500 Series includes all the interfaces necessary for microcontroller-driven applications. The
address and control lines can be interfaced to a
microcontroller and manipulated to perform a variety of tasks, including message assembly,
message concatenation, predefined fixed message segmentation, and message management.
Device Control
A6 A7
A8
PD OVF P/R
CE EOM AUX IN
1
PIN DESCRIPTIONS
Voltage Inputs (VCCA, VCCD)
To minimize noise, the analog and digital circuits in
the ISD2500 Series devices use separate power
busses. These voltage busses are brought out to
separate pins and should be tied together as close
to the supply as possible. In addition, these supplies should be decoupled as close to the package
as possible.
Ground Inputs (VSSA, VSSD)
The ISD2500 Series of devices utilizes separate
analog and digital ground busses. These pins
should be connected separately through a lowimpedance path to power supply ground.
Power Down Input (PD)
Programming
The ISD2500 Series is also ideal for playback-only
applications, where single or multiple messages
are referenced through buttons, switches, or a
microcontroller. Once the desired message configuration is created, duplicates can easily be
generated via an ISD programmer.
When not recording or playing back, the PD pin
should be pulled HIGH to place the part in a very
low power mode (see ISB specification). When
OVF pulses LOW for an overflow condition, PD
should be brought HIGH to reset the address
pointer back to the beginning of the Record/Playback space. The PD pin has additional
functionality in the M6 (Push-Button) Operational
*
Advance information: ISD2532/40/48/64 devices.
1–81
ISD2500 Series
Product Data Sheets
ISD2560/75/90/120 DEVICE PINOUTS
OVF
CE
PD
EOM
XCLK
P/R
VCCD
NC
NC
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ISD2560/75/90/120
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ANA OUT
ANA IN
AGC
MIC REF
MIC
VCCA
SP–
NC
NC
SP+
VSSA
VSSD
AUX IN
A9
A8
A7
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
A7
A8
A9
AUX IN
VSSD
VSSA
SP+
TSOP
Mode described later in the Operational Mode
section.
-1
Chip Enable Input (CE)
The CE pin is taken LOW to enable all Playback
and Record operations. The address inputs and
Playback/Record input (P/R) are latched by the
falling edge of CE. CE has additional functionality
in the M6 (Push-Button) Operational Mode
described later in the Operational Mode section.
Playback/Record Input (P/R)
The P/R input is latched by the falling edge of the
CE pin. A HIGH level selects a Playback cycle
while a LOW level selects a Record cycle. For a
Record cycle, the address inputs provide the starting address and recording continues until PD or
CE is pulled HIGH or an overflow is detected (i.e.
the chip is full). When a Record cycle is terminated
by pulling PD or CE HIGH, an End-Of-Message
(EOM) marker is stored at the current address in
memory. For a Playback cycle, the address inputs
provide the starting address and the device will
play until an EOM marker is encountered. The
device can continue past an EOM marker in an
operational mode, or if CE is held LOW in address
mode. (See page 1-85 for more Operational
Modes).
1–82
*
Advance information: ISD2532/40/48/64 devices.
1
28
2
27
3
26
4
25
5
24
6
ISD2560
7 ISD2575
8 ISD2590
9 ISD25120
23
10
19
11
18
12
17
13
16
22
21
20
15
14
VCCD
P/R
XCLK
EOM
PD
CE
OVF
ANA OUT
ANA IN
AGC
MIC REF
MIC
VCCA
SP–
DIP/SOIC
End-Of-Message / RUN Output (EOM)
A nonvolatile marker is automatically inserted at
the end of each recorded message. It remains
there until the message is recorded over. The
EOM output pulses LOW for a period of TEOM at
the end of each message.
In addition, the ISD2500 Series has an internal
VCC detect circuit to maintain message integrity
should VCC fall below 3.5V. In this case, EOM
goes LOW and the device is fixed in Playback-only
mode.
When the device is configured in Operational
Mode M6 (Push-Button Mode), this pin provides an
active-HIGH RUN signal, indicating the device is
currently recording or playing. This signal can conveniently drive an LED for a visual indicator of a
Record or Playback operation in process.
Overflow Output (OVF)
This signal pulses LOW at the end of memory
space, indicating the device has been filled and the
message has overflowed. The OVF output then follows the CE input until a PD pulse has reset the
device. This pin can be used to cascade several
ISD2500 devices together to increase Record/
Playback durations.
ISD2500 Series
Product Data Sheets
ISD2532/40/48/64* DEVICE PINOUTS
OVF
CE
PD
EOM
XCLK
P/R
VCCD
NC
NC
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ISD2532/40/48/64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ANA OUT
ANA IN
AGC
MIC REF
MIC
VCCA
SP–
NC
NC
SP+
VSSA
VSSD
AUX IN
A8
A7
NC
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
NC
A7
A8
AUX IN
VSSD
VSSA
SP+
1
28
2
27
3
26
4
25
6
7
8
9
The microphone input transfers its signal to the onchip preamplifier. An on-chip Automatic Gain Control (AGC) circuit controls the gain of this
preamplifier from -15 to 24 dB. An external microphone should be AC coupled to this pin via a series
capacitor. The capacitor value, together with the
internal 10 K ohm resistance on this pin, determines the low-frequency cutoff for the ISD2500
Series passband. See ISD's Application Notes and
Design Manual in this book for additional information on low-frequency cutoff calculation.
ISD2532
ISD2540
ISD2548
ISD2564
23
22
21
20
10
19
11
18
12
17
13
16
15
14
TSOP
Microphone Input (MIC)
24
5
VCCD
P/R
XCLK
EOM
PD
CE
OVF
ANA OUT
ANA IN
AGC
MIC REF
MIC
VCCA
SP–
DIP/SOIC
AGC pin to VSSA analog ground. The “release”
time is determined by the time constant of an
external resistor (R2) and an external capacitor
(C2) connected in parallel between the AGC Pin
and VSSA analog ground. Nominal values of
470 KΩ and 4.7 µF give satisfactory results in
most cases.
Analog Output (ANA OUT)
This pin provides the preamplifier output to the
user. The voltage gain of the preamplifier is determined by the voltage level at the AGC pin.
Microphone Reference Input (MIC REF)
Analog Input (ANA IN)
The MIC REF input is the inverting input to the
microphone preamplifier. This provides a noisecanceling or common-mode rejection input to the
device when connected to a differential
microphone.
The analog input pin transfers its signal to the chip
for recording. For microphone inputs, the ANA
OUT pin should be connected via an external
capacitor to the ANA IN pin. This capacitor value,
together with the 3.0 KΩ input impedance of ANA
IN, is selected to give additional cutoff at the lowfrequency end of the voice passband. If the
desired input is derived from a source other than a
microphone, the signal can be fed, capacitively
coupled, into the ANA IN pin directly.
Automatic Gain Control Input (AGC)
The AGC dynamically adjusts the gain of the
preamplifier to compensate for the wide range of
microphone input levels. The AGC allows the full
range of whispers to loud sounds to be recorded
with minimal distortion. The “attack” time is determined by the time constant of a 5 KΩ internal
resistance and an external capacitor (C2 on the
schematic on page 1-100) connected from the
External Clock Input (XCLK)
The external clock input for the ISD2500 devices
has an internal pull-down device. These devices
are configured at the factory with an internal sampling clock frequency centered to ± 1% of
*
Advance information: ISD2532/40/48/64 devices.
1–83
1
ISD2500 Series
Product Data Sheets
specification. The frequency is then maintained to
a variation of ± 2.25% over the entire commercial
temperature and operating voltage ranges. The
internal clock has a ± 5% tolerance over the industrial temperature and voltage range. A regulated
power supply is recommended for industrial temperature range parts. If greater precision is
required, the device can be clocked through the
XCLK pin as follows:
Part
Number
-1
Sample Rate
Required Clock
ISD2560
8.0 KHz
1024 KHz
ISD2575
6.4 KHz
819.2 KHz
ISD2590
5.3 KHz
682.7 KHz
ISD25120
4.0 KHz
512 KHz
ISD2532*
8.0 KHz
1024 KHz
ISD2540*
6.4 KHz
819.2 KHz
ISD2548*
5.3 KHz
682.7 KHz
ISD2564*
4.0 KHz
512 KHz
These recommended clock rates should not be
varied because the antialiasing and smoothing filters are fixed, and aliasing problems can occur if
the sample rate differs from the one recommended. The duty cycle on the input clock is not
critical, as the clock is immediately divided by two.
IF THE XCLK IS NOT USED, THIS INPUT MUST BE CONNECTED TO GROUND.
Speaker Outputs (SP+/SP-)
All devices in the ISD2500 Series include an onchip differential speaker driver, capable of driving
50 milliwatts into 16 Ω from AUX IN (12.2 mW from
memory).
The speaker outputs are held at VSSA levels during
record and power down. It is therefore not possible
to parallel speaker outputs of multiple ISD2500
devices or the outputs of other speaker drivers.
1–84
*
Advance information: ISD2532/40/48/64 devices.
NOTE
Connection of speaker outputs in parallel
may cause damage to the device.
A single output may be used alone (including a
coupling capacitor between the SP pin and the
speaker). These outputs may be used individually
with the output signal taken from either pin. Using
the differential outputs results in a 4:1 improvement in output power.
NOTE
Never ground or drive an unused speaker
output.
Auxiliary Input (AUX IN)
The Auxiliary Input is multiplexed through to the
output amplifier and speaker output pins when CE
is HIGH, P/R is HIGH, and Playback is currently
not active or if the device is in Playback overflow.
When cascading multiple ISD2500 devices, the
AUX IN pin is used to connect a Playback signal
from a following device to the previous output
speaker drivers. For noise considerations, it is suggested that the auxiliary input not be driven when
the storage array is active.
Address/Mode Inputs (Ax/Mx)
The Address/Mode Inputs have two functions
depending on the level of the two Most Significant
Bits (MSB) of the address (A8 and A9 for the
ISD256075/90/120 devices, and A7 and A8 for the
ISD2532/40/48/64* devices).
If either or both of the two MSBs are LOW, the
inputs are ALL interpreted as address bits and are
used as the start address for the current Record or
Playback cycle. The address pins are inputs only
and do not output internal address information as
the operation progresses. Address inputs are
latched by the falling edge of CE.
If both MSBs are HIGH, the Address/Mode Inputs
are interpreted as Mode bits according to the
Operational Mode table on page 1-85. There are
six operational modes (M0..M6) available as indi-
ISD2500 Series
Product Data Sheets
OPERATIONAL MODES TABLE
Mode
Control
Function
Typical Use
Jointly Compatible*
M0
Message cueing
Fast-forward through messages
M4, M5, M6
M1
Delete EOM markers
Position EOM marker at the end of the last
message
M3, M4, M5, M6
M2
Not applicable
Reserved
N/A
M3
Looping
Continuous playback from Address 0
M1, M5, M6
M4
Consecutive addressing
Record/Play multiple consecutive
messages
M0, M1, M5
M5
CE level-activated
Allows message pausing
M0, M1, M3, M4
M6
Push-button control
Simplified device interface
M0, M1, M3
1
NOTE: An asterisk (*) indicates additional operational modes which can be used simultaneously with the given mode.
cated in the table. It is possible to use multiple
operational modes simultaneously. Operational
Modes are sampled on each falling edge of CE,
and thus Operational Modes and direct addressing
are mutually exclusive.
OPERATIONAL MODES
The ISD2500 Series is designed with several builtin operational modes that provide maximum functionality with minimum additional components.
These are described in detail below. The operational modes use the address pins on the ISD2500
devices, but are mapped outside the valid address
range. When the two Most Significant Bits (MSBs)
are HIGH (A8 and A9 for the ISD2560/75/90/120
devices, and A7 and A8 for the ISD2532/40/48/64*
devices), the remaining address signals are interpreted as mode bits and not as address bits.
Therefore, operational modes and direct addressing are not compatible and cannot be used
simultaneously.
There are two important considerations for using
operational modes. First, all operations begin initially at address 0, which is the beginning of the
ISD2500 address space. Later operations can
begin at other address locations, depending on the
operational mode(s) chosen. In addition, the
address pointer is reset to 0 when the device is
changed from Record to Playback, Playback to
Record (except M6 mode), or when a Power-Down
cycle is executed.
Second, Operational Modes are executed when
CE goes LOW and the two MSBs are HIGH. This
Operational Mode remains in effect until the next
LOW-going CE signal, at which point the current
address/mode levels are sampled and executed.
OPERATIONAL MODES DESCRIPTION
The Operational Modes can be used in conjunction
with a microcontroller, or they can be hard-wired to
provide the desired system operation.
M0 — Message Cueing
Message Cueing allows the user to skip through
messages, without knowing the actual physical
addresses of each message. Each CE LOW pulse
causes the internal address pointer to skip to the
next message. This mode should be used for
*
Advance information: ISD2532/40/48/64 devices.
1–85
ISD2500 Series
Playback only, and is typically used with the M4
Operational Mode.
M1 — Delete EOM Markers
The M1 Operational Mode allows sequentially
recorded messages to be combined into a single
message with only one EOM marker set at the end
of the final message. When this operational mode
is configured, messages recorded sequentially are
played back as one continuous message.
M2 — Unused
When operational modes are selected, the M2 pin
should be LOW.
M3 — Message Looping
-1
The M3 Operational Mode allows for the automatic, continuously repeated playback of the
message located at the beginning of the address
space. A message CAN completely fill the ISD2500
device and will loop from beginning to end without
OVF going LOW.
M4 — Consecutive Addressing
During normal operations, the address pointer will
reset when a message is played through to an
EOM marker. The M4 Operational Mode inhibits
the address pointer reset on EOM, allowing messages to be played back consecutively.
M5 — CE-Level Activated
The default mode for ISD2500 devices is for CE to
be edge-activated on Playback and level-activated
on Record. The M5 Operational Mode causes the
CE pin to be interpreted as level-activated as
opposed to edge-activated during Playback. This
is specifically useful for terminating Playback operations using the CE signal.
In this mode, CE LOW begins a Playback cycle, at
the beginning of the device memory. The Playback
cycle continues as long as CE is held LOW. When
CE goes HIGH, Playback will immediately end. A
new CE LOW will restart the message from the
beginning unless M4 is also HIGH.
1–86
*
Advance information: ISD2532/40/48/64 devices.
Product Data Sheets
M6 — Push-Button Mode
The ISD2500 Series of devices contain a PushButton operational mode. The Push-Button mode
is used primarily in very low-cost applications and
is designed to minimize external circuitry and components, thereby reducing system cost. In order to
configure the device in Push-Button operational
mode, the two most significant address bits must
be HIGH, and the M6 mode pin must also be
HIGH. A device in this mode always powers down
at the end of each Playback or Record
cycle after CE goes HIGH.
When this operational mode is implemented, several of the pins on the device have alternate
functionality:
Pin Name
Alternate Functionality in
Push-Button Mode
CE
Start/Pause Push-Button
(LOW pulse-activated)
PD
Stop/Reset Push-Button
(HIGH pulse activated)
EOM
Active-HIGH Run Indicator
CE Pin (START/PAUSE)
In Push-Button Operational Mode, CE acts as a
LOW-going pulse-activated START/PAUSE signal. If no operation is currently in progress, a LOWgoing pulse on this signal will initiate a Playback or
a Record cycle according to the level on the P/R
pin. A subsequent pulse on the CE pin, before an
End-Of-Message is reached in Playback or an
overflow condition occurs, will cause the device to
pause. The address counter is not reset, and
another CE pulse will cause the device to continue
the operation from the place where it was paused.
PD Pin (STOP/RESET)
In push-button Operational Mode, PD acts as a
HIGH-going pulse-activated STOP/RESET signal.
When a Playback or Record cycle is in progress
and a HIGH-going pulse is observed on PD, the
ISD2500 Series
Product Data Sheets
Playback in Push-Button Mode
current cycle is terminated and the address pointer
is reset to address 0, the beginning of the message
space.
1. The PD pin should be LOW.
2. The P/R pin is taken HIGH.
EOM Pin (RUN)
3. The CE pin is pulsed LOW. Playback starts,
EOM goes HIGH to indicate an operation in
progress.
In Push-Button Operational Mode, EOM becomes
an active-HIGH RUN signal which can be used to
drive an LED or other external device. It is HIGH
whenever a Record or Playback operation is in
progress.
4. If the CE pin is pulsed LOW or an EOM
marker is encountered during an operation,
the part will pause. The internal address
pointers are not cleared, and EOM goes
back LOW. The P/R pin may be changed at
this time. A subsequent Record operation
would not reset the address pointers and
the recording would begin where Playback
ended.
Recording in Push-Button Mode
1. The PD pin should be LOW, usually using a
pulldown resistor.
2. The P/R pin is taken LOW.
3. The CE pin is pulsed LOW. Recording
starts, EOM goes HIGH to indicate an operation in progress.
5. CE is again pulsed LOW. Playback starts
where it left off, with EOM going HIGH to
indicate an operation in progress.
4. The CE pin is pulsed LOW. Recording
pauses, EOM goes back LOW. The internal
address pointers are not cleared, but an
EOM marker is stored in memory to point to
the message end. The P/R pin may be
taken HIGH at this time. Any subsequent
CE would start a playback at address 0.
5. The CE pin is pulsed LOW. Recording
starts at the next address after the previous
set EOM marker. EOM goes back HIGH.
6. Playback continues as in steps 4 and 5 until
PD is pulsed HIGH or overflow occurs.
7. If in overflow, pulling CE LOW will reset the
address pointer and start Playback from the
beginning. After a PD pulse, the part is reset
to address 0.
NOTE
Push-button mode can be used in conjunction with modes M0, M1, and M3.
NOTE
If the M1 operational mode pin is also
HIGH, the just previously written EOM bit
is erased, and recording starts at that
address.)
6. When the recording sequences are finished, the final CE pulse LOW will end the
last Record cycle, leaving a set EOM
marker at the message end. Recording may
also be terminated by a HIGH level on PD,
which will leave a set EOM marker.
Good Audio Design Practices
ISD products are very high-quality single-chip
voice Recording and Playback systems. To ensure
the highest quality voice reproduction, it is important that good audio design practices on layout and
power supply decoupling be followed. See the ISD
Application Notes and Design Manual in this book
for details.
*
Advance information: ISD2532/40/48/64 devices.
1–87
1
ISD2500 Series
ISD1000A COMPATIBILITY
Push-Button Mode
The ISD2500 Series of devices is designed to provide upward compatibility with the ISD1000A
family. When designing with the ISD2500 Series,
the following differences should be noted.
The ISD2500 Series includes an additional Operational Mode called Push-Button mode. This
provides an alternative interface to the Record and
Playback functions of the part. The CE and PD
pins become redefined as edge-activated “pushbuttons.” A pulse on CE initiates a cycle, and if
triggered again, pauses the current cycle without
resetting the address pointer (i.e., a Start or Pause
function). PD stops any current cycle and resets
the address pointer to the beginning of the message space (i.e., a Stop and Reset function).
Additionally, the EOM pin functions as an activeHIGH run indicator, and can be used to drive an
LED indicating a Record or Playback operation is
in progress. Devices in the Push-Button mode cannot be cascaded.
Addressing
-1
Product Data Sheets
The ISD2560/75/90/120 devices have 480K storage cells designed to provide 60 seconds of
storage at a sampling rate of 8.0 KHz. This is
approximately four times the storage of the
ISD1000A family. To enable the same addressing
resolution, two additional address pins have been
added. The address space of each device is divisible into 300 increments with valid addressing from
00 to 13F Hex. Some higher addresses are
mapped into the Operational Modes. All other
addresses are invalid.
The ISD2532/40/48/64 devices have 256K storage
cells designed to provide 32 seconds of storage at
a sampling rate of 8.0 KHz. This is twice the
amount of storage of the ISD1000A family. To
enable the same addressing resolution, one additional address pin has been added. The address
space of each device is divisable into 320 increments with valid addressing from 00 to 13F Hex.
Overflow
The ISD1000A Series combined two functions on
the EOM pin: end-of-message indication and overflow. The ISD2500 separates these two functions.
Pin 25 (PDIP package) remains as EOM, but outputs only the EOM signal indication. Pin 22 (PDIP
package) becomes OVF and pulses LOW only
when the device reaches its end of memory, or is
“full.” This change allows easy message cueing
and addressability across device boundaries. This
also means that the M2 operational mode found in
the ISD1000A family is not implemented in the
ISD2500 Series.
1–88
*
Advance information: ISD2532/40/48/64 devices.
Looping Mode
The ISD2500 Series can loop with a message that
completely fills the memory space.
NOTE
Additional descriptions of ISD2500 device
functionality and application examples are
provided in the ISD Application Notes and
Design Manual in this book.
ISD2500 Series
Product Data Sheets
TIMING DIAGRAMS
Record
TCE
CE
TSET
Don't Care
P/R
T PDH
THOLD
PD
Don't Care
A0-A9
Don't Care
TPDS TPDR
Don't Care
TSET
MIC
ANA IN
TPUD
TOVF
OVF
1
Playback
TCE
CE
TSET
Don't Care
P/R
T PDH
THOLD
PD
Don't Care
A0-A9
Don't Care
TPDS
TPDP
Don't Care
TSET
SP+/–
TOVF
OVF
EOM
TEOM
TPUD
*
Advance information: ISD2532/40/48/64 devices.
1–89
ISD2500 Series
Product Data Sheets
OPERATING CONDITIONS
(PACKAGED PARTS)
ABSOLUTE MAXIMUM RATINGS
(PACKAGED PARTS)
Condition
Condition
Value
Junction temperature
Commercial operating
150° C
Storage temperature range
–65° C to +150° C
Voltage applied to any pin
(VSS – 0.3 V) to
(VCC + 0.3 V)
Voltage applied to any pin
(Input current limited to ±20 mA)
(VSS – 1.0 V) to
(VCC + 1.0 V)
Lead temperature (soldering –
10 seconds)
300° C
VCC - VSS
– 0.3 V to + 7.0 V
NOTE:
-1
Value
0° C to +70° C
temperature range(1)
–40° C to +85° C
Industrial operating
temperature range(1)
Supply voltage (VCC)(2)
+4.5 V to +5.5 V
Ground voltage (VSS)(3)
0V
NOTES:
1. Case temperature.
2. VCC = VCCA = VCCD.
3. VSS = VSSA = VSSD.
Typ (1)
Max(2)
Units
0.8
V
Stresses above those listed may cause permanent
damage to the device. Exposure to the absolute
maximum ratings may affect device reliability.
Functional operation is not implied at these
conditions.
DC PARAMETERS (PACKAGED PARTS)
Symbol
Parameters
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VOH1
Min(2)
2.0
Conditions
V
V
IOL = 4.0 mA
VCC–0.4
V
IOH = – 10 µA
OVF Output High Voltage
2.4
V
IOH = – 1.6 mA
VOH2
EOM Output High Voltage
VCC–1.0
V
IOH = – 3.2 mA
ICC
VCC Current (Operating)
25
30
mA
REXT = ∞ (3)
ISB
VCC Current (Standby)
1
10
µA
(3)
IIL
Input Leakage Current
+1
µA
IILPD
Input Current HIGH w/Pull
Down
130
µA
Force VCC (4)
REXT
Output Load Impedance
16
Ω
Speaker Load
RMIC
Preamp In Input Resistance
4
9
15
KΩ
RAUX
AUX INPUT Resistance
5
11
20
KΩ
1–90
*
0.4
Advance information: ISD2532/40/48/64 devices.
VCC–0.8
MIC and MIC REF Pins
ISD2500 Series
Product Data Sheets
DC PARAMETERS (PACKAGED PARTS) – CONTINUED
Symbol
Parameters
Min(2)
Typ (1)
Max(2)
Units
Conditions
RANA IN
ANA IN Input Resistance
2.3
3
5
KΩ
APRE1
Preamp Gain 1
21
24
26
dB
AGC = 0.0 V
APRE2
Preamp Gain 2
–15
5
dB
AGC = 2.5 V
AAUX
AUX IN/SP+ Gain
0.98
1.0
V/V
AARP
ANA IN to SP+/- Gain
21
23
26
dB
RAGC
AGC Output Resistance
2.5
5
9.5
KΩ
NOTES:
1. Typical values @ TA = 25° C and 5.0 V.
2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. VCCA and VCCD connected together.
4. XCLK pin only.
1
AC PARAMETERS (PACKAGED PARTS)
Symbol
FS
FCF
Characteristic
Sampling
Frequency
Filter Pass Band
Min(2)
Typ (1)
Max(2)
Units
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
8.0
6.4
5.3
4.0
8.0
6.4
5.3
4.0
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
— ISD2532*
3.4
KHz
— ISD2540*
2.7
KHz
— ISD2548*
2.3
KHz
— ISD2564*
1.7
KHz
— ISD2560
3.4
KHz
— ISD2575
2.7
KHz
— ISD2590
2.3
KHz
— ISD25120
1.7
KHz
*
Conditions
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
Advance information: ISD2532/40/48/64 devices.
1–91
ISD2500 Series
Product Data Sheets
AC PARAMETERS (PACKAGED PARTS) – CONTINUED
Symbol
TREC
TPLAY
Characteristic
Record
Duration
Playback
Duration
-1
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2560
— ISD2575
— ISD2575
— ISD2590
— ISD25120
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2560
— ISD2575
— ISD2575
— ISD2590
— ISD25120
Min(2)
Typ (1)
58.1
56.5
72.6
70.7
87.1
116.1
32.0
40.0
48.0
64.0
60.0
60.0
75.0
75.0
90.0
120.0
58.1
56.5
72.6
70.7
87.1
116.1
32.0
40.0
48.0
64.0
60.0
60.0
75.0
75.0
90.0
120.0
Max(2)
Units
62.0
63.8
77.5
79.7
93.0
123.9
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
62.0
63.8
77.5
79.7
93.0
123.9
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
TCE
CE Pulse Width
100
nsec
TSET
Control/Address Setup Time
300
nsec
THOLD
Control/Address Hold Time
0
nsec
TPUD
Power-Up Delay
25.0
31.3
37.5
50.0
25.0
25.0
31.3
31.3
37.5
50.0
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
TPDR
1–92
PD Pulse
Width Record
*
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2560
— ISD2575
— ISD2575
— ISD2590
— ISD25120
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
Advance information: ISD2532/40/48/64 devices.
24.1
23.5
30.2
29.3
36.2
48.2
25
31.25
37.5
50.0
25
31.25
37.5
50.0
27.8
28.5
34.3
35.2
40.8
53.6
msec
msec
msec
msec
msec
msec
msec
msec
Conditions
Commercial Operation
Industrial Operation
Commercial Operation
Industrial Operation
Commercial Operation
Commercial Operation
(7)
(7)
(7)
(7)
Commercial Operation(7)
Industrial Operation(7)
Commercial Operation(7)
Industrial Operation(7)
Commercial Operation(7)
Commercial Operation(7)
Commercial Operation
Industrial Operation
Commercial Operation
Industrial Operation
Commercial Operation
Commercial Operation
ISD2500 Series
Product Data Sheets
AC PARAMETERS (PACKAGED PARTS) – CONTINUED
Symbol
Characteristic
TPDP
PD Pulse
Width Play
TPDS
PD Pulse Width Static
TPDH
Power Down Hold
TEOM
EOM Pulse Width
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
TOVF
Overflow Pulse Width
THD
Total Harmonic Distortion
POUT
Speaker Output Power
VOUT
Min(2)
Typ (1)
Max(2)
Units
12.5
15.625
18.75
25.0
12.5
15.625
18.75
25.0
msec
msec
msec
msec
msec
msec
msec
msec
100
nsec
0
nsec
12.5
15.625
18.75
25.0
12.5
15.625
18.75
25.0
msec
msec
msec
msec
msec
msec
msec
msec
6.5
µsec
Conditions
(6)
1
1
2
%
12.2
50
mW
Voltage Across Speaker Pins
2.5
V p–p
VIN1
MIC Input Voltage
20
mV
Peak-to-Peak (5)
VIN2
ANA IN Input Voltage
50
mV
Peak-to-Peak
VIN3
Aux Input Voltage
1.25
V
Peak-to-Peak;
REXT = 16 Ω
NOTES:
@ 1 KHz
REXT = 16 Ω (4)
REXT = 600 Ω
1. Typical values @ TA = 25° C and 5.0 V.
2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions).
4. From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT=12.2 mW, typical.
5. With 5.1 KΩ series resistor at ANA IN.
6. TPDS is required during a static condition, typically overflow.
7. Sampling Frequency and Playback Duration can vary as much as ± 2.25% over the commercial
temperature range and voltage range and ± 5% over the industrial temperature and voltage range.
For greater stability, an external clock can be utilized (see Pin Descriptions).
8. Filter specification applies to the antialiasing filter and the smoothing filter.
*
Advance information: ISD2532/40/48/64 devices.
1–93
ISD2500 Series
Product Data Sheets
TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE
(PACKAGED PARTS)
STANDBY CURRENT (ISB)
RECORD MODE OPERATING CURRENT (ICC)
Operating Current (mA)
25
1.2
Standby Current (µA)
20
15
10
5
1.0
0.8
0.6
0.4
0.2
-1
0
0
-40
25
70
85
-40
Temperature (C)
85
OSCILLATOR STABILITY
0.7
0.4
0.6
0.2
Percent Change (%)
Percent Distortion (%)
70
Temperature (C)
TOTAL HARMONIC DISTORTION
0.5
0.4
0.3
0.2
0.1
0
-0.2
-0.4
-0.6
-0.8
0
-1.0
-40
25
70
Temperature (C)
5.5 Volts
1–94
25
*
4.5 Volts
Advance information: ISD2532/40/48/64 devices.
85
-40
25
70
Temperature (C)
85
ISD2500 Series
Product Data Sheets
ABSOLUTE MAXIMUM RATINGS (DIE)
Condition
OPERATING CONDITIONS (DIE)
Value
Condition
Junction temperature
150° C
Storage temperature range
–65° C to +150° C
Voltage applied to any pad
(VSS – 0.3 V) to
(VCC + 0.3 V)
Voltage applied to any pad
(Input current limited to
+ 20 mA)
(VSS – 1.0 V) to
(VCC + 1.0 V)
VCC - VSS
– 0.3 V to + 7.0 V
NOTE:
Value
Commercial operating
temperature range
0° C to +50° C
Supply voltage (VCC)(1)
+4.5 V to +6.5 V
Ground voltage (VSS)(2)
0V
NOTES:
1. VCC = VCCA = VCCD.
2. VSS = VSSA = VSSD.
Stresses above those listed may cause permanent
damage to the device. Exposure to the absolute
maximum ratings may affect device reliability.
Functional operation is not implied at these
conditions.
1
DC PARAMETERS (DIE)
Symbol
Parameters
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VOH1
Min(2)
Typ (1)
Max(2)
Units
0.8
V
2.0
Conditions
V
0.4
V
IOL = 4.0 mA
VCC–0.4
V
IOH = – 10 µA
OVF Output High Voltage
2.4
V
IOH = – 1.6 mA
VOH2
EOM Output High Voltage
VCC–1.0
V
IOH = – 3.2 mA
ICC
VCC Current (Operating)
25
30
mA
REXT = ∞ (3)
ISB
VCC Current (Standby)
1
10
µA
(2)
IIL
Input Leakage Current
+1
µA
IILPD
Input Current HIGH w/Pull
Down
130
µA
Force VCC (4)
REXT
Output Load Impedance
16
Ω
Speaker Load
RMIC
Preamp In Input Resistance
4
9
15
KΩ
RAUX
AUX INput Resistance
5
11
20
KΩ
RANA IN
ANA IN Input Resistance
2.3
3
5
KΩ
VCC–0.8
*
MIC and MIC REF Pads
Advance information: ISD2532/40/48/64 devices.
1–95
ISD2500 Series
Product Data Sheets
DC PARAMETERS (DIE) – CONTINUED
Symbol
Min(2)
Typ (1)
Max(2)
Units
21
24
26
dB
AGC = 0.0 V
AGC = 2.5 V
APRE1
Preamp Gain 1
APRE2
Preamp Gain 2
– 15
5
dB
AAUX
AUX IN/SP+ Gain
0.98
1.0
V/V
AARP
ANA IN to SP+/- Gain
21
23
26
dB
RAGC
AGC Output Resistance
2.5
5
9.5
KΩ
NOTES:
-1
Parameters
Conditions
1. Typical values @ TA = 25° C and 5.0 V.
2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. VCCA and VCCD connected together.
4. XCLK pad only.
AC PARAMETERS (DIE)
Symbol
FS
FCF
TREC
1–96
Characteristic
Sampling
Frequency
Filter Pass Band
Record
Duration
*
Min(2)
Typ (1)
Max(2)
Units
Conditions
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
8.0
6.4
5.3
4.0
8.0
6.4
5.3
4.0
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
— ISD2532*
3.4
KHz
— ISD2540*
2.7
KHz
— ISD2548*
2.3
KHz
— ISD2564*
1.7
KHz
— ISD2560
3.4
KHz
— ISD2575
2.7
KHz
— ISD2590
2.3
KHz
— ISD25120
1.7
KHz
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
3 dB Roll-Off Point (3) (8)
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
32.0
40.0
48.0
64.0
60.0
75.0
90.0
120.0
sec
sec
sec
sec
sec
sec
sec
sec
Commercial Operation
Commercial Operation
Commercial Operation
Commercial Operation
Advance information: ISD2532/40/48/64 devices.
58.1
72.6
87.1
116.1
62.0
77.5
93.0
123.9
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
ISD2500 Series
Product Data Sheets
AC PARAMETERS (DIE) – CONTINUED
Symbol
TPLAY
Characteristic
Playback
Duration
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
Min(2)
Typ (1)
58.1
72.6
87.1
116.1
32.0
40.0
48.0
64.0
60.0
75.0
90.0
120.0
Max(2)
Units
62.0
77.5
93.0
123.9
sec
sec
sec
sec
sec
sec
sec
sec
TCE
CE Pulse Width
100
nsec
TSET
Control/Address Setup Time
300
nsec
THOLD
Control/Address Hold Time
0
nsec
TPUD
Power-Up Delay
25.0
31.3
37.5
50.0
25.0
31.3
37.5
50.0
msec
msec
msec
msec
msec
msec
msec
msec
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
24.1
30.2
36.2
48.2
27.8
34.3
40.8
53.6
TPDR
PD Pulse
Width Record
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
25
31.25
37.5
50.0
25
31.25
37.5
50.0
msec
msec
msec
msec
msec
msec
msec
msec
TPDP
PD Pulse
Width Play
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
12.5
15.625
18.75
25.0
12.5
15.625
18.75
25.0
msec
msec
msec
msec
msec
msec
msec
msec
TPDS
PD Pulse Width Static
100
nsec
TPDH
Power Down Hold
0
nsec
*
Conditions
(7)
(7)
(7)
(7)
Commercial Operation(7)
Commercial Operation(7)
Commercial Operation(7)
Commercial Operation(7)
1
Commercial Operation
Commercial Operation
Commercial Operation
Commercial Operation
(6)
Advance information: ISD2532/40/48/64 devices.
1–97
ISD2500 Series
Product Data Sheets
AC PARAMETERS (DIE) – CONTINUED
Symbol
-1
Characteristic
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
TEOM
EOM Pulse Width
TOVF
Overflow Pulse Width
THD
Total Harmonic Distortion
POUT
Speaker Output Power
VOUT
Min(2)
Typ (1)
Max(2)
Units
12.5
15.625
18.75
25.0
12.5
15.625
18.75
25.0
msec
msec
msec
msec
msec
msec
msec
msec
6.5
µsec
Conditions
1
3
%
12.2
50
mW
Voltage Across Speaker Pins
2.5
V p–p
VIN1
MIC Input Voltage
20
mV
Peak-to-Peak (5)
VIN2
ANA IN Input Voltage
50
mV
Peak-to-Peak
VIN3
Aux Input Voltage
1.25
V
Peak-to-Peak;
REXT = 16 Ω
NOTES:
1–98
@ 1 KHz
REXT = 16 Ω (4)
REXT = 600 Ω
1. Typical values @ TA = 25° C and 5.0 V.
2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions).
4. From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT=12.2 mW, typical.
5. With 5.1 KΩ series resistor at ANA IN.
6. TPDS is required during a static condition, typically overflow.
7. Sampling Frequency and Playback Duration can vary as much as ± 2.25% over the commercial temperature range
and voltage range. For greater stability, an external clock can be utilized (see Pin Descriptions).
8. Filter specification applies to the antialiasing filter and the smoothing filter.
*
Advance information: ISD2532/40/48/64 devices.
ISD2500 Series
Product Data Sheets
TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE (DIE)
STANDBY CURRENT (ISB)
RECORD MODE OPERATING CURRENT (ICC)
1.0
25
Standby Current (µA)
Operating Current (mA)
30
20
15
10
0.8
0.6
0.4
0.2
5
1
0
0
0
25
50
0
Temperature (C)
OSCILLATOR STABILITY
0.2
0.6
0
Percent Change (%)
Percent Distortion (%)
0.7
0.5
0.4
0.3
0.2
-0.2
-0.4
-0.6
0.1
-0.8
0
-1.0
25
50
0
Temperature (C)
6.5 Volts
5.5 Volts
50
Temperature (C)
TOTAL HARMONIC DISTORTION
0
25
25
50
Temperature (C)
4.5 Volts
*
Advance information: ISD2532/40/48/64 devices.
1–99
ISD2500 Series
Product Data Sheets
ISD2500 APPLICATION EXAMPLE – DESIGN SCHEMATIC
ISD2500 (PDIP/SOIC)
1
V CC
VSS
2
3
4
R4
100 KΩ
5
6
7
8
CHIP ENABLE
9
10
POWER DOWN
23
24
27
25
PLAYBACK/RECORD
22
26
-1
A0
A1
A2
A3
A4
A5
A6
A7 (NC*)
A8 (A7*)
A9 (A8*)
CE
PD
P/R
EOM
OVF
XCLK
V CC
VCCD 28
VCCA 16
VSSD
VSSA
12
SP+
SP–
AUX IN
ANA IN
14
*
22 µF
15
11
16 Ω
SPEAKER
20
21
MIC REF**
MIC
18
AGC
19
C3
0.1 µF
R 6 5.1 KΩ
17
C2
4.7 µF
C1
0.1 µF
V CC
R1
1 KΩ
NOTES:
C7
0.1 µF
13
ANA OUT
R2
470 KΩ
C8
C6
0.1 µF
R3
10 KΩ
C4
220 µF
ELECTRET
MICROPHONE
C5
0.1 µF
R5
10 KΩ
Pin identifications for the ISD2532/40/48/64 devices which differ from those of the ISD2560/75/90/120 devices are
indicated.
** If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In this case,
pin 18 must not be tied to any other signal or voltage. Additional design example schematics are provided in the
Application Notes and Design Manual in this book.
APPLICATION EXAMPLE – BASIC DEVICE CONTROL
Control Step
1–100
Function
Action
1
Power up chip and select Record/Playback mode
1. PD = LOW, 2. P/R = As desired
2
Set message address for Record/Playback
Set addresses A0–A9
3A
Begin Playback
P/R = HIGH, CE = Pulsed LOW
3B
Begin Record
P/R = LOW, CE = LOW
4A
4B
End Playback
End Record
Automatic
PD or CE = HIGH
*
Advance information: ISD2532/40/48/64 devices.
ISD2500 Series
Product Data Sheets
APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS
Part
Function
Comments
R1
Microphone power supply
decoupling
Reduces power supply noise
R2
Release time constant
Sets release time for AGC
R3, R5
Microphone biasing resistors
Provides biasing for microphone operation
R4
Series limiting resistor
Reduces level to prevent distortion at higher supply
voltages.
R6
Series limiting resistor
Reduces level to high supply voltages
C1, C5
Microphone DC–blocking capacitor
Low-frequency cutoff
Decouples microphone bias from chip. Provides singlepole low-frequency cutoff and common mode noise
rejection.
C2
Attack/Release time constant
Sets attack/release time for AGC
C3
Low-frequency cutoff capacitor
Provides additional pole for low-frequency cutoff
C4
Microphone power supply
decoupling
Reduces power supply noise
C6, C7, C8
Power supply capacitors
Filter and bypass of power supply
1
EXPLANATION
In this simplified block diagram of a microcontroller
application, the Push-Button mode and message
cueing are used. The microcontroller is a 16-pin
version with enough port pins for buttons, an LED,
and the ISD2500 Series device. The software can
be written to use three buttons: one each for play
and record, and one for message selection.
Because the microcontroller is interpreting the buttons and commanding the ISD2500 device,
software can be written for any functions desired in
a particular application.
NOTE
ISD does not recomend connecting
address lines directly to a microprocessor
bus. Address lines should be externally
latched.
*
Advance information: ISD2532/40/48/64 devices.
1–101
ISD2500 Series
Product Data Sheets
ISD2500 APPLICATION EXAMPLE – MICROCONTROLLER/ISD2500 INTERFACE
V CC
S1
RECORD
S2
PLAY
S3
MSG#
D1
RUN
MC68HC705K1A
ISD2500 (PDIP/SOIC)
PB0
PB1
OSC1
OSC2
1
2
RESET
IRQ
U1
VDD
V SS
-1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R1
TBD
3
4
5
6
7
8
9
10
23
24
27
25
22
26
NOTES:
1–102
*
Pin identifications for the ISD2532/40/48/64 devices which differ from those of the
ISD2560/75/90/120 devices are indicated.
*
Advance information: ISD2532/40/48/64 devices.
A0
A1
A2
A3
A4
U2
A5
A6
A7 (NC*)
A8 (A7*)
A9 (A8*)
CE
PD
P/R
EOM
OVF
XCLK
28
CCD
16
CCA
12
SSD
13
SSA
14
15
11
20
21
18
17
19
ISD2500 Series
Product Data Sheets
ISD2500 APPLICATION EXAMPLE – PUSH-BUTTON
ISD2500 (PDIP/SOIC)
1
V CC
2
VSS
3
4
R6
100 KΩ
V CC
R7
100 KΩ
V CC
5
6
7
S1
8
9
START/PAUSE
10
S2
23
STOP/RESET
24
27
25
22
PLAYBACK/RECORD
26
A0
A1
A2
A3
A4
A5
A6
A7 (NC*)
A8 (A7*)
A9 (A8*)
CE
PD
P/R
EOM
OVF
XCLK
V CC
VCCD 28
VCCA 16
VSSD
VSSA
12
SP+
SP–
AUX IN
ANA IN
14
ANA OUT
21
MIC REF
MIC
18
AGC
19
C4
0.1 µF
C5
22 µF
C1
0.1 µF
13
LS1
15
11
16 Ω
SPEAKER
20
C3
0.1 µF
R 4 5.1 KΩ
17
C1
0.1 µF
V CC
R3
10 KΩ
R2
470 KΩ
NOTES:
*
C2
4.7 µF
C4
220 µF
ELECTRET
MICROPHONE
C5
0.1 µF
R5
10 KΩ
Pin identifications for the ISD2532/40/48/64 devices which differ from those of the
ISD2560/75/90/120 devices are indicated.
** For more details, please refer to the ISD Application Notes and Design Manual.
APPLICATION EXAMPLE – PUSH-BUTTON CONTROL
Control Step
1
Function
Action
Select Record/Playback mode
P/R = As desired
2A
Begin Playback
2B
Begin Record
P/R = HIGH
CE = Pulsed LOW
P/R = LOW
CE = Pulsed LOW
3
Pause Record or Playback
CE = Pulsed LOW
4A
End Payback
4B
End Record
Automatic at EOM marker or
PD = Pulsed HIGH
PD = Pulsed HIGH
*
Advance information: ISD2532/40/48/64 devices.
1–103
1
ISD2500 Series
Product Data Sheets
APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS
Part
-1
Function
Comments
R2
Release time constant
Sets release time for AGC
R4
Series limiting resistor
Reduces level to prevent distortion at
higher supply voltages
R6, R7
Pull-up and pull-down resistors
Defines static state of inputs
C1, C4, C5
Power supply capacitors
Filters and bypass of power supply
C2
Attack/Release time constant
Sets attack/release time for AGC
C3
Low-frequency cutoff capacitor
Provides additional pole for lowfrequency cutoff
PUSH-BUTTON PARAMETERS
Symbol
Characteristic
Min
Typ (1)
Max
Units
TCE
CE Pulse Width [Start/Pause]
300
nsec
TSET
Control/Address Setup Time
300
nsec
TPUD
Power-Up Delay
25
31.25
37.25
50.0
25
31.25
37.25
50.0
msec
msec
msec
msec
msec
msec
msec
msec
TPD
PD Pulse Width [Stop/Reset]
300
nsec
TRUN
CE to EOM HIGH
25
400
nsec
TPAUSE
CE to EOM LOW
50
400
nsec
TDB
CE HIGH
Debounce
70
85
105
135
70
85
105
135
105
135
160
215
105
135
160
215
msec
msec
msec
msec
msec
msec
msec
msec
1–104
*
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
— ISD2532*
— ISD2540*
— ISD2548*
— ISD2564*
— ISD2560
— ISD2575
— ISD2590
— ISD25120
Advance information: ISD2532/40/48/64 devices.
Conditions
ISD2500 Series
Product Data Sheets
TIMING DIAGRAMS
Push-Button Mode Record
"Pause"
"Start"
TCE
CE
(Start/Pause)
"Start"
TCE
TSET
"Stop"
TCE
TSET
TSET
P/R
TSET
PD
(Stop/Reset)
TPD
TSET
TSET
A0-A9
MIC ANA IN
OVF
TPAUSE
TRUN
EOM
(Run)
TDB
TDB
TPUD
Notes:
(1)
TPUD
(2)
(3)
(4, 5)
TDB
(6, 7)
1
(8)
Push-Button Mode Playback
"Pause"
"Start"
TCE
CE
(Start/Pause)
"Start"
TCE
TSET
"Stop"
TCE
TSET
TSET
P/R
TSET
PD
(Stop/Reset)
TPD
TSET
TSET
A0-A9
SP+/–
OVF
TPAUSE
TRUN
EOM
(Run)
TDB
TPUD
Notes:
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
(1)
(2)
(3)
TDB
(4, 5)
TPUD
(6, 7)
TDB
(8)
A9, A8, and A6 = 1 for push-button operation.
The first CE LOW pulse performs a Start function.
The part will begin to play or record after a power-up delay TPUD.
The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of
CE and pause.
The second CE LOW pulse, and every even pulse thereafter, performs a Pause function.
Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling
edge of CE, which would restart an operation. In addition, the part will not do an internal power down until
CE is HIGH for the TDB time.
The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function.
At any time, a HIGH level on PD will stop the current function, reset the address counter, and power down
the device.
*
Advance information: ISD2532/40/48/64 devices.
1–105
ISD2500 Series
Product Data Sheets
ORDERING INFORMATION
Product Number Descriptor Key
ISD25 _ _ _ _
2 = 2nd Generation
Special Temperature Field:
Blank = Commercial Packaged (0˚C to +70˚C)
or Commercial Die (0˚C to +50˚C)
I = Industrial (-40˚C to +85˚C)
5 = 5 Volts
-1
Duration:
32 = 32 Seconds*
40 = 40 Seconds*
48 = 48 Seconds*
64 = 64 Seconds*
60 = 60 Seconds
75 = 75 Seconds
90 = 90 Seconds
120 = 120 Seconds
Package Type:
E = 28-Lead 8x13.4-mm Thin Small Outline Package
(TSOP)
P = 28-Lead 0.600-Inch Plastic Dual In-Line Package
(PDIP)
S = 28-Lead 0.300-Inch Small Outline Integrated Circuit
(SOIC)
T = 32-Lead 8x20-mm Thin Small Outline Package
(TSOP)
X = Die
When ordering ISD2500 Series devices, please refer to the following valid part numbers.
Part Number
Part Number
Part Number
Part Number
ISD2560E
ISD2575E
ISD2590E
ISD25120P
ISD2560EI
ISD2575EI
ISD2590P
ISD25120X
ISD2560P
ISD2575P
ISD2590S
ISD2560PI
ISD2575PI
ISD2590T
ISD2560S
ISD2575S
ISD2590X
ISD2560SI
ISD2575SI
ISD2560T
ISD2575T
ISD2560TI
ISD2575TI
ISD2560X
ISD2575X
For the latest product information, access ISD’s worldwide website at http://www.isd.com.
1–106
*
Advance information: ISD2532/40/48/64 devices.