PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84324 is a Crystal-to-3.3V LVPECL Frequency Synthesizer with Fanout Buffer and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. Output frequency can be programmed using frequency select pins. The low phase noise characteristics of the ICS84324 make it an ideal clock source for Fibre Channel 1 and Gigabit Ethernet applications. • 6 differential 3.3V LVPECL outputs ,&6 • Crystal oscillator interface • Output frequency range: 53.125MHz to 125MHz • Crystal input frequency: 25MHz and 25.5MHz • RMS phase jitter at 106.25MHz, using a 25.5MHz crystal (637KHz to 10Mhz): 2.69ps • Phase noise: Offset Noise Power 100Hz ................. -96 dBc/Hz 1KHz ................. -115 dBc/Hz 10KHz ................. -125 dBc/Hz 100KHz ................. -127 dBc/Hz FUNCTION TABLE Inputs XTAL Output Frequency MR F_SEL1 F_SEL0 F_OUT 1 X X LOW 0 0 0 25.5MHz 53.125MHz • 3.3V supply voltage 0 0 1 25.5MHz 106.25MHz • 0°C to 70°C ambient operating temperature 0 1 0 25MHz 62.5MHz 0 1 1 25MHz 125MHz • Industrial termperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 0 OSC XTAL2 1 Output Divider PLL 6 Q0:Q5 6 nQ0:nQ5 / / Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Feedback Divider 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCO F_SEL0 F_SEL1 MR XTAL1 XTAL2 VEE VCCA VCC PLL_SEL VEE VCCO ICS84324 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View F_SEL1 MR PLL_SEL F_SEL0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84324EM www.icst.com/products/hiperclocks.html 1 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Type Description Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11, 12 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 13, 24 VCCO Power Output supply pins. 16 VCC Power Core supply pin. 14, 18 VEE 15 PLL_SEL Input 17 VCCA Power Analog supply pin. 19, 20 XTAL2, XTAL1 Input Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Negative supply pins. Pullup Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. 21 MR Input Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 22 F_SEL1 Input Pulldown Feedback frequency select pin. LVCMOS / LVTTL interface levels. 23 F_SEL0 Input Pullup Output frequency select pin. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical CIN Input Capacitance 4 RPULLUP Input Pullup Resistor 51 RPULLDOWN Input Pulldown Resistor 51 84324EM www.icst.com/products/hiperclocks.html 2 Maximum Units pF KW KW REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 50°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 3.465 VCCA Analog Supply Voltage IEE Power Supply Current 135 mA V ICCA Analog Supply Current 20 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 PLL_SEL, F_SEL0 Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V 150 µA 5 µA VCC = VIN = 3.465V VCC = VIN = 3.465V MR, F_SEL1 VCC = 3.465V, VIN = 0V -5 µA PLL_SEL, F_SEL0 VCC = 3.465V, VIN = 0V -150 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50W to VCCO - 2V. 84324EM www.icst.com/products/hiperclocks.html 3 Minimum Typical Maximum Units VCCO - 1.4 VCCO - 1.0 V VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25.5 MHz Equivalent Series Resistance (ESR) Frequency 25 50 Ω Shunt Capacitance 7 pF TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency Minimum 53.125 tsk(o) Output Skew; NOTE 1, 2 tR Output Rise Time 20% to 80% 200 20% to 80% 200 tF Output Fall Time odc Output Duty Cycle tPW Output Pulse Width Typical Units 125 MHz 650 ps 650 ps TBD ps 50 tPERIOD/2 - TBD % tPERIOD/2 + TBD PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 84324EM Maximum www.icst.com/products/hiperclocks.html 4 1 ps ms REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TYPICAL PHASE NOISE AT 106.25MHZ USING A 25.5MHZ QUARTZ CRYSTAL 0 -10 -20 -30 Jitter Process Result Source -40 -50 Start Freq. 10.000 Hz Stop Freq. 40.000M Hz Freq. carrier 106.250M Hz -60 Mode Noise only -70 sec. rms Integral 2.69p -80 Execute Plot -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10 100 1k 10k 100k 1M 10M 100M 637KHz to 10MHz, 2.69ps 84324EM www.icst.com/products/hiperclocks.html 5 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC, VCCA = 2V Qx SCOPE nQx Qx LVPECL nQy nQx Qy tsk(o) VEE = -1.3V ± 0.165 OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT nQ0:nQ5 80% 80% tR tF Q0:Q5 Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84324EM www.icst.com/products/hiperclocks.html 6 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84324 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 24Ω V CCA .01µF 10 µF FIGURE 2. POWER SUPPLY FILTERING TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Zo (VOH + VOL / VCC – 2) – 2 FIN 50Ω VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 84324EM 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER CRYSTAL INPUT INTERFACE A crystal can be characterized for either series or parallel mode operation. The ICS84324 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 4. 19 XTAL2 C1 18pF 25MHz X1 20 XTAL1 C2 22pF ICS84324 Figure 4. CRYSTAL INPUt INTERFACE SCHEMATIC EXAMPLE Figure 5A shows a schematic example of using an ICS84324. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VCCA pin as possible. VCC R4 1K VCC R7 24 VCCA 22p C11 0.1u C1 C16 10u X1 25MHz,18pF F_SEL1 R5 F_SEL0 1K C2 VCC U2 VCC Zo = 50 13 14 15 16 17 18 19 20 21 22 23 24 VCCO VEE PLL_SEL VCC VCCA VEE XTAL2 XTAL1 MR F_SEL1 F_SEL0 VCCO nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 12 11 10 9 8 7 6 5 4 3 2 1 Zo = 50 + R1 50 R2 50 R3 50 18p ICS84324 RU2 1K RU3 1K VCC=3.3V F_SEL1 F_SEL0 RD2 SP RD3 SP (U1,13) VCC (U1,16) C6 0.1u e.g. F_SEL[1:0]=11 (U1,24) C5 0.1u C3 0.1u SP = Spare, Not Installed FIGURE 5A. ICS84324 SCHEMATIC EXAMPLE 84324EM www.icst.com/products/hiperclocks.html 8 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER The following component footprints are used in this layout example: • The differential 50Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 20 (XTAL1) and 19(XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C6 GND VCC C1 C5 Signals R7 VCCA VIA C11 C16 X1 C2 C3 U1 ICS84324 Pin1 50 Ohm Traces FIGURE 5B. PCB BOARD LAYOUT FOR ICS84324 84324EM www.icst.com/products/hiperclocks.html 9 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84324. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84324 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 468mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.2mW = 181mW Total Power_MAX (3.465V, with all outputs switching) = 468mW + 181mW = 649mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.649W * 43°C/W = 98°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 50°C/W 43°C/W 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84324EM www.icst.com/products/hiperclocks.html 10 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V – 1.0V CCO_MAX ) = 1.0V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX ))/R ] * (V -V OH_MAX CCO_MAX L -V OH_MAX )= [(2V - 1V)/50Ω) * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 84324EM www.icst.com/products/hiperclocks.html 11 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50°C/W 43°C/W 500 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84324 is: 3500 84324EM www.icst.com/products/hiperclocks.html 12 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER FOR 24 LEAD SOIC TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum Maximum N A 24 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 15.20 15.85 E 7.40 e H 7.60 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 a 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 84324EM www.icst.com/products/hiperclocks.html 13 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS84324EM ICS84324EM 24 Lead SOIC 30 per tube 0°C to 70°C ICS84324EMT ICS84324EM 24 Lead SOIC on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84324EM www.icst.com/products/hiperclocks.html 14 REV. A SEPTEMBER 18, 2003