PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84427 is a Crystal-to-LVDS Frequency Synthesizer/Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The output frequency can be programmed using the frequency select pins. The low phase noise characteristics of the ICS84427 make it an ideal clock source for 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, OC3 and OC12 applications. • Six LVDS outputs ICS • Crystal oscillator interface • Output frequency range: 77.76MHz to 625MHz • Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz • RMS phase jitter at 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 3.4ps (typical) Phase noise: Offset Noise Power 100Hz ................. -95 dBc/Hz 1kHz ............... -110 dBc/Hz 10kHz ............... -120 dBc/Hz 100kHz ............... -121 dBc/Hz FUNCTION TABLE Inputs F_SEL1 F_SEL0 Output Frequency F_OUT F_XTAL MR F_SEL2 X 1 X X X LOW 19.44MHz 0 1 0 0 77.76MHz • 0°C to 70°C ambient operating temperature 19.44MHz 0 1 0 1 155.52MHz • Industrial temperature information available upon request 19.44MHz 0 1 1 0 311.04MHz 19.44MHz 0 1 1 1 622.08MHz • Available in both standard and lead-free RoHS-compliant packages 25MHz 0 0 0 0 78.125MHz 25MHz 0 0 0 1 156.25MHz 25MHz 0 0 1 0 312.5 MHz 25MHz 0 0 1 1 625MHz 25.5MHz 0 0 0 1 159.375MHz • 3.3V supply voltage BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN 0 OSC XTAL_OUT 1 Output Divider PLL 6 Q0:Q5 6 nQ0:nQ5 / / Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Feedback Divider 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD F_SEL0 F_SEL1 MR XTAL_IN XTAL_OUT F_SEL2 V DDA VDD PLL_SEL GND VDD ICS84427 F_SEL2 MR PLL_SEL F_SEL1 F_SEL0 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84427CM www.icst.com/products/hiperclocks.html 1 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Type Output Description Differential output pair. LVDS interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVDS interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVDS interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVDS interface levels. 11, 12 Q5, nQ5 Output Differential output pair. LVDS interface levels. 13, 16, 24 VDD Power Core supply pins. 14 GN D 15 PLL_SEL Input 17 VDDA Power Power supply ground. Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL_IN and XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. 18 19, 20 F_SEL2 XTAL_OUT, XTAL_IN Input 21 MR Input 22 F_SEL1 Input 23 F_SEL0 Input Input Pullup Pullup Feedback frequency select pin. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 84427CM www.icst.com/products/hiperclocks.html 2 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 50°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3. 3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 235 mA IDDA Analog Supply Current 20 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical 2 -0.3 VDD = VIN = 3.465V MR, F_SEL1 PLL_SEL, F_SEL0 VDD = VIN = 3.465V Maximum Units VDD + 0.3 V 0. 8 V 150 µA 5 µA MR, F_SEL1 VDD = 3.465V, VIN = 0V -5 µA PLL_SEL, F_SEL0 VDD = 3.465V, VIN = 0V -150 µA TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change 84427CM Test Conditions Minimum Typical Maximum Units 250 400 600 mV 50 mV 1.4 V 50 www.icst.com/products/hiperclocks.html 3 mV REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25.5 MHz Equivalent Series Resistance (ESR) Frequency 19.44 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT tsk(o) Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit(Ø) Test Conditions Minimum Typical 77.76 155.52MHz, (Integration Range: 12kHz-20MHz) 20% to 80% 45 www.icst.com/products/hiperclocks.html 4 Units 625 MHz 3.4 ps 40 ps 400 ps 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: See Phase Noise Plots. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 84427CM Maximum 55 % 1 ms REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER TYPICAL PHASE NOISE AT 155.52MHZ 0 -10 -20 19.44MHz Input RMS Phase Noise Jitter 12kHz to 20MHz = 3.4ps (typical) -30 -40 -50 -70 Z (dBc H ) PHASE NOISE -60 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ ( ) dBc HZ PHASE NOISE 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 25MHz Input RMS Phase Noise Jitter 12kHz to 20MHz = 3.1ps (typical) 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 84427CM www.icst.com/products/hiperclocks.html 5 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD 3.3V±5% POWER SUPPLY + Float GND - out SCOPE DC Input LVDS LVDS ➤ Qx ➤ out nQx VOS/Δ VOS ➤ 3.3V OUTPUT LOAD AC TEST CIRCUIT OFFSET VOLTAGE SETUP VDD nQx Qx ➤ out ➤ LVDS 100 VOD/Δ VOD out nQy ➤ DC Input Qy tsk(o) DIFFERENTIAL OUTPUT VOLTAGE SETUP OUTPUT SKEW nQ0:nQ5 80% 80% Q0:Q5 VOD Clock Outputs t PW 20% 20% tR t PERIOD tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME 84427CM OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 6 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84427 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 24Ω V DDA .01μF 10 μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS84427 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. CRYSTAL INPUt INTERFACE 84427CM www.icst.com/products/hiperclocks.html 7 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver in- put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 84427CM www.icst.com/products/hiperclocks.html 8 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER SCHEMATIC EXAMPLE Figure 4A shows a schematic example of using an ICS84427. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible. For LVDS driver, the unused output pairs should be terminated with a 100Ω resistor across. VDD VDD R4 1K R7 24 VDDA 22p C11 0.1u C16 10u F_SEL2 C1 X1 25MHz,18pF U1 VDD F_SEL1 R5 F_SEL0 1K C2 Zo = 50 13 14 15 16 17 18 19 20 21 22 23 24 VDD VEE PLL_SEL VDD VDDA F_SEL2 XTAL_OUT XTAL_IN MR F_SEL1 F_SEL0 VDD nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 12 11 10 9 8 7 6 5 4 3 2 1 + R1 100 - Zo = 50 LVDS_input VDD VDD 18p ICS84427 RU1 1K RU2 SP RU3 1K VDD=3.3V F_SEL2 F_SEL1 F_SEL0 RD1 SP RD2 1K RD3 SP VDD (U1,13) (U1,16) C6 0.1u e.g. F_SEL[2:0]=101 (U1,24) C5 0.1u C3 0.1u SP = Spare, Not Installed FIGURE 4A. ICS84427 SCHEMATIC EXAMPLE 84427CM www.icst.com/products/hiperclocks.html 9 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER The following component footprints are used in this layout example: • The differential 100Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND • Make sure no other signal traces are routed between the clock trace pair. TERMINATION • The matching termination resistors should be located as close to the receiver input pins as possible. Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 20 (XTAL_IN) and 19 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C6 GND VDD C1 C5 Signals R7 VDDA C16 VIA C11 X1 C2 C3 U1 ICS84427 Pin1 50 Ohm Traces FIGURE 4B. PCB BOARD LAYOUT FOR ICS84427 84427CM www.icst.com/products/hiperclocks.html 10 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50°C/W 43°C/W 500 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84427 is: 2804 84427CM www.icst.com/products/hiperclocks.html 11 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX FOR ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER 24 LEAD SOIC TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 24 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 15.20 15.85 E 7.40 e H 7.60 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 84427CM www.icst.com/products/hiperclocks.html 12 REV. D NOVEMBER 30, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS84427 CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS84427CM ICS84427CM 24 Lead SOIC tube 0°C to 70°C ICS84427CMT ICS84427CM 24 Lead SOIC 1000 tape & reel 0°C to 70°C ICS84427CMLF ICS84427CMLF 24 Lead "Lead-Free" SOIC tube 0°C to 70°C ICS84427CMLFT ICS84427CMLF 24 Lead "Lead-Free" SOIC 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84427CM www.icst.com/products/hiperclocks.html 13 REV. D NOVEMBER 30, 2005