Integrated Circuit Systems, Inc. ICS9248-185 Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 Pin Configuration VDD REF0 GND X1 X2 VDDPCI 1 *PCICLK_F GND 1, 2 FS1/PCICLK0 BUFFER_IN 1 PCICLK1 PCI_STOP# GND *FS0/48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ICS9248-185 Recommended Application: VIA PM133 chipset Output Features: • 2 - CPUs @ 2.5V • 5 - SDRAM @ 3.3V • 3 - PCI @ 3.3V, • 1 - 48MHz, @ 3.3V fixed. • 2 - REF @ 3.3V, 14.318MHz. Features: • Up to 133MHz frequency support • Support power management: PCI_STOP & CLK_STOP • Spread spectrum for EMI control (-0.5% down spread). • Uses external 14.318MHz crystal • FS pins for frequency select Key Specifications: • CPU – PCI Skew: 1-4ns • PCI – PCI Skew: ±500ps • CPU – CPU Skew: ±175ps • CPU Jitter: 250ps (cyc-cyc) • PCI Jitter: 500ps (cyc-cyc) 1 REF1/FREE_SEL* VDDL CPUCLK0/_F CPUCLK1 GND CLK_STOP# SDRAM0/_F SDRAM1 SDRAM2 GND VDDSDR SDRAM3 SDRAM4 VDD48 28-Pin SSOP/TSSOP * Internal Pull-up Resistor of 120K to VDD 1. These pin will have 2X drive strength 2. FS1 is a pull down Block Diagram PLL2 X1 X2 48MHz XTAL OSC REF (1:0) 2 CPU DIVDER PLL1 Spread Spectrum CPUCLK0/_F BUFFER_IN Stop 4 Logic Config. Reg. FS1 FS0 CPUCLK PCICLK Down Spread 0 0 66.66 33.33 -0.5% 0 1 100.00 33.33 -0.5% 1 0 97.00 32.33 -0.5% 1 1 133.33 33.33 -0.5% SDRAM (4:1) SDRAM0/_F Control PCI_STOP# CLK_STOP# FS (1:0) Frequency Select CPUCLK1 Stop PCI DIVDER Stop 2 PCICLK (1:0) PCICLK_F Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9248-185 RevC - 10/25/01 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-185 General Description The ICS9248-185 is the single chip clock solution for Notebook designs using the 440BX or the VIA Apollo Pro 133 style chipset. It provides all necessary clock signals for such a system. The ICS9248-185 provides CPU and PCI clocks with continous spread spectrum. The ICS9248-185 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Pin Descriptions PIN P I N NA M E NUMBER 1, 6, 15, 18, VDD 2 TYPE PWR DESCRIPTION Power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the STRONGER buffer f o r I S A BU S l o a d s REF0 OUT GND PWR Ground 10 11 X1 X2 PCICLK_F FS11, 2 PCICLK0 BUFFER IN PCICLK1 IN OUT OUT IN OUT IN OUT 12 PCI_STOP# IN Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Frequency select pin. Latched Input 48MHz output clock SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Either free running SDRAM or stoppable depending on FREE_SEL This asynchronous input halts CPUCLKs, & SDRAMs at logic "0" level when driven low. CPU clock output, powered by VDDL Either free running CPUCLK or stoppable depending on FREE_SEL Supply for CPU clocks 2.5V Selects CPUCLK0/_F and SDRAM0/_F to be either free running or stoppable by CLK_STOP#. When FREE_SEL is set to (0) low the above clocks are free running - when set to (1) high, the clocks are stoppable. 14.318 MHz reference clock. 3, 8, 13, 19, 24 4 5 7 9 1, 2 14 FS0 48MHz IN OUT 16, 17, 20, 21 22 SDRAM (4:1) OUT SDRAM0/_F OUT 23 CLK_STOP# IN 25 26 27 CPUCLK1 CPUCLK0/_F VDDL OUT OUT PWR 28 FREE_SEL REF1 IN OUT Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9248-185 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND –0.5 V to VDD +0.5 V 0°C to +70°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 2 Input High Voltage VIH VSS-0.3 Input Low Voltage VIL 63 CL = 30 pF; Select @ 66MHz Operating Supply IDD3.3OP 67 CL = 30 pF; Select @ 100MHz Current 73 CL = 30 pF; Select @ 133MHz IDDPD Powerdown Current CL = 0 pF; Input address VDD or GND VDD = 3.3 V 12 14.318 Input Frequency Fi Input Capacitance 1 1 Clk Stabilization 1 Skew 1 CIN CINX Logic Inputs X1 & X2 pins TSTAB From VDD = 3.3 V to 1% target Freq. tCPU-PCI1 27 VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 3 36 28 MAX VDD+0.3 0.8 150 170 180 600 16 UNITS V V mA µA MHz 5 45 pF pF 5.5 ms 4 ns ICS9248-185 Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF PARAMETER SYMBOL Output High Voltage VOH2A IOH = -20 mA IOL = 12 mA Output Low Voltage VOL2A Output High Current IOH2A VOH = 2.0 V VOL = 0.8 V Output Low Current IOL2A 22 TYP 2.85 0.31 -45 29 MAX UNITS V 0.4 V -27 mA mA tr2A VOL = 0.4 V, VOH = 2.4 V 0.9 1.6 ns 1 tf2A dt2A VOH = 2.4 V, VOL = 0.4 V 1 1.6 ns 50 55 % tsk2A VT = 1.5 V 35 175 ps tjcyc-cyc2A VT = 1.5 V Dram not running, CPU=66.6MHz 123 150 ps tjcyc-cyc2A VT = 1.5 V Dram running 119 250 ps 1 Duty Cycle 1 Skew window 1 Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle1 1 MIN 2.4 1 Rise Time Fall Time CONDITIONS VT = 1.5 V 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU TA = 0 - 70C; VDDL= 2.5V, +/-5%; CL = 20 pF PARAMETER SYMBOL IOH = -20 mA Output High Voltage VOH2A IOL = 12 mA Output Low Voltage VOL2A VOH = 2.0 V Output High Current IOH2A VOL = 0.8 V Output Low Current IOL2A 22 TYP 2.3 0.31 -39 26 MAX UNITS V 0.4 V -21 mA mA tr2A VOL = 0.4 V, VOH = 2.0 V 0.96 1.6 ns 1 tf2A dt2A VOH = 2.0 V, VOL = 0.4 V 1.06 1.6 ns 50.3 55 % tsk2A VT = 1.25 V 35 175 ps tjcyc-cyc2A VT = 1.25 V Dram not running 123 150 ps tjcyc-cyc2A VT = 1.25 V Dram running 119 250 ps 1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1 1 MIN 2 1 Rise Time Fall Time CONDITIONS VT = 1.25 V 45 Guaranteed by design, not 100% tested in production. 4 ICS9248-185 Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -18 mA Output High Voltage VOH1 IOL = 9.4 mA Output Low Voltage VOL1 Output High Current IOH1 VOH = 2.0 V VOL = 0.8 V Output Low Current IOL1 MAX UNITS V 0.4 V -33 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 1.51 2 ns 1 tf1 VOH = 2.4 V, VOL = 0.4 V 1.47 2 ns dt1 VT = 1.5 V 50.1 55 % tsk1 tcycle VT = 1.5 V VT = 1.5 V 58 145 500 500 ps ps Duty Cycle 1 1 Skew window Jitter, Cycle to cycle 1 38 TYP 3 0.2 -62 43 1 Rise Time Fall Time MIN 2.4 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = 3.3 V, VDDL= 2.50V, +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Fall Time1 Tf3 VOH = 2.4 V, VOL = 0.4 V Dt3 VT = 1.5 V Tsk3 VT = 1.5 V Tsk3 VT = 1.5 V 1 Duty Cycle 1 Skew window CONDITIONS IOH = -28 mA IOL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V MIN 2.4 32 45 TYP 3 0.3 -69 42 1.07 MAX UNITS V 0.4 V -46 mA mA 1.3 ns 1.3 2 ns 50.8 55 % 104 250 ps 5 ns 1 Propagation Time (Buffer In to output) 1 Guaranteed by design, not 100% tested in production. 5 ICS9248-185 Electrical Characteristics - REF TA = 0 - 70C; VDD = 3.3 V, VDDL= 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -14 mA 2.4 Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 6 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 16 Rise Time1 TYP 2.6 0.22 -32 22 MAX UNITS V 0.4 V -20 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 2.11 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 2.14 4 ns dt5 VT = 1.5 V 45 52.1 55 % tjcycle5 VT = 1.5 V -600 848 1000 ps TA = 0 - 70C; VDD = 3.3 V, VDDL= 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -14 mA 2.4 Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 6 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 16 TYP 2.6 0.22 -32 22 Fall Time 1 1 Duty Cycle Jitter, cycle to cycle1 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V 1.79 4 ns 1 tf5 VOH = 2.4 V, VOL = 0.4 V 1.92 4 ns dt5 VT = 1.5 V VT = 1.5 V 50.8 267 55 500 % ps Fall Time 1 Duty Cycle Jitter, cycle to cycle 1 MAX UNITS V 0.4 V -20 mA mA tjcycle 45 Guaranteed by design, not 100% tested in production. 6 ICS9248-185 CLK_STOP# Timing Diagram CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-185. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) SDRAM CPUCLK CPUCLK _F SDRAM_F Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-185. 3. All other clocks continue to run undisturbed. 7 ICS9248-185 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-185. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-185 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock. CPUCLK (Internal) PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP# PCI_STOP# PCICLK [6:0] Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state. 8 ICS9248-185 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 9 ICS9248-185 c N SYMBOL L E1 INDEX AREA A A1 A2 b c D E E1 e L N α E 1 2 α D A A2 A1 -Ce b In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° VARIATIONS SEATING PLANE N .10 (.004) C 28 D mm. MIN 9.90 D (inch) MAX 10.50 MIN .390 MAX .413 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 209 mil SSOP Ordering Information ICS9248yF-185-T Example: ICS XXXX y F - PPP T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 10 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-185 c N In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 SEE VARIATIONS D 6.40 BASIC E E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS α 0° 8° aaa -0.10 L E1 INDEX AREA E 1 2 α D A A2 A1 VARIATIONS -Ce b In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 D mm. N SEATING PLANE MIN 9.60 28 aaa C D (inch) MAX 9.80 MIN .378 MAX .386 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS9248yG-185-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 11 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.