IC62LV1008L IC62LV1008LL Document Title 1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM Revision History Revision No History Draft Date Remark 0A Initial Draft January 3,2002 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. LPSR015-0A 1/3/2002 1 IC62LV1008L IC62LV1008LL 1M x 8 LOW POWER and LOW VCC CMOS STATIC RAM FEATURES Preliminary DESCRIPTION The ICSI IC62LV1008L and IC62LV1008LL is a low voltage, • Access times of 55, 70, 100 ns • CMOS Low power operation: ICC=15mA (typical)* operation ISB2=2µA (typical)* standby • Low data retention voltage: 1.5V (min.) • Output Enable (OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications • TTL compatible inputs and outputs • Fully static operation: — No clock or refresh reguired • Single 2.7V-3.6V power supply • Wafer level burn in test mode • Available in the know good die form and 48-pin 8*10mm TF-BGA 1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62LV1008L and IC62LV1008LL are available in know good die form and 48-pin 8*10mm TF-BGA. * Typical values are measured at VCC=3.0V, TA=25°C FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE1 CE2 OE CONTROL CIRCUIT WE ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. LPSR015-0A 1/3/2001 IC62LV1008L IC62LV1008LL PIN CONFIGURATIONS 48-Pin 8*10mm TF-BGA (TOP View) 1 2 3 4 5 6 A NC OE A0 A1 A2 CE2 B NC NC A3 A4 CE1 NC C I/O0 NC A5 A6 NC I/O4 D GND I/O1 A17 A7 I/O5 Vcc E Vcc I/O2 Vcc A16 I/O6 GND F I/O3 NC A14 A15 NC I/O7 G NC NC A12 A13 WE NC H A18 A8 A9 A10 A11 A19 PIN DESCRIPTIONS A0-A19 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Data Input/Output NC No Connection Vcc Power GND Ground TRUTH TABLE WE CE1 CE2 OE I/O Operation Vcc Current Not Selected (POWER-DOWN) X X H X X L X X High-Z High-Z ISB1, ISB2 ISB1, ISB2 Output Disabled Read Write H H L L L L H H H H L X High-Z DOUT DIN ICC ICC ICC Mode OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C VCC 2.7V - 3.6V –40°C to +85°C 2.7V - 3.6V Integrated Circuit Solution Inc. LPSR015-0A 1/3/2002 3 IC62LV1008L IC62LV1008LL ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –0.3 to +4.0 –40 to +85 –65 to +150 1 Unit V V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1)(2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 3.0 V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(2) Input Leakage Output Leakage VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA 2.0 — 2.2 –0.2 –1 –1 — 0.4 VCC + 0.3 0.4 1 1 V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Notes: 1. VIH(max.) = VCC +2.0V for pulse width less than 10 ns. 1. VIL(min.) = –2.0V for pulse width less than 10 ns. 4 Integrated Circuit Solution Inc. LPSR015-0A 1/3/2001 IC62LV1008L IC62LV1008LL IC62LV1008L POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) -55 Symbol Parameter Test Conditions Min. -70 Max. Min. -100 Max. Min. Max. Unit ICC Vcc Dynamic Operating Supply Current VCC = 3.0V, CE1 = VIL,CE2=VIH IOUT = 0 mA, f = fMAX Com. Ind. — — 30 35 — — 25 30 — — 20 25 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., f = 0 CE1 ≥ VIH or CE2 ≤ VIL, VIN = VIH or VIL, Com. Ind. — — 0.2 0.3 — — 0.2 — 0.3 — 0.2 0.3 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 CE1 ≥ VCC – 0.2V or CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, VIN ≤ 0.2V Com. Ind. — — 35 50 — — 35 50 35 50 µA — — Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IC62LV1008LL POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) -55 Symbol Parameter Test Conditions Min. -70 Max. Min. -100 Max. Min. Max. Unit ICC Vcc Dynamic Operating Supply Current VCC = 3.0V, CE1 = VIL,CE2=VIH IOUT = 0 mA, f = fMAX Com. Ind. — — 30 35 — — 25 30 — — 20 25 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., f = 0 CE1 ≥ VIH or CE2 ≤ VIL, VIN = VIH or VIL, Com. Ind. — — 0.2 0.3 — — 0.2 — 0.3 — 0.2 0.3 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 CE1 ≥ VCC – 0.2V or CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, VIN ≤ 0.2V Com. Ind. — — 20 25 — — 20 25 20 25 µA — — Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. LPSR015-0A 1/3/2002 5 IC62LV1008L IC62LV1008LL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -55 Symbol Parameter -70 Min. Max. Min. Max. -100 Min. Max. Unit tRC Read Cycle Time 55 — 70 — 100 — ns tAA Address Access Time — 55 — 70 — 100 ns tOHA Output Hold Time 10 — 10 — 15 — ns tACE1 CE1 Access Time — 55 — 70 — 100 ns tACE2 CE2 Access Time — 55 — 70 — 100 ns tDOE OE Access Time — 30 — 35 — 50 ns tLZOE(2) OE to Low-Z Output 5 — 5 — 5 — ns tHZOE(2) OE to High-Z Output — 20 0 25 0 30 ns tLZCE1 CE1 to Low-Z Output 10 — 10 — 10 — ns tLZCE2 CE2 to Low-Z Output 10 — 10 — 10 — ns tHZCE(2) CE1 or CE2 to Low-Z Output 0 20 0 25 0 30 ns (2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V 1.5V See Figures 1 and 2 AC TEST LOADS 1 TTL OUTPUT OUTPUT 100 pF Including jig and scope Figure 1 6 1 TTL 5 pF Including jig and scope Figure 2 Integrated Circuit Solution Inc. LPSR015-0A 1/3/2001 IC62LV1008L IC62LV1008LL AC TEST LOADS READ CYCLE NO.1(1,2) (Address controlled, CE1 = OE = VIL , CE2 = VIH) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CE1, OE OE, CE2 controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE CE1 tLZOE tACE1/tACE2 CE2 DOUT tLZCE1/ tLZCE2 HIGH-Z tHZCE DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. LPSR015-0A 1/3/2002 7 IC62LV1008L IC62LV1008LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) Symbol Parameter Min. -55 Max. Min. -70 Max. -100 Min. Max Unit tWC Write Cycle Time 55 — 70 — 100 — ns tSCE1 CE1 to Write End 50 — 65 — 80 — ns tSCE2 CE2 to Write End 50 — 65 — 80 — ns tAW Address Setup Time to Write End 50 — 65 — 80 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns Address Setup Time 0 — 0 — 0 — ns tPWE WE Pulse Width 45 — 55 — 80 — ns tSD Data Setup to Write End 25 — 30 — 40 — ns tSA (4) tHD Data Hold from Write End 0 — 0 — 0 — ns (3) WE LOW to High-Z Output — 30 — 30 — 40 ns (3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns tHZWE tLZWE Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW , CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled) (1,2) tWC ADDRESS tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 8 tHD DATA-IN VALID Integrated Circuit Solution Inc. LPSR015-0A 1/3/2001 IC62LV1008L IC62LV1008LL WRITE CYCLE NO. 2 (CE1, CE2 Controlled) (1,2) tWC ADDRESS tSA tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE WE tHZWE DOUT DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the HIGH-z state if OE =VIH. Integrated Circuit Solution Inc. LPSR015-0A 1/3/2002 9 IC62LV1008L IC62LV1008LL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V IDR Data Retention Current Vcc = 1.5V, CE1 ≥ Vcc – 0.2V — — — — 15 6 20 9 µA µA µA µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform 10 — ns Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) DATA RETENTION WAVEFORM (CE1 Controlled) tSDR Data Retention Mode tRDR VCC 3.0V 2.2V VDR CE1 GND 10 CE1 ≥ VCC - 0.2V Integrated Circuit Solution Inc. LPSR015-0A 1/3/2001 IC62LV1008L IC62LV1008LL ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 55 IC62LV1008L-55B 8*10mm TF-BGA 55 IC62LV1008L-55BI 8*10mm TF-BGA 70 IC62LV1008L-70B 8*10mm TF-BGA 70 IC62LV1008L-70BI 8*10mm TF-BGA 100 IC62LV1008L-100B 8*10mm TF-BGA 100 IC62LV1008L-100BI 8*10mm TF-BGA ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 55 IC62LV1008LL-55B IC62LV1008LL-55D 8*10mm TF-BGA know good die 55 IC62LV1008LL-55BI IC62LV1008LL-55DI 8*10mm TF-BGA know good die 70 IC62LV1008LL-70B IC62LV1008LL-70D 8*10mm TF-BGA know good die 70 IC62LV1008LL-70BI IC62LV1008LL-70DI 8*10mm TF-BGA know good die 100 IC62LV1008LL-100B IC62LV1008LL-100D 8*10mm TF-BGA know good die 100 IC62LV1008LL-100BI 8*10mm TF-BGA IC62LV1008LL-100DI know good die Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. LPSR015-0A 1/3/2002 11