INTEL PD6710

PD6710/’22
ISA-to-PC-Card (PCMCIA) Controllers
Datasheet
The PD6710 and PD6722 are single-chip PC Card (PCMCIA) controller solutions capable of
controlling one (PD6710) or two (PD6722) PC Card sockets. The chips are compliant with PC
Card Standard, PCMCIA 2.1, and JEIDA 4.1 and are optimized for use in embedded
applications and notebook/handheld/mobile computer systems where reduced form factor and
low power consumption are critical design objectives. With the PD6710, a complete PC Card
solution with power-control logic can occupy less than 1.5 square inches (excluding the socket
connector). With the PD6722, a complete dual-socket PC Card solution with power-control
logic can occupy less than 2 square inches (excluding socket connectors).
The chips employ energy-efficient mixed-voltage technology that can reduce system power
consumption by over 50 percent. The chips also provide: a Low-Power Dynamic mode, which
automatically stops the internal clock during periods of card inactivity; a software-controlled
Suspend mode, which dramatically reduces power by disabling most of the internal circuitry and
stopping data transactions to the PC Cards; and a hardware-controlled Super Suspend mode,
which reduces current to the µA range.
Personal computer applications typically access PC Cards through a third-party socket/cardservices software interface. To assure full compatibility with industry-standard socket/cardservices software and PC Card applications, the register set in the PD6710 and PD6722 is a
superset of the Intel 82365SL register set.
The chips provide fully buffered PC Card interfaces, meaning that no external logic is required
for buffering signals to/from the interface, and power consumption can be controlled by limiting
signal transitions on the PC Card bus.
As of May 2001, this document replaces the Basis Communications
Corp. document CL-PD6710/’22 — ISA-to-PC-Card Host Adapters.
May 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The PD6710 or PD6722 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, May 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Contents
1.0
Product Features ........................................................................................................9
2.0
General Conventions ..............................................................................................11
2.1
3.0
Pin Information ..........................................................................................................12
3.1
3.2
3.3
3.4
4.0
Numbers and Units..............................................................................................11
Pin Diagrams.......................................................................................................13
Pin Description Conventions ...............................................................................14
Pin Descriptions ..................................................................................................16
Power-On Configuration Summary .....................................................................25
Introduction ................................................................................................................27
4.1
4.2
4.3
System Architecture ............................................................................................27
4.1.1 PC Card Basics ......................................................................................27
4.1.2 PD67XX Windowing Capabilities ...........................................................27
4.1.3 PD67XX Functional Blocks ....................................................................30
4.1.4 Interrupts ................................................................................................30
4.1.5 Alternate Functions of Interrupt Pins ......................................................31
4.1.6 General-Purpose Strobe Feature ...........................................................32
4.1.7 Voltage Sense Pins ................................................................................32
4.1.8 PD67XX Power Management ................................................................32
4.1.9 Socket Power Management Features ....................................................34
4.1.10 Write FIFO..............................................................................................35
4.1.11 Bus Sizing ..............................................................................................35
4.1.12 Programmable PC Card Timing .............................................................36
4.1.13 DMA Mode Operation for the PD6722 ...................................................36
4.1.14 Selective Data Drive for I/O Windows ....................................................36
Host Access to Registers ....................................................................................36
Power-On Setup..................................................................................................38
5.0
Register Description Conventions ....................................................................39
6.0
Operation Registers ................................................................................................41
6.1
6.2
7.0
Chip Control Registers ..........................................................................................46
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.0
Chip Revision ......................................................................................................46
Interface Status ...................................................................................................47
Power Control......................................................................................................48
Interrupt and General Control..............................................................................51
Card Status Change............................................................................................52
Management Interrupt Configuration...................................................................54
Mapping Enable ..................................................................................................55
I/O Window Mapping Registers ..........................................................................58
8.1
8.2
Datasheet
Index....................................................................................................................41
Data.....................................................................................................................44
I/O Window Control .............................................................................................58
System I/O Map 0–1 Start Address Low .............................................................59
3
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.3
8.4
8.5
8.6
8.7
9.0
Memory Window Mapping Registers ............................................................... 64
9.1
9.2
9.3
9.4
9.5
9.6
10.0
System Memory Map 0–4 Start Address Low..................................................... 64
System Memory Map 0–4 Start Address High .................................................... 65
System Memory Map 0–4 End Address Low ...................................................... 66
System Memory Map 0–4 End Address High ..................................................... 66
Card Memory Map 0–4 Offset Address Low ....................................................... 67
Card Memory Map 0–4 Offset Address High ...................................................... 68
Extension Registers ................................................................................................ 70
10.1
10.2
10.3
10.4
10.5
10.6
10.7
11.0
System I/O Map 0–1 Start Address High ............................................................ 60
System I/O Map 0–1 End Address Low .............................................................. 60
System I/O Map 0–1 End Address High ............................................................. 61
Card I/O Map 0–1 Offset Address Low ............................................................... 62
Card I/O Map 0–1 Offset Address High .............................................................. 62
Misc Control 1 ..................................................................................................... 70
FIFO Control ....................................................................................................... 72
Misc Control 2 ..................................................................................................... 72
Chip Information.................................................................................................. 74
ATA Control......................................................................................................... 75
Extended Index ................................................................................................... 77
Extended Data .................................................................................................... 77
10.7.1 Data Mask 0–1 ....................................................................................... 78
10.7.2 Extension Control 1 (PD6722 only, formerly DMA Control) ................... 78
10.7.3 Maximum DMA Acknowledge Delay (PD6722 only) .............................. 79
10.7.4 External Data (PD6722 only, Socket A, Index 2Fh) ............................... 81
10.7.5 External Data (PD6722 only, Socket A, Index 6Fh) ............................... 82
10.7.6 Extension Control 2 (PD6722 only) ........................................................ 83
Timing Registers ...................................................................................................... 84
11.1
11.2
11.3
Setup Timing 0–1 ............................................................................................... 84
Command Timing 0–1......................................................................................... 85
Recovery Timing 0–1 .......................................................................................... 86
12.0
ATA Mode Operation .............................................................................................. 88
13.0
Using GPSTB Pins for External Port Control
(PD6722 only)91
13.1
13.2
13.3
Control of GPSTB Pins ....................................................................................... 91
Example Implementations of GPSTB-Controlled Read and Write Ports............. 93
GPSTB in Suspend Mode ................................................................................... 94
14.0
VS1# and VS2# Voltage Detection .................................................................... 95
15.0
DMA Operation (PD6722 only) ............................................................................ 97
15.1
15.2
15.3
15.4
4
DMA Capabilities of the PD6722......................................................................... 97
DMA-Type PC Card Cycles ................................................................................ 97
ISA Bus DMA Handshake Signal ........................................................................ 98
Configuring the PD6722 Registers for a DMA Transfer ...................................... 98
15.4.1 Programming the DMA Request Pin from the Card ............................... 98
15.4.2 Configuring the Socket Interface for I/O ................................................. 99
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
15.4.3
15.4.4
15.4.5
15.4.6
16.0
Electrical Specifications ......................................................................................101
16.1
16.2
16.3
16.4
17.0
Preventing Dual Interpretation of DMA Handshake Signals...................99
Turning On DMA System .....................................................................100
The DMA Transfer Process ..................................................................100
Terminal Count to Card at Conclusion of Transfer ..............................100
Absolute Maximum Ratings...............................................................................101
DC Specifications ..............................................................................................101
AC Timing Specifications ..................................................................................104
ISA Bus Timing..................................................................................................104
16.4.1 Reset Timing ........................................................................................107
16.4.2 System Interrupt Timing .......................................................................107
16.4.3 General-Purpose Strobe Timing (PD6722 only)...................................108
16.4.4 Input Clock Specification ......................................................................108
16.4.5 PC Card Bus Timing Calculations ........................................................109
Package Specifications .......................................................................................121
17.1
17.2
17.3
144-Pin LQFP Package.....................................................................................121
208-Pin MQFP Package....................................................................................122
208-Pin LQFP Package.....................................................................................123
18.0
Order Numbers Example .....................................................................................124
19.0
Appendix A ...............................................................................................................125
19.1
19.2
19.3
19.4
19.5
19.6
Index
Datasheet
Register Summary Tables.................................................................................125
19.1.1 Operation Registers .............................................................................125
Chip Control Registers ......................................................................................125
I/O Window Mapping Registers.........................................................................127
Memory Window Mapping Registers.................................................................129
Extension Registers ..........................................................................................130
Timing Registers ..............................................................................................133
.......................................................................................................................................135
5
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
6
System Block Diagram........................................................................................ 10
PC Card Controller Form Factor ......................................................................... 10
PD6710 Pin Diagram ......................................................................................... 13
PD6722 Pin Diagram .......................................................................................... 14
Memory Window Organization ............................................................................ 29
I/O Window Organization .................................................................................... 29
Functional Block Diagram ................................................................................... 30
Indexed 8-Bit Register Structure ......................................................................... 37
Indexed 8-Bit Register Example.......................................................................... 37
Device/Socket/Register Index Space.................................................................. 42
Pulse Mode Interrupts ......................................................................................... 71
Selection of Acknowledge Time-out Interval ....................................................... 80
Example GPSTB Write Port (Extension Control 2 bits 4:3 are ‘10’) .................... 93
Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘01’).................... 93
VS1# and VS2# Sensing on a PD6722
(Socket B Extension Control 2 bit 3 is ‘1’) ........................................................... 96
DMA Handshake Connections to the ISA Bus
to Make the PD6722 DMA-Capable.................................................................... 98
Card DMA Request and Acknowledge Handshake with Terminal Count ........... 99
Bus Timing — ISA Bus...................................................................................... 106
Reset Timing ..................................................................................................... 107
Pulse Mode Interrupt Timing ............................................................................. 108
General-Purpose Strobe Timing ....................................................................... 108
Input Clock Specification................................................................................... 109
Memory Read/Write Timing .............................................................................. 111
Word I/O Read/Write Timing ............................................................................. 113
PC Card Read/Write Timing When System Is 8-Bit (SBHE Tied High) ............ 114
Normal Byte Read/Write Timing........................................................................ 115
16-Bit System to 8-Bit I/O Card: Odd Byte Timing ............................................ 116
DMA Read Cycle Timing................................................................................... 117
DMA Write Cycle Timing ................................................................................... 119
DMA Request Timing ........................................................................................ 120
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Datasheet
ISA Bus Interface Pins ........................................................................................16
Socket Interface Pins ..........................................................................................20
General-Purpose Strobe / Voltage Sense Pins ...................................................24
Power Control Pins..............................................................................................24
Power and Ground Pins ......................................................................................25
Pin Usage Summary ...........................................................................................25
Chip Configuration at Power-up for Socket Support ...........................................26
PD67XX Power-Management Modes .................................................................34
16-Bit Mode Operation ........................................................................................35
8-Bit Mode Operation ..........................................................................................35
Index Registers ...................................................................................................42
Enabling of Socket Power Controls.....................................................................49
Enabling of Outputs to Card Socket ....................................................................49
Maximum DMA Acknowledge Delay Register Values.........................................80
Functions of Socket A External Data Register ....................................................81
Functions of Socket B External Data Register (PD6722 only) ............................82
ATA Pin Cross-Reference ...................................................................................88
Registers for Control and Data of GPSTB Pins...................................................91
Four Card Cycle Types for DMA-Type PC Card Interface ..................................97
General DC Specifications ................................................................................101
PC Card Bus Interface DC Specifications .........................................................101
ISA Bus Interface DC Specifications .................................................................102
Power Control Interface (+5V Powered) DC Specifications ..............................103
Operating Current Specifications ......................................................................103
List of AC Timing Specifications........................................................................104
ISA Bus Timing..................................................................................................104
Reset Timing .....................................................................................................107
Pulse Mode Interrupt Timing .............................................................................107
General-Purpose Strobe Timing........................................................................108
Input Clock Specification ...................................................................................108
Memory Read/Write Timing (Word Access) .....................................................111
Word I/O Read/Write Timing ............................................................................112
PC Card Read/Write Timing when System Is 8-Bit ..........................................113
Normal Byte Read/Write Timing.......................................................................114
16-Bit System to 8-Bit I/O Card: Odd Byte Timing ............................................115
DMA Read Cycle Timing (PD6722 only) ..........................................................116
DMA Write Cycle Timing (PD6722 only) ..........................................................118
DMA Request Timing (PD6722 only) ...............................................................119
7
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Revision History
8
Revision
Date
1.0
May 2001
Description
Initial release.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
1.0
Product Features
•
•
•
•
Single-chip PC Card (PCMCIA) controllers
•
•
•
•
Automatic Low-Power Dynamic mode for lowest active power consumption
•
•
•
•
•
•
•
•
•
•
Programmable card access cycle timing
Direct connection to ISA (PC AT) bus and one or two PC Card sockets
Compliant with PC Card Standard, PCMCIA 2.1, and JEIDA 4.1
82365SL-compatible register set,
ExCA-compatible
Programmable Suspend mode
Hardware-enabled Super Suspend mode
Five programmable memory windows per socket and two programmable I/O windows per
socket
8- or 16-bit system bus interface
8- and 16-bit PC Card interface support
PCMCIA-ATA and ture-IDE disk interface support
DMA support (PD6722)
Card-voltage sense support
PC Card activity indicator
Mixed-voltage operation (3.3/5.0 V)
Single-socket interface: 144-pin LQFP for smallest form factor (PD6710)
Dual-socket interface: 208-pin MQFP or LQFP (PD6722)
Embedded and Mobile Systems Design Priorities
Supporting Features
• Single-chip solutions
• Small Form Factor
• No external buffers for host or socket
• Efficient board layout
• Automatic Low-Power Dynamic mode
• Minimum Power Consumption
• Hardware- and software-controlled Suspend
modes
• Mixed-voltage operation
• Write cache
• High Performance
• Programmable timing supports more cards,
faster reads and writes
• Automatic bus sizing for 8- or 16-bit
• DMA available with the PD6722
• Hardware and Software Compatibility
Datasheet
• Compliant with PC Card Standard, PCMCIA 2.1,
and JEIDA 4.1
• 82365SL A-step register-compatible,
ExCA-compatible
9
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 1. System Block Diagram
PC
Ca
PC CARD SOCKET 1
rd
..
. ....
..... .
.......
.....
.......
......
. ....
...... .
. ....
...... .
PD6710
144-Pin
PC CARD SOCKET 2
(PD6722)
Ca
PD6722
PC
ISA (AT)
BUS
rd
208-Pin
.
. .....
..... .
. .....
......
. .... .
. .....
..... .
. .....
..... .
.......
Figure 2. PC Card Controller Form Factor
1 9/16"
1 3/8"
Card
10
PD6710
144-Pin LQFP
and
VPP
Switching
Circuitry
VCC
1 1/4"
1"
Card
VCC
PD6722
208-Pin
MQFP or LQFP
and
VPP
Switching
Circuitry
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
2.0
General Conventions
The following general conventions apply to this document.
Throughout this document, PD67XX means PD6710 and PD6722.
Bits within words and words within various memory spaces are generally numbered with a 0 (zero)
as the least-significant bit or word. For example, the least-significant bit of a byte is bit 0, while the
most-significant bit is bit 7.
In addition, number ranges for bit fields and words are presented with the most-significant value
first. Thus, when discussing a bit field within a register, the bit number of the most-significant bit is
written first, followed by a colon (:) and then the bit number of the least-significant bit; as in,
bits 7:0.
In this document, the names of the PD67XX internal registers are boldfaced. For example, Chip
Revision and Power Control are register names. The names of bit fields are written with initial
uppercase letters. For example, Card Power On and Battery Voltage Detect are bit field names.
2.1
Numbers and Units
The unit Kbyte designates 1024 bytes (210). The unit Mbyte designates 1,048,576 bytes (220). The
unit Gbyte designates 1,073,741,824 bytes (230). The unit Hz designates hertz. The unit kHz
designates 1000 Hz. The unit MHz designates 1,000,000 Hz. The unit ms designates millisecond.
The unit µs designates microsecond. The unit ns designates nanosecond. The unit mA designates
milliampere. The unit V immediately following a number designates volt.
Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For
example, 14h and 03CAh are hexadecimal numbers.
Binary numbers are enclosed in single quotation marks when in text. For example, ‘11’ is a binary
number.
Numbers not appended with an h nor enclosed by single quotation marks are decimal.
In addition, a capital letter X is used within numbers to indicate digits ignored by the PD67XX
within the current context. For example, ‘101XX01’ is a binary number with bits 3:2 ignored.
Datasheet
11
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
3.0
Pin Information
The PD6710 is available in a 144-pin VQFP (very tight-pitch quad flat pack) component package
and the PD6722 is available in either a 208-pin PQFP (plastic quad flat pack) component package
or a 208-pin VQFP component package. The interface pins can be divided into five groups:
•
•
•
•
•
ISA (or ISA-like) bus interface pins
PC Card socket interface pins (one or two sets)
General-purpose strobe / voltage sense pins
Power control pins
Power and ground pins
Refer to Figure 3 for the PD6710 and Figure 4 for the PD6722 pin diagrams. The pin assignments
for the groups of interface pins are shown in Table 1 through Table 5.
12
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
3.1
Pin Diagrams
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
SA6
SA5
SA4
ALE
SA3
SA2
CLK
SA1
SA0
MEMCS16*
SBHE*
IOCS16*
LA23
IRQ10
LA22
IRQ11
LA21
CORE_VDD
IRQ12/LED_OUT*
LA20
IRQ15/RI_OUT*
LA19
IRQ14
LA18
LA17
MEMR*
MEMW*
SD8
SD9
SD10
GND
SD11
ISA_VCC
SD12
SD13
SD14
Figure 3. PD6710 Pin Diagram
IRQ3
SA7
IRQ4
SA8
IRQ5
SA9
SA10
IRQ7
SA11
SA12
REFRESH*
SA13
SA14
SA15
SA16
IOR*
IOW*
AEN
IOCHRDY
GND
SD0
SD1
ZWS*
SD2
GND
SD3
ISA_VCC
SD4
SD5
ISA_VCC
PD6710
144-Pin LQFP
+5V
SOCKET_VCC
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
SD15
-CD2
WP/-IOIS16
D10
D2
D9
D1
D8
D0
BVD1/-STSCHG/-RI
A0
BVD2/-SPKR/-LED
A1
A2
-INPACK
A3
-WAIT
GND
A4
SOCKET_VCC
RESET
A5
A6
A25
A7
A24
A12
A23
A15
A22
A16
A21
RDY/-IREQ
A20
-WE
+5V
VPP_PGM
VPP_VCC
-VPP_VALID
-VCC_3
-VCC_5
5V_DET
-REG
D3
-CD1
D4
D11
D5
D12
D6
CORE_VDD
D13
SOCKET_VCC
D7
GND
D14
-CE1
D15
A10
-CE2
-OE
A11
-IORD
A9
-IOWR
A8
A17
A13
A18
A14
A19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IRQ9
SD6
SD7
PWRGOOD
SPKR_OUT*/C_SEL
-INTR
N/C
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Datasheet
13
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
ISA_VCC
B_SOCKET_VCC
PD6722
208-Pin MQFP or LQFP
A_SOCKET_VCC
+5V
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
B_A22
B_A16
B_A21
B_RDY/-IREQ
B_A20
B_-WE
B_A19
B_A14
B_A18
B_A13
B_A17
B_A8
B_-IOWR
B_A9
B_-IORD
B_A11
B_SOCKET_VCC
B_-OE
B_-CE2
B_A10
B_D15
B_-CE1
B_D14
B_D7
B_D13
GND
B_D6
B_D12
B_D5
B_D11
B_D4
B_-CD1
B_D3
B_-REG
GND
A_-CD2
A_WP/-IOIS16
A_D10
A_D2
A_D9
A_D1
A_D8
A_D0
A_BVD1/-STSCHG/
A_A0
A_BVD2/-SPKR/-LE
A_A1
A_A2
A_-INPACK
A_A3
A_-WAIT
A_A4
A_VPP_PGM
A_VPP_VCC
-VPP_VALID
A_-VCC_3
A_-VCC_5
A_GPSTB
B_GPSTB
A_-REG
A_D3
A_-CD1
A_D4
A_D11
A_D5
A_D12
A_D6
A_D13
A_D7
A_D14
A_-CE1
A_D15
A_A10
A_-CE2
A_-OE
A_SOCKET_VCC
A_A11
A_-IORD
CORE_VDD
A_A9
A_-IOWR
A_A8
GND
A_A17
A_A13
A_A18
A_A14
A_A19
A_-WE
A_A20
A_RDY/-IREQ
A_A21
A_A16
A_A22
A_A15
A_A23
A_A12
A_A24
A_A7
A_A25
A_A6
A_A5
A_RESET
A_SOCKET_VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
LA23
IOCS16*
SBHE*
MEMCS16*
SA0
SA1
CLK
SA2
SA3
ALE
SA4
SA5
SA6
IRQ3
SA7
IRQ4
SA8
IRQ5
SA9
SA10
IRQ7
SA11
SA12
REFRESH*
SA13
SA14
SA15
SA16
IOR*
IOW*
AEN
IOCHRDY
SD0
SD1
ZWS*
GND
SD2
SD3
ISA_VCC
SD4
SD5
IRQ9
SD6
SD7
PWRGOOD
KR_OUT*/C_SEL
-INTR
B_VPP_PGM
B_VPP_VCC
B_-VCC_3
B_-VCC_5
+5V
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
IRQ10
LA22
IRQ11
LA21
IRQ12/LED_OUT*
LA20
IRQ15/RI_OUT*
LA19
IRQ14
LA18
LA17
MEMR*
MEMW*
SD8
SD9
SD10
GND
SD11
ISA_VCC
SD12
SD13
SD14
SD15
CORE_VDD
B_-CD2
B_WP/-IOIS16
B_D10
B_D2
B_D9
B_D1
B_D8
B_D0
B_BVD1/-STSCHG/-RI
B_A0
B_BVD2/-SPKR/-LED
B_A1
B_A2
B_-INPACK
B_A3
B_SOCKET_VCC
B_-WAIT
B_A4
B_RESET
B_A5
B_A6
GND
B_A25
B_A7
B_A24
B_A12
B_A23
B_A15
Figure 4. PD6722 Pin Diagram
3.2
Pin Description Conventions
The following conventions apply to the pin description tables in “Pin Descriptions” on page 16:
• A dash (-) at the beginning of a pin name indicates an active-low signal for the PC Card bus.
14
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
• An asterisk (*) at the end of a pin name indicates an active-low signal for the ISA bus or that is
a general interface for the PD67XX.
• Pins marked with a dagger (†) in the pin description tables can be switched between CMOS
and TTL input levels when CORE_VDD is powered at 5 volts. All other pins use CMOS input
levels when CORE_VDD is powered at 5 volts and TTL input levels when powered at 3.3
volts.
• A pin name ending in bracketed digits separated by a colon [n:n] indicates a multi-pin bus.
• The pin number (Pin Number) column indicates the package pin that carries the listed signal.
Note that multi-pin buses are listed with the first pin number corresponding to the mostsignificant bit of the bus. For example, pin numbers 123:120, 118, 117, 115, 114, 112, 110,
108:106, 104, 103, 101, and 100 are associated with ISA Bus Address Input and Data Input/
Output pins SA[16:0] and indicate that:
— SA16 is pin 123
— SA15 is pin 122
— SA0 is pin 100
• The quantity (Qty.) column indicates the number of pins used (per socket where applicable).
• The I/O-type code (I/O) column indicates the input and output configurations of the pins on
the PD67XX.The possible types are defined below.
• The power-type code (Pwr.) column indicates the output drive power source for an output pin
or the pull-up power source for an input pin on the PD67XX. The possible types are defined
below.
I/O Type
Datasheet
Description
I
Input pin
O
Constant-driven output pin
I/O
Input/output pin
O-OD
Open-drain output pin
O-TS
Tristate output pin
-PU
An internal pull-up resistor is present
GND
Ground pin
PWR
Power pin
Power Type
Output or Pull-up Power Source
1
+5V: powered from a 5.0-volt power supply
in most systems (see description of +5V pin
in Table 5)
2
A_SOCKET_VCC: powered from the Socket
A VCC supply connecting to PC Card pins 17
and 51 of Socket A
15
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Note:
Power Type
Output or Pull-up Power Source
3
B_SOCKET_VCC: powered from the Socket
B VCC supply connecting to PC Card pins 17
and 51 of Socket B
4
ISA_VCC: powered from the ISA bus power
supply
5
CORE_VDD: usually powered from the
lowest available power supply for lowest
power consumption, which in most systems
is 3.3 volts
All pin inputs are referenced to CORE_VDD, independent of their output supply voltage.
The drive-type (Drive) column describes the output drive-type of the pin (see DC specifications in
“Electrical Specifications” on page 101 for more information). Note that the drive type listed for an
input-only (I) pin is not applicable (–).
3.3
Table 1.
Pin Descriptions
ISA Bus Interface Pins (Sheet 1 of 4)
Pin Number
Pin Name
Description
Qty.
I/O
Pwr.
Drive
157, 155, 153,
151, 149, 147,
146
7
I
4
–
123:120, 118,
117, 115, 114,
112, 110,
108:106, 104,
103, 101, 100
184:181, 179,
178, 176, 175,
173, 171,
169:167, 165,
164, 162, 161
17
I
4
–
71, 73–75, 77,
79–81, 140,
139, 137, 136,
134, 132, 130,
129
134–137, 139,
141–143, 200,
199, 197, 196,
194, 193, 190,
189
16
I/O
4
12 mA
98
159
1
I
4
–
PD6710
PD6722
LA[23:17]
ISA Bus Address Input: Connect to ISA
signals LA[23:17] or, for systems limited to
1-Mbyte address space, tie ALE high,
ground LA[23:20] and connect LA[19:17] to
ISA signals SA[19:17].
96, 94, 92, 89,
87, 85, 84
SA[16:0]
ISA Bus Address Input: Connect to ISA
signals SA[16:0].
SD[15:0]
ISA Bus Data Input/Output: These pins are
used to transfer data during a memory or I/O
cycle. Connect to ISA signals SD[15:0].
For 8-bit system buses, leave SD[15:8]
unconnected.
SBHE*
Byte High Enable: This input is used in
conjunction with SA[0] to specify the width
and alignment of a data transfer. Connect to
ISA signal SBHE*.
For 8-bit system buses, pull up connect to
ISA_VCC supply.
IOR*
I/O Read: This input indicates that a host
I/O read cycle is occurring. Connect to ISA
signal IOR*.
124
185
1
I
4
–
IOW*
I/O Write: This input indicates that a host I/O
write cycle is occurring. Connect to ISA
signal IOW*.
125
186
1
I
4
–
16
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 1.
ISA Bus Interface Pins (Sheet 2 of 4)
Pin Number
Pin Name
Description
PD6710
PD6722
Qty.
I/O
Pwr.
Drive
MEMR*
Memory Read: This input indicates that a
host memory read cycle is occurring.
Connect to ISA signal MEMR*.
83
145
1
I
4
–
MEMW*
Memory Write: This input indicates that a
host memory write cycle is occurring.
Connect to ISA signal MEMW*.
82
144
1
I
4
–
REFRESH*
Refresh: This input indicates a memory
refresh cycle is occurring and will cause the
PD67XX to ignore memory accesses on the
bus. Connect to ISA signal REFRESH*.
119
180
1
I
4
–
ALE
Address Latch Enable: A high on this input
indicates a valid memory address on the
LA[23:17] bus lines. Connect to ISA signal
BALE.
105
166
1
I
4
–
PWRGOOD
Power Good: The PD67XX will be reset
when the POWERGOOD input is low.
Connect to the POWERGOOD signal from
the system power supply; or, if not available,
connect to inverted RESETDRV signal from
ISA bus.
141
201
1
I
4
–
126
187
1
I
4
–
MEMCS16*
Memory Select 16: This output is an
acknowledge of 16-bit-wide access support
and is generated by the PD67XX when a
valid 16-bit-word-accessible memory
address has been decoded. Connect to ISA
signal MEMCS16*.
99
160
1
O-OD
4
16 mA
IOCS16*
I/O Select 16: This output is an
acknowledge for 16-bit-wide access support
and is generated by the PD67XX when a
valid 16-bit word accessible I/O address has
been decoded. Connect to ISA signal
IOCS16*.
97
158
1
O-OD
4
16 mA
IOCHRDY
I/O Channel Ready: This output is driven
low by the PD67XX to lengthen host cycles.
Connect to the ISA bus IOCHRDY signal.
127
188
1
O-TS
4
16 mA
AEN
Address Enable: This is an input from the
host CPU bus signal that distinguishes
between DMA and non-DMA bus cycles.
This input should be high for a DMA cycle
and will cause the PD67XX to ignore IOR*
and IOW* except when a PD6722 is
configured for DMA and its DREQ (IRQ10)
and DACK* (IRQ9) signals are active.
Connect to ISA signal AEN.
When PD67XX is in Suspend mode (see
“Misc Control 2” on page 72), pull this input
high during system power-down for lowest
power consumption.
Datasheet
17
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 1.
ISA Bus Interface Pins (Sheet 3 of 4)
Pin Number
Pin Name
Qty.
I/O
Pwr.
Drive
148, 154, 177,
174, 172, 170
6
O-TS
4
2 mA
138
198
1
I/O-TS
4
2 mA
95
156
1
O-TS
4
2 mA
Interrupt Request 12 / LED Output: In
default IRQ mode this output indicates an
interrupt request from one of the cards, and
is connected to the ISA bus IRQ12 signal.
When the Drive LED Enable bit (see “Bit 4
— Drive LED Enable” on page 73) is set,
this output becomes an open-drain driver for
a disk-active LED (see ATA Control
register bit 1) or PC Card activity LED (see
Extension Control 1 register bit 2).
90
152
1
4
12 mA
IRQ15/
RI_OUT*
Interrupt Request 15 / Ring Indicate
Output: In IRQ mode this output indicates
an interrupt request from one of the cards.
When the IRQ15/RI_OUT* Is RI Out bit (see
“Bit 7 — IRQ15 Is RI Out” on page 74) is set
to ‘1’, this output is the -RI signal from the
corresponding PC Card.
88
150
1
O-TS
4
2 mA
-INTR
Interrupt: This output indicates a
management interrupt. This should be
connected to the system processor’s SMI or
NMI interrupt input, depending on the type
of processor used.
143
203
1
O-TS
4
2 mA
ZWS*
Zero Wait State: This output is connected
to the ISA ZWS (0WS) signal. It is driven low
by the PD67XX when it is able to complete
the current memory access cycle in zero
wait states.
131
191
1
O-OD
4
16 mA
IRQ[14, 11, 7,
5:3]
Description
Interrupt Request: These outputs indicate
programmable interrupt requests generated
from any of a number of card actions.
Although there is no specific mapping
requirement for connecting interrupt lines
from the PD67XX to the system, a common
use is to connect these pins to the
corresponding ISA signal names in the
system.
PD6710
PD6722
86, 93, 116,
113, 111, 109
Interrupt Request 9: In default mode this
output indicates an interrupt request from
one of the cards.
IRQ9
When the PD6722 is in DMA mode (see
Misc Control 2, bit 6), IRQ9 becomes an
input and is connected to the ISA bus
DACK* line corresponding to the ISA bus
DREQ line that the IRQ10 pin is connected
to. In DMA mode this signal is active-low.
Interrupt Request 10: In IRQ mode this
output indicates an interrupt request from
one of the cards.
IRQ10
IRQ12/
LED_OUT*
18
When the PD6722 is in DMA mode (see
Misc Control 2, bit 6), IRQ10 is the DREQ
to be connected to DREQ0, 1, 2, 3, 5, 6, 7 of
the ISA bus. In DMA mode this signal is
active-high.
O-TS
or
O-OD
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 1.
ISA Bus Interface Pins (Sheet 4 of 4)
Pin Number
Pin Name
Description
Qty.
Pwr.
Drive
4
12 mA
I
4
–
1
I
1
–
2
PWR
–
–
PD6710
PD6722
142
202
1
102
163
1
4
3
76, 135
138, 195
I/O
Speaker Out / Chip Select: This I/O pin can
be used as a digital output to a speaker to
allow a system to support a PC Card’s SPKR pin for fax/modem/voice and audio.
During reset this pin also serves as a chipconfiguration input.
If the level on this pin is low when
PWRGOOD rises, the PD6710 is configured
to support cards as a PC Card Socket 2
device, and the PD6722 is configured to
support cards as PC Card Socket 2 and
Socket 3 devices.
SPKR_OUT*/
C_SEL
If the level on this pin is high when
PWRGOOD rises, the PD6710 is configured
to support cards as a PC Card Socket 0
device, and the PD6722 is configured to
support cards as PC Card Socket 0 and
Socket 1 devices.
This pin is internally pulled up during reset
so that default configuration of the chip as a
Socket 0 (and Socket 1 for PD6722) is
facilitated. Adhere to the minimum pulsewidth timing specification for PWRGOOD to
allow the internal pull-up to operate and
ensure the default configuration. Refer to
“Bit 6 — Socket Index” on page 41 for more
information on chip configuration.
I/OPU
After reset operations have completed, this
pin defaults to high-impedance, and can
then be enabled as a totem-pole speaker
output by the setting of a card socket’s
Speaker Enable bit (Misc Control 1
register, bit 4). This output then becomes
the negative polarity XOR of each socket’s
BVD2/-SPKR/-LED input that has its
Speaker Enable bit set. For a description of
socket index values, refer to Table 11.
CLK
Clock: This input is connected to the ISA
bus OSC signal. A 14.318-MHz signal is
used to derive the internal 25-MHz clock
used for all socket timing. Alternately, a 25MHz clock source can be directly connected
and the internal synthesizer bypassed.
In default mode this is a status input that can
be used by software as an indication that the
VPP power supply is stable.
-VPP_VALID
ISA_VCC
Datasheet
When the PD6722 is in DMA mode (see
Misc Control 2, bit 6), this input is connected
to the TC (Terminal Count) signal of the ISA
bus. In DMA mode, this signal is active-high.
System Bus VCC: This supply pin can be
set to 3.3 or 5.0 V. The ISA Bus Interface pin
group (this table) operates at the voltage
applied to this pin independent of the
voltage applied to other pin groups.
19
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 2.
Socket Interface Pins (Sheet 1 of 4)
Pin Number
Pin Name1
Description2
PD6722
Qty.
I/O
Pwr.
Drive
PD6710
Socket A
Socket B
8
8
71
1
O-TS
2 or 3
2 mA
PC Card socket address outputs.
48, 46, 44,
42, 40, 38,
36, 34, 32,
41, 43, 35,
33, 45, 27,
24, 29, 31,
47, 49, 50,
53, 56, 58,
59, 61
48, 46, 44,
42, 40, 38,
36, 34, 32,
41, 43, 35,
33, 45, 25,
21, 28, 30,
47, 49, 50,
53, 55, 57,
58, 60
110, 108,
106, 104,
102, 100,
98, 96, 94,
103, 105,
97, 95,
107, 89,
85, 91, 93,
109, 112,
113, 115,
118, 120,
121, 123
26
O-TS
2 or 3
2 mA
PC Card socket data I/O signals.
23, 21, 17,
14, 12, 68,
66, 64, 19,
15, 13, 11,
9, 67, 65, 63
20, 18, 16,
14, 12, 67,
65, 63, 17,
15, 13, 11,
9, 66, 64,
62
84, 82, 80,
77, 75,
130, 128,
126, 81,
78, 76, 74,
72, 129,
127, 125
16
I/O
2 or 3
2 mA
26
23
87
1
O-TS
2 or 3
2 mA
Register Access: In Memory Card
Interface mode, this output chooses
between attribute and common
memory. In I/O Card Interface mode for
non-DMA transfers, this signal is active
(low).
-REG
For DMA cycles on the PD6722 to a
DMA-capable card, -REG is inactive
during I/O cycles to indicate a DMA
cycle to or from the PC Card.
In ATA mode, this signal is always
inactive.
A[25:0]
D[15:0] †
Output Enable: For non-DMA
transfers, this output goes active (low)
to indicate a memory read from the
socket.
-OE
During a DMA write (when -IORD is
active) this output goes low if the ISA
output TC is active (high), indicating to
the card that the system’s terminal
count signal is active. During DMA
reads (when -IOWR is active), this
output remains high.
1. 1To differentiate the sockets, all PD6722 pin names have either A_ or B_ prepended to the pin names indicated. For example,
A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.
2. 2When a socket is configured as an ATA drive interface, socket interface pin functions change. See Table 17 on page 88.
20
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 2.
Socket Interface Pins (Sheet 2 of 4)
Pin Number
Pin Name1
Description2
PD6722
Qty.
I/O
Pwr.
Drive
PD6710
Socket A
Socket B
37
37
99
1
O-TS
2 or 3
2 mA
Write Enable: For non-DMA transfers,
this signal goes active (low) to indicate
a memory write to the socket.
-WE
During a DMA read (when -IOWR is
active), this signal goes low if the ISA
output TC is active (high), indicating to
the card that the system’s terminal
count signal is active. During DMA
writes (when -IORD is active), this
output remains high.
-IORD
I/O Read: This output is driven low for I/
O reads from the socket.
28
26
90
1
O-TS
2 or 3
2 mA
-IOWR
I/O Write: This output is driven low for I/
O writes to the socket.
30
29
92
1
O-TS
2 or 3
2 mA
69
68
131
1
I-PU
2 or 3
–
57
56
119
1
I-PU
2 or 3
–
39
39
101
1
I-PU
2 or 3
–
55
54
116
1
I-PU
2 or 3
–
Write Protect / I/O Is 16-Bit: In
Memory Card Interface mode (Interrupt
and General Control register, bit 5 is
equal to ‘0’), this input is the status of
the PC card write protect switch.
WP/
-IOIS16 †
In I/O Card Interface mode, a low on
this input indicates that the I/O address
being accessed is capable of 16-bit
operation.
In DMA mode, this pin can be
programmed as the -DREQ input from
a DMA-capable PC Card.
-INPACK †
Input Acknowledge: This input
indicates to the PD67XX that the PC
Card supports I/O access at the current
address. A PC Card activates this input
during IORD cycles to which the card
can respond.
In DMA mode, this pin can be
programmed as the -DREQ input from
a DMA-capable PC Card.
RDY/
-IREQ †
Ready / Interrupt Request: In Memory
Card Interface mode, this input is
readable as the status of bit 5 of the
Interface Status register, which is
used by a PC Card to signal system
software of its ready or busy state.
In I/O Card Interface mode, this activelow input indicates an interrupt request.
-WAIT †
Wait: This input indicates to the
PD67XX that the current card access
cycle is to be extended until this signal
becomes inactive (high).
1. 1To differentiate the sockets, all PD6722 pin names have either A_ or B_ prepended to the pin names indicated. For example,
A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.
2. 2When a socket is configured as an ATA drive interface, socket interface pin functions change. See Table 17 on page 88.
Datasheet
21
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 2.
Socket Interface Pins (Sheet 3 of 4)
Pin Number
Pin Name1
Description2
PD6722
Qty.
I/O
Pwr.
Drive
PD6710
Socket A
Socket B
-CD[2:1]
Card Detect: These inputs indicate to
the PD67XX the presence of a card in
the socket. They are pulled high
internally in the chip.
70, 10
69, 10
132, 73
2
I-PU
1
–
-CE[2:1]
Card Enable: These outputs are driven
low by the PD67XX during card access
cycles to control byte/word card
access. -CE1 enables even-numbered
address bytes and -CE2 enables oddnumbered address bytes. When
configured for 8-bit cards, only -CE1 will
be active and A0 will be set to ‘1’ for
odd-byte accesses.
25, 22
22, 19
86, 83
2
O-TS
2 or 3
2 mA
RESET
Reset: This output will be high to reset
the card and low for normal operation.
To reduce power consumption of idle
cards and to prevent reset glitches to a
card, this signal is high-impedance
unless a card is fully seated in the
socket and card interface signals are
enabled.
51
51
114
1
O-TS
2 or 3
2 mA
1. 1To differentiate the sockets, all PD6722 pin names have either A_ or B_ prepended to the pin names indicated. For example,
A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.
2. 2When a socket is configured as an ATA drive interface, socket interface pin functions change. See Table 17 on page 88.
22
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 2.
Socket Interface Pins (Sheet 4 of 4)
Pin Number
Pin Name1
Description2
PD6722
Qty.
I/O
Pwr.
Drive
PD6710
Socket A
Socket B
60
59
122
1
I-PU
2 or 3
–
62
61
124
1
I-PU
2 or 3
–
18, 52
24, 52
88, 117
2
PWR
–
–
Battery Voltage Detect 2 / Speaker /
LED: In Memory Card Interface mode,
this input serves as the BVD2 or battery
warning status input.
BVD2/
-SPKR/
-LED †
In I/O Card Interface mode, this input
can be configured as a card’s -SPKR
binary audio input. For disk-drive
support, BVD2/-SPKR/-LED can also
be configured as a drive-status LED
input.
In DMA mode, this pin can be
programmed as the -DREQ input from
a DMA-capable PC Card.
Battery Voltage Detect 1 / Status
Change / Ring Indicate: In Memory
Card Interface mode, this input serves
as BVD1 (Battery Dead Status) input.
BVD1/
-STSCHG/
-RI †
SOCKET_
VCC
In I/O Card Interface mode, this input is
the -STSCHG input, which indicates to
the PD67XX that the card’s internal
status has changed. In I/O Card
Interface mode, this input can
alternately be used as -RI ring indicate
when IRQ15/RI_OUT* is configured for
RI Out (see “Bit 7 — IRQ15 Is RI Out”
on page 74).
Connect these pins to the VCC supply
of the socket (pins 17 and 51 of the
respective PC Card socket). These pins
can thus be 0, 3.3, or 5 V, depending
on card presence, card type, and
system configuration. The socket
interface outputs (listed in this table) will
operate at the voltage applied to these
pins, independent of the voltage
applied to other PD67XX pin groups.
1. 1To differentiate the sockets, all PD6722 pin names have either A_ or B_ prepended to the pin names indicated. For example,
A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.
2. 2When a socket is configured as an ATA drive interface, socket interface pin functions change. See Table 17 on page 88.
Datasheet
23
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 3.
General-Purpose Strobe / Voltage Sense Pins
Pin Number
Pin Name
Description
PD6722
Qty.
I/O
Pwr.
Drive
PD6710
Socket A
Socket B
GPSTB
General-Purpose Strobe: Connect
A_GPSTB to pin 43 and B_GPSTB to
pin 57 on PC Card socket. This pin can
be used with external logic to sense
pins VS1 and VS2 of the socket. It is
only available on the PD6722.1, 2
–
6
7
1
I-PU/
OOC
1
2 mA
5V_DET
This status input is used to detect 5 V/
3.3 V on PCMCIA pin 57.
7
–
–
1
I-PU
1
N/A
1. General-purpose strobe controlled by ‘Socket A’ (index 2Eh/2Fh) Extension Control 2 register at extended index 0Bh.
2. General-purpose strobe controlled by ‘Socket B’ (index 6Eh/6Fh) Extension Control 2 register at extended index 0Bh.
Table 4.
Power Control Pins
Pin Number
Pin Name
PD6722
Description
PD6710
Socket A
Socket B
Qty
.
I/O
Pwr.
Drive
VPP_VCC
This output is used to enable the socket
VCC supply onto the VPP pin. This pin is
mutually exclusive with VPP_PGM.
3
2
205
1
O
1
12
mA
VPP_PGM
This output is used to enable the
programming voltage supply onto the
VPP pin. This pin is mutually exclusive
with VPP_VCC.
2
1
204
1
O
1
12
mA
-VCC_3
This output is used to enable a 3.3V
supply onto the VDD socket. This pin is
mutually exclusive with -VCC_5.
5
4
206
1
O
1
12
mA
-VCC_5
This output is used to enable a 5V
supply onto the VDD socket. This pin is
mutually exclusive with -VCC_3.
6
5
207
1
O
1
12
mA
24
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 5.
Power and Ground Pins
Pin Number
Pin Name
Description
Qty.
I/O
Pwr.
Drive
208
1
PWR
–
–
PD6710
PD6722
1
+5V
This pin is connected to the system’s 5-volt
power supply. In systems where 5 volts is not
available, this pin can be connected to the
system’s 3.3-volt supply (but 5-volt-only PC
Cards will not be supported).
CORE_VDD
This pin provides power to the core circuitry of
the PD67XX. It can be connected to either a
3.3- or 5-volt power supply, independent of the
operating voltage of other interfaces. For power
conservation on a system with a 3.3-volt supply
available, this pin should be connected to the
3.3-volt supply even if there is no intention of
operating other interfaces on the device at less
than 5 volts.
16, 91
27, 133
2
PWR
–
–
GND
All ground pins should be connected to system
ground.
20, 54, 72, 78,
128, 133
31, 70, 79,
111, 140, 192
6
GND
–
–
Table 6 below summarizes the pin usage.
Table 6.
Pin Usage Summary
Pin Quantity
Pin Group
PD6710
PD6722
ISA bus interface pins
69
69
Socket interface pins
60
120
General-purpose strobe pins
0
2
Voltage sense pins
1
0
N/C
1
0
Power control pins
4
8
Power and ground pins
9
9
144
208
Total:
3.4
Power-On Configuration Summary
On the rising edge of PWRGOOD, the PD67XX latches the configuration pin SPKR_OUT*/
C_SEL to determine which sockets are addressed by this device. A ‘1’ on the SPKR_OUT*/
C_SEL pin will cause the device to address Socket 0 (and Socket 1 for the PD6722). A ‘0’ on this
pin will cause the device to address Socket 2 (and Socket 3 for the PD6722).
Datasheet
25
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 7.
Chip Configuration at Power-up for Socket Support
SPKR_OUT*/C_SEL Level
at Rising Edge of
PWRGOOD
High
Low
26
PD6710
Socket Interface Support
PD6722
Socket A
Interface Support
Socket B
Interface Support
PC Card Socket 0
PC Card Socket 0
PC Card Socket 1
3E0 Index 00h–3Fh
3E0 Index 00h–3Fh
3E0 Index 40h–7Fh
PC Card Socket 2
PC Card Socket 2
PC Card Socket 3
3E0 Index 80h–BFh
3E0 Index 80h–BFh
3E0 Index C0h–FFh
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
4.0
Introduction
4.1
System Architecture
This section describes PC Card basics, windowing, interrupts, PD67XX power management,
socket power management, write FIFO, bus sizing, programmable PC Card timing, and ATA and
DMA mode operation.
4.1.1
PC Card Basics
PCMCIA is an abbreviation for Personal Computer Memory Card International Association. PC
Card Standard is a standard for using memory and I/O devices as insertable, exchangeable
peripherals for PCs (personal computers) and handheld computers. For simpler end-user and
vendor implementation of the standard, systems employing PC Card Standard should also be
backward-compatible with industry-standard PC addressing.
Note:
The PD67XX is backward-compatible with PCMCIA standards 1.0, 2.0, 2.01, and 2.1. The
PD67XX is also compatible with JEIDA 4.1 and its earlier standards corresponding with the
PCMCIA standards above.
The memory information for memory-type PC Cards must be mapped into the system memory
address space. This is accomplished with a ‘windowing’ technique that is similar to expanded
memory schemes already used in PC systems (for example, LIM 4.0 memory manager).
PC Cards can have attribute and common memory. Attribute memory is used to indicate to host
software the capabilities of the PC Card, and it allows host software to change the configuration of
the card. Common memory can be used by host software for any purpose (such as flash file system,
system memory, and floppy emulation).
I/O-type PC Cards, such as modem network cards, should also be directly addressable, as if the
cards were I/O devices plugged into the system bus. For example, it would be highly desirable to
have a PC Card modem accessible to standard communications software as if it were at a COM
port. For COM1, this would require that the modem be accessed at system I/O address 3F8h–3FFh.
The method of mapping a PC Card I/O address into anticipated areas of ISA I/O space is done
similarly to memory windowing.
I/O-type PC Cards usually have interrupts that need to be serviced by host software. For the
example of a modem card accessed as if at COM1, software would expect the modem to generate
interrupts on the IRQ4 line. To be sure all interrupts are routed as expected, the PD67XX can steer
the interrupt from the PC Card to one of several standard PC interrupts (see “Interrupts” on page 30
and the “Interrupt and General Control” on page 51).
4.1.2
PD67XX Windowing Capabilities
For full compatibility with existing software, and to ensure compatibility with future memory cards
and software, the PD67XX provides five programmable memory windows per socket and two
programmable I/O windows per socket. These windows can be used by an inserted PC Card to
access ISA memory and I/O space.
Datasheet
27
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Having five memory windows per socket allows a memory-type card to be accessed through four
memory windows programmed for common memory access (allowing PC-type expandedmemory-style management), leaving the fifth memory window available to be programmed to
access the card’s attribute memory without disrupting the common memory in use.
Each of the five memory windows has several programming options, including:
Memory
Window Option
Description
Enabled
Each of the five memory windows can be individually enabled. Disabled windows are not responded to.
Start Address
The starting address of the window is programmable on 4-Kbyte boundaries starting at 64 Kbytes
(1000h) with a maximum address of 16 Mbyte.
End Address
The ending address of the window is programmable on 4-Kbyte boundaries starting at 64 Kbytes
(1000h) with a maximum address of 16 Mbyte. Only memory accesses between the starting and ending
address are responded to.
Offset Address
The offset address is added to the ISA address to determine the address for accessing the PC Card.
This allows the addresses in the PC Card address space to be different from the ISA address space.
Data Size
The size of accesses can be set manually to either 8 or 16 bits.
Timing
The timing of accesses (Setup/Command/Recovery) can be set by either of two timing register sets:
Timer Set 0 or Timer Set 1.
Register Access
Setting
The -REG pin can be enabled on a per-window basis so that any of the windows can be used for
accessing attribute memory.
Write Protect
If the window is programmed to be write-protected, then writes to the memory window are ignored (reads
are still performed normally).
Each of the two I/O windows has several programming options, including:
I/O
Window Option
Description
Enabled
Each of the two I/O windows can be individually enabled.
Start Address
The starting address of the window is programmable on single-byte boundaries from 0 to 64 Kbytes.
End Address
The ending address of the window is also programmable on single-byte boundaries from 0 to 64 Kbytes.
Offset Address
The offset address is added to the ISA address to determine the address for accessing the PC Card.
Auto Size
The size of accesses can be set automatically, based on the PC Card -IOIS16 signal.
Data Size
The size of accesses can be set manually to either 8 or 16 bits, overriding the Auto Size option.
Timing
The timing of accesses (Setup/Command/Recovery) can be set by either of two timing register sets:
Timer Set 0 or Timer Set 1.
Caution:
28
The windows of the PD67XX should never be allowed to overlap with each other or the other
devices in the system. This would cause collisions in the IOCS16*, MEMCS16*, IOCHRDY, and
SD[15:0] signals, resulting in erratic behavior.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Figure 5. Memory Window Organization
PC Card Memory Address Space
64 Mbytes
ISA Memory Address Space
16 Mbytes
Common Memory
Attribute
Memory
Card Memory Window
System Memory Map
End Address Registers
Memory Window
System Memory Map
Start Address Registers
 First 64 Kbytes

 not usable in
 most ISA systems

Card Memory Map
Offset Address Registers
NOTE: ISA memory window can map to either
common or attribute PC Card memory.
Figure 6. I/O Window Organization
PC Card I/O Address Space
64 Mbytes
Card I/O Window
System I/O Map
End Address Registers
ISA I/O Address Space
64 Kbytes
I/O Window
System I/O Map
Start Address Registers
Datasheet
Card I/O Map
Offset Address Registers
29
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
4.1.3
PD67XX Functional Blocks
Figure 7. Functional Block Diagram
Per Chip
Per Socket
Control
Address
Bus
Interface
Unit
Operation
Registers
Socket
Bus Control
Mapper
and
Offset
Socket
Timing Control
Data
Clock
INTR
IRQs
-WAIT
Control
Data
Synthesizer
Write
FIFO
Address
CD1, CD2
BVD, -STSCHG
RDY/-IREQ
Interrupt
Control
Power Control
4.1.4
WP/-IOIS16
VCC Control
VPP Control
Interrupts
The PD67XX provides ten interrupt pins that are labeled with names suggesting their mapping in
the system, though there are no hard requirements specifying the exact mapping. Typically, all ten
interrupt pins should be connected to system interrupt signals to allow maximum flexibility in
programming interrupt routing from the PD67XX.
Classes of Interrupts
The PD67XX supports two classes of interrupts:
• Socket or card interrupts initiated by the PC Card activating its RDY/-IREQ signal
• Management interrupts triggered by changes in PC Card status, including:
— Card insertion or removal
— Battery warning indicator (BVD2) change on a memory-type card
— Battery dead indicator (BVD1) or I/O-type card status change (-STSCHG)
— Ready (RDY) status change on a memory-type card
Either class of interrupts can be routed to any of the ten interrupt pins on the PD67XX.
30
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Connection of Interrupt Pins
IRQ interrupts in PC-compatible systems are not generally shared by hardware. Therefore, each
device in the system using IRQ interrupts must have a unique interrupt line. Additionally, many
software applications assume that certain I/O devices use specific IRQ signals. To allow PC Cards
with differing I/O functionalities to be connected to appropriate nonconflicting IRQ locations, the
PD67XX can steer the interrupt signal from a PC Card to any one of the ten different hardware
interrupt lines.
For some I/O-type cards, software is written so that IRQ interrupts can be shared. The PD67XX
contains unique logic that allows IRQ interrupts to be shared under software control. This is
accomplished by programming the PD67XX to alternately pulse and then three-state the desired
interrupt pin, which has been programmed as an IRQ output. This unique IRQ interrupt sharing
technique can be controlled through software so that systems incapable of IRQ sharing have no
loss of functionality.
4.1.5
Alternate Functions of Interrupt Pins
The PD67XX has two interrupt pins that can be programmed for alternate functions: IRQ12/
LED_OUT* and IRQ15/RI_OUT*. In addition, the PD6722 allows IRQ9 and IRQ10 to be
programmed for system DMA transfer handshake functions.
4.1.5.1
IRQ12 as LED_OUT* Driver
If a disk-activity or card-cycle-activity indicator is desired, IRQ12/LED_OUT* can be
programmed as an open-collector LED driver, capable of driving most common LEDs. There is no
specific bit that programs the IRQ12 pin to become an LED driver; instead, whenever a socket
interface is programmed to support a drive status LED input or is programmed to show card
activity on the LED (as described below), the IRQ12 pin becomes reconfigured as an opencollector LED driver.
The Extension Control 1 register’s LED Activity Enable bit (extended index 03h bit 2) is used to
enable the LED being used to show card activity. When this bit is set, any type of read or write
cycles to the respective socket cause the IRQ12/LED_OUT* signal to be driven low for the
duration of the card activity.
The Drive LED Enable bit (Misc Control 2 register bit 4) is used to enable the BVD2/-SPKR/LED input from an I/O-interfaced card to be interpreted as a drive LED input, where an opencollector signal driven low on this input will cause the IRQ12/LED_OUT* open-collector output to
go low.
Any combination of settings of LED Activity Enable and Drive LED Enable bits can be used on
each socket, with each type of activity being able to separately cause the LED to be illuminated.
Status from non-present or non-activated cards is automatically masked off from causing the
IRQ12/LED_OUT* signal to be driven low.
4.1.5.2
IRQ15 as RI_OUT*
If the capability to ‘wake up’ a system on an incoming phone call to a PC Card modem is desired,
it may be necessary in some systems to use a dedicated wakeup signal to the system’s SMI or NMI
controller to facilitate this instead of using the normal interrupt connections. If this is the case, the
IRQ15 connection can be reprogrammed to pass through a qualified version of an I/O interfaced
card’s -RI signal.
Datasheet
31
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
IRQ15/RI_OUT* is programmed as RI_OUT* by programming the IRQ15 Is RI Out bit (Misc
Control 2 register 1Eh bit 7) to ‘1’. Then if a particular socket supporting a modem is to have its
BVD1/-STSCHG/-RI pin passed to the IRQ15/RI_OUT* pin, that socket’s Ring Indicate Enable
bit (Interrupt and General Control register 03h bit 7) should be set to ‘1’.
When the PD67XX is configured this way, a low level at the BVD1/-STSCHG/-RI pin on an I/O
interfaced PC Card will cause the IRQ15/RI_OUT* signal to become active-low (because it is
intended to be connected to an SMI* or NMI* input on the system processor or core logic). To
prevent multiple SMI or NMI interrupts from occurring on one ring condition, the IRQ15/
RI_OUT* pin remains low until ISA bus activity resumes, indicated by the resumption of ISA bus
memory or I/O reads or writes.
4.1.5.3
IRQ9 as DACK* and IRQ10 as DRQ
When a PD6722 is to be used for DMA support, IRQ9 is programmed as a DACK* input from an
ISA bus DACK* signal selected by the system designer. Similarly, IRQ10 is programmed as an
active-high DRQ output to the ISA bus and should be connected to the system bus DRQ signal
corresponding to that used for DACK*.
IRQ9 and IRQ10 are thus redefined for DMA cycle support by the setting of the DMA System bit
(Misc Control 2 register 1Eh, bit 6) to ‘1’. Setting the DMA System bit redefines these ISA
interface signals but does not cause DMA to a card to be enabled.
4.1.6
General-Purpose Strobe Feature
The PD6722 has capability to use two pins as general-purpose strobes. This is a feature that causes
a pin programmed as a general-purpose strobe to appear in software as an extended register in the
PD6722 register set, while in reality accesses to this extended register cause the general-purpose
strobe pin to go active during the register access. The strobe can be programmed to activate on
reads or writes to this virtual extended register, allowing straightforward single-chip
implementation of an 8-bit general purpose read or write port.
“Using GPSTB Pins for External Port Control (PD6722 only)” on page 91 provides detailed
information on how this port can be used.
4.1.7
Voltage Sense Pins
The PD6710 provides a single pin to detect 5 V or 3.3 V on pin 57 of the PC Card.
The PD6722 can be simply configured for dual-socket VS1 and VS2 detection with an external
read port consisting of half of a ’244 buffer or other similar device, enabled by the B_GPSTB pin
programmed as a read port.
“VS1# and VS2# Voltage Detection” on page 95 provides detailed information on the
programming model for VS1 and VS2 detection and how connections are made to achieve this
functionality.
4.1.8
PD67XX Power Management
To provide the longest possible battery life, the PD67XX provides many power management
features, including Low-Power Dynamic mode, Suspend mode, and control of PC Card socket
power.
32
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Low-Power Dynamic mode is transparent to the ISA bus. After reset, the PD67XX is configured
for Low-Power Dynamic mode. This mode can be turned off by setting Misc Control 2 register,
bit 1 to ‘0’. When in Low-Power Dynamic mode, periods of inactivity (no activity on the PC Card
bus and system accesses to chip registers or inserted cards are no longer being performed) cause
the PD67XX to enter a low-power state where the clock is turned off to most of the chip and the PC
Card address and data lines are set to a static value. VCC and VPP power to the card is left
unchanged. When there is activity present on the PC Card bus, or the system accesses PD67XX
registers, or PC Cards are inserted or removed from the socket, the PD67XX enters its active state,
services the transaction, and then returns to its low-power state.
A Suspend mode can also be programmed. The PD67XX Suspend mode is the chip’s lowest
software-controlled power mode. The PD67XX is put into Suspend mode by setting the Misc
Control 2 register, bit 2 to ‘1’. In Suspend mode, all the internal clocks are turned off, and only
read/write access to the Index register and write access to the Misc Control 2 register is supported.
All accesses to the PC Cards are ignored when in Suspend mode. VCC and VPP power to the card is
left unchanged (the system power management software is responsible for turning off power to the
socket and entering Suspend mode). Interrupts and ring indicate signals are passed through to the
system bus when in Suspend mode. To exit Suspend mode, the Misc Control 2 register bit 2 must
be reset to ‘0’. It requires 50 ms for the PD67XX to restart the internal clock synthesizer and
become active again.
In addition to the software suspend, if the system hold’s the AEN signal of the PD67XX high, a
hardware-assisted Super-Suspend mode occurs where ISA inputs to the chip are internally shut off.
Internal in the PD67XX, the ISA inputs are ignored and floating conditions on the ISA bus will not
cause high current flow in the PD67XX ISA input receivers. Since the ISA bus inputs to the core
logic of the PD67XX are also not toggling when AEN is set high, power consumption is further
reduced. Interrupts and ring indicate signals are passed through to the system bus when in SuperSuspend mode
The PD67XX power can be further managed by controlling socket power as outlined in “Socket
Power Management Features” on page 34. Socket power can be turned on and off through software
or automatically when cards are inserted or removed. The PD67XX provides six pins per socket for
controlling external logic to switch VCC and VPP voltages on and off and for sensing a card’s
operating voltage range. Cards can be turned off when not in use.
Datasheet
33
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 8.
PD67XX Power-Management Modes
Misc Control 2 Register
Typical Power
Consumption
(CORE_VDD =
3.3 V,
ISA_VCC,
SOCKET_VCC, and
+5V = 5.0 V)
Mode Name
PWRGOOD
Level
AEN
Suspend
Mode
(Bit 2)
Low-Power
Dynamic
Mode
(Bit 1)
Low-Power
Dynamic
(Default)
High
Normal
0
1
Full functionality
< 45 mW high activity,
9–14 mW normal
system activity
Normal
High
Normal
0
0
Full functionality
< 85 mW high activity,
18 mW normal
system activity
–
8-bit access to Misc
Control 2 register.
No other register
access. No card in
socket(s).
< 2 mW
< 1 mW
9–14 mW
Suspend
High
Normal
(Hardware
Controlled)
High
Static
High
1
–
No register access.
No card in socket(s).
System bus signals
disabled (clock off).
Reset
Low1
–
–
–
No register access.
No card in socket(s).
System bus signals
disabled.
(Software
Controlled)
Super-Suspend
1
Functionality
1. IOR*, IOW*, MEMR*, and MEMW* must be held high when PWRGOOD is low to prevent manufacturing test mode outputs
from driving the system data bus
4.1.9
Socket Power Management Features
Card Removal
When a card is removed from a socket, the PD67XX by default automatically disables the VCC and
VPP supplies to the socket. If Extension Control 1 register bit 1 is ‘0’, card power is prevented
from being automatically disabled when a card is removed. The PD67XX can also be configured to
have management interrupts notify software of card removal.
Card Insertion
Power to the socket is off at reset and whenever there is no card in a socket. When a card is
detected (card detect input pins, -CD1 and -CD2, to the PD67XX become asserted low), two
independent actions can be programmed to occur.
If the PD67XX has been set for automatic power-on (Power Control register bits 4 and 5 are both
‘1’), the PD67XX automatically enables the socket VCC supply (and, if so programmed, the VPP
supply).
If the PD67XX has been programmed to cause management interrupts for card-detection events,
assertion of -CD1 and -CD2 to the PD67XX causes a management interrupt to inform system
software that a card was inserted. In the case of manual power detection (Power Control register
34
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
bit 5 is ‘0’), system software can determine the card’s operating voltage range and then power-up
the socket and initialize the card (or simply initialize the card if programmed for automatic poweron (Power Control register bit 5 is ‘1’ and Extension Control 1 register bit 1 is ‘1’)).
4.1.10
Write FIFO
To increase performance when writing to PC Cards, two, independent, four-word-deep write
FIFOs are used. Writes to PC Cards will complete without wait states until the FIFO is full.
Register states should not be changed until the write FIFO is empty.
4.1.11
Bus Sizing
The PD67XX incorporates logic to automatically detect its connection to 8- or 16-bit buses. This is
accomplished by sensing SBHE* input activity. If the SBHE* pin is always high (that is, tied to
ISA_VCC), the PD67XX operates in 8-bit mode where all transfers occur on the lower data bus,
bits 7:0. Any occurrence of the SBHE* going low triggers the PD67XX to operate thereafter as a
16-bit device. 16-bit operation of the PD67XX is properly triggered when the SBHE* input is
connected to the system’s SBHE* signal. When the PD67XX is operating in 16-bit mode, all ISA
bus transactions are 16-bit whenever possible, even if installed PC cards only support 8-bit
transfers. In 16-bit mode, the signals SBHE* and SA0 are used to specify the width of the data
transfer and the location of data on the bus (which byte lane has the data) during 8-bit transfers.
The possible combinations for SBHE* and SA0 are shown in Table 9 and Table 10
Table 9.
16-Bit Mode Operation
16-Bit Mode Transfer Types
SBHE*
SA0
Word
0
0
Upper Byte/Odd Address
0
1
Low Byte/Even Address
1
0
Not Valid
1
1
.
Table 10. 8-Bit Mode Operation
8-Bit Mode Transfer Types1
SA0
Even Address
0
Odd Address
1
1. The SBHE* signal is pulled up. If the SBHE*
signal remains high, thePD67XX causes all
transfers to occur on D[7:0] only
Typically, there are three types of data transfers to and from the PD67XX:
• 16-Bit Transfer from 16-Bit Processor — The CPU puts the address on the bus. Then the
PD67XX identifies the address on the bus as either an 8- or 16-bit transfer. If the transfer is
identified as 16-bit, the host acknowledges with the appropriate signal, either MEMCS16* or
IOCS16*. Data is transferred to/from the data bus as a word on both byte lanes.
• 8-Bit Transfer from 16-Bit Processor — The CPU puts the address on the bus. Then the
PD67XX identifies the address on the bus as either an 8- or 16-bit transfer. In this case, the
transfer is identified as an 8-bit transfer. The host queries SA0 and SBHE* to determine the
Datasheet
35
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
byte lane on which the transfer is to occur. The data is transferred to/from the data bus (see
Table 9).
• 8-Bit Transfer from 8-Bit Processor — The CPU puts the address on the bus. The host
determines that it will be an 8-bit transfer since the SBHE* signal has been tied high. The
PD67XX queries SA0 to determine if the byte is odd/even. The data is transferred to/from the
Data bus (D[7:0]).
4.1.12
Programmable PC Card Timing
The Setup, Command, and Recovery time for the PC Card bus is programmable (see “Timing
Registers” on page 84). The PD67XX can be programmed to match the timing requirements of any
PC Card. There are two sets of timing registers, Timer Set 0 and Timer Set 1, that can be selected
on a per-window basis for both I/O and memory windows.
To be compatible with the 82365SL, the two timing sets are programmed at the rising edge of
PWRGOOD to include normal-wait and one-wait-state timing.
4.1.12.1
ATA Mode Operation
The PD67XX supports direct connection to AT-attached-interface hard drives. ATA drives use an
interface very similar to the IDE interface found on many popular portable computers. In this
mode, the address and data conflict with the floppy drive is handled automatically. See “ATA Mode
Operation” on page 88 for more information.
4.1.13
DMA Mode Operation for the PD6722
A slave mode Direct Memory Access (DMA) feature exists in the PD6722. To use DMA mode, the
Interrupt and General Control register, bit 5 must be set to ‘1’ to operate the PC Card in I/O
Card Interface mode. PC Card interface DMA handshake signal options must also be selected.
Refer to the description of the “Extension Control 1 (PD6722 only, formerly DMA Control)” on
page 78 as well as “DMA Operation (PD6722 only)” on page 97.
4.1.14
Selective Data Drive for I/O Windows
The PD67XX can be programmed to drive only some of the ISA bus data pins on reads from I/O
windows. This reduces data contention for I/O addresses that include more than one peripheral. In
the standard IBM PC AT, I/O map, floppy disk, and hard disk share address 3F7h. The floppy
disk drives ISA-data-bus bit 7 on a read from 3F7h, and the hard disk drives bits 6:0. To allow both
floppy disk controllers on the motherboard and hard disks on the PC Card bus (or vice versa) to
coexist, the PD67XX can be programmed through use of its Data Mask registers to disable bit 7 on
I/O reads at addresses 3F7h and 377h. This is done by programming up I/O windows to these
addresses as part of the task of configuring a socket for ATA drive support (see “Extended Data” on
page 77). Alternately, all bits except bit 7 can also be disabled to allow the opposite case.
4.2
Host Access to Registers
The PD67XX registers are accessed through an 8-bit indexing mechanism. An index register
scheme allows a large number of internal registers to be accessed by the CPU using only two I/O
addresses.
36
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
The Index register (see “Operation Registers” on page 41) is used to specify which of the internal
registers the CPU will access next. The value in the Index register is called the Register Index.
This number specifies a unique internal register. The Data register is used by the CPU to read and
write the internal register specified by the Index register.
Figure 8. Indexed 8-Bit Register Structure
Internal Registers
FFh
FEh Register
•
Indexes
•
•
02h
01h
00h
High Byte
Data
3E1h
Low Byte
Index
3E0h
I/O Addresses
Figure 9. Indexed 8-Bit Register Example
Internal Registers
The following code segment demonstrates use
of an indexed 8-bit register:
Register
Indexes
mov dx, 3E0h
mov al, 02h
mov ah, 3Ch
3Ch
out dx, ax
02h
AH
AL
3Ch
3E1h
02h
3E0h
I/O Addresses
Double-Indexed Registers
The PD67XX has Extension registers that add to the functionality of the 82365SL-compatible
register set. Within the Extension registers is an Extended Index register and Extended Data
register that provide access to more registers. The registers accessed through Extended Index and
Extended Data are thus double indexed. The example below shows how to access the Extension
Control 1 register, one of the double-indexed registers.
;Write to Extension Control 1
;Constants section
Extended_Index
EQU
Index_Reg
EQU
Ext_Cntrl_1
EQU
PD67XX_Index
EQU
register example
2Eh
2Fh
03h
3E0h
;Code section
mov
dx, PD67XX_Index
mov
al, Extended_Index
mov
ah, Ext_Cntrl_1
Datasheet
37
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
out
mov
mov
out
dx,
al,
ah,
dx,
ax
Index_Reg
user_data
ax
;Desired data to be
;written to
;extended index 03h
;Read from Extension Control 1 register example
;Code section
mov
mov
mov
out
mov
out
inc
in
4.3
dx,
al,
ah,
dx,
al,
dx,
dx
al,
PD67XX_Index
Extended_Index
Ext_Cntrl_1
ax
Index_Reg
al
;al has extended
dx
;index 03h data
Power-On Setup
Following reset, the PD67XX must be configured by host software. The host software’s setup
procedure is different depending on its PC system configuration, in particular, the power supply
arrangement.
The application of the RESET signal (see Table 2 on page 20) on power-up causes initialization of
all the PD67XX register bits and fields to their reset values. Not all registers have reset values; only
registers with bits and fields specified to have reset values are initialized.
One bit, which is loaded on hardware reset from the SPKR_OUT*/C_SEL pin (see Table 1 on
page 16), is used to determine the socket to which the PD67XX will respond.
38
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
5.0
Register Description Conventions
Register Headings
The description of each register starts with a header containing the following information:
Header Field
Description
Register Name
Indicates the register name.
Index1
The Index value through which an internal
register in an indexed register set is accessed.
Register Per
Indicates whether the register affects both
sockets, marked chip, or an individual socket,
marked socket. If socket is indicated, there
are two registers being described, each with a
separate Index value (one for each socket, A
and B). a
Register
Compatibility
Type
Indicates whether the register is 82365SLcompatible, marked 365 or a register
extension, marked ext.
1. When the register is socket-specific, the Index value given in
the register heading is for Socket A only. For the Socket B
register on the PD6722, add 40h to the Index value of the
Socket A register.
Special Function Bits
Following is a description of bits with special functions:
Datasheet
Bit Type
Description
Reserved
These bits are Reserved and should not be
changed.
Compatibility Bit
These bits have no function on the PD67XX,
but are included for compatibility with the
82365SL register set.
0 or 1
These read-only bits are forced to either ‘0’ or
‘1’ at reset and cannot be changed.
Scratchpad Bit
These read/write bits are available for use as
bits of memory.
39
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit Naming Conventions
The following keywords are used within bit and field names:
Keyword
Description
Enable
Indicates that the function described in the
rest of the bit name is active when the bit is ‘1’.
Disable
Indicates that the function described in the
rest of the bit name is active when the bit is ‘0’.
Mode
Indicates that the function of the bit alters the
interpretation of the values in other registers.
Input
Indicates a bit or field that is read from a pin.
Output
Indicates a bit or field that is driven to a pin.
Select
Indicates that the bit or field selects between
multiple alternatives. Fields that contain
Select in their names have an indirect
mapping between the value of the field and
the effect.
Status
Indicates one of two types of bits: either readonly bits used by the PD67XX to report
information to the system, or bits set by the
PD67XX in response to an event, and can
also be cleared by the system. The system
cannot directly cause a Status bit to become
‘1’.
Value
Indicates that the bit or field value is used as a
number.
Read/Write Convention
40
Bit Access
Description
RW:n
Bit is read/write and resets to value n when
PWRGOOD is cycled.
R
Bit is read-only and setting is determined by
conditions noted. Set this bit to ‘0’, or echo
back value read.
R:n
Bit is read-only and resets to value n when
PWRGOOD is cycled. Set this bit to ‘0’, or
echo back value read.
R:n W:m
Bit is read/write and resets to value n when
PWRGOOD is cycled. Set this bit to value m
only.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
6.0
Operation Registers
The PD67XX internal registers are accessed through a pair of Operation registers — an Index
register and a Data register. The Index register is accessed at address 03E0h, and the Data register
is accessed at 03E1h.
6.1
Index
Register Name: Index
Register Per: chip
Index: n/a
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Device Index
Socket Index
Register Index
RW:0
RW:0
RW:000000
Bit 1
Bit 0
The Data register is accessed at 03E1h.
Bits 5:0 — Register Index
These bits determine which of the 64 possible socket-specific registers will be accessed when the
Data register is next accessed by the processor. Note that some values of the Register Index field
are reserved (see Table 11 on page 42).
Bit 6 — Socket Index
This bit determines which set of socket-specific registers is currently selected. When this bit is ‘0’,
a Socket A register is selected. When this bit is ‘1’, a Socket B register is selected. Note that the
PD6710 supports one socket, and the PD6722 supports two sockets.
Bit 7 — Device Index
In systems where two PD67XXs are used, this bit differentiates between them.
The Index register value determines which internal register should be accessed (read or written) in
response to each CPU access of the Data register. Each of the possible PC Card sockets is allocated
64 of the 256 locations in the internal register index space
Datasheet
41
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
.
Figure 10. Device/Socket/Register Index Space
FFh
Socket D Registers
Possible with two PD67XXs
80h
7Fh
40h
3Fh
Socket C Registers
Socket B Registers
Socket A Registers
00h
When viewed as a 8-bit value, the contents of the Index register completely specify a single
internal-register byte. For example, when the value of this register is in the range 00h–3Fh, a
Socket A register is selected (Socket Index bit is ‘0’), and when the value of this register is in the
range 40h–7Fh, a Socket B register is selected (Socket Index bit is ‘1’). This register only reads
back for Device 0. Device 1 will read back only the upper data byte when 16-bit reads occur at
3E0h.
The internal register that is accessed when the CPU reads or writes the Data register is determined
by the current value of the Index register, as follows:
Table 11. Index Registers (Sheet 1 of 3)
Index Value
Register Name
Chapter
Socket B1
Socket A
00h2
Chip Revision
Page
Number
46
Interface Status
01h
41h
47
Power Control
02h
42h
Interrupt and General Control
03h
43h
Card Status Change
04h
44h
Management Interrupt Configuration
05h
45h
54
Mapping Enable
06h
46h
55
I/O Window Control
07h
47h
58
“Chip Control
Registers” on
page 46
48
51
52
System I/O Map 0 Start Address Low
08h
48h
59
System I/O Map 0 Start Address High
09h
49h
60
System I/O Map 0 End Address Low
0Ah
4Ah
System I/O Map 0 End Address High
0Bh
4Bh
System I/O Map 1 Start Address Low
0Ch
4Ch
System I/O Map 1 Start Address High
0Dh
4Dh
60
System I/O Map 1 End Address Low
0Eh
4Eh
60
System I/O Map 1 End Address High
0Fh
4Fh
61
“I/O Window
Mapping Registers”
on page 58
60
61
59
1. Socket B is available on the dual-socket PD6722.
2. This register affects both sockets (it is not specific to either socket).
3. These registers are not available on the PD6710.
42
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 11. Index Registers (Sheet 2 of 3)
Index Value
Register Name
Chapter
Socket A
Socket B1
System Memory Map 0 Start Address Low
10h
50h
System Memory Map 0 Start Address High
11h
51h
Page
Number
64
65
“Memory Window
Mapping Registers”
on page 64
System Memory Map 0 End Address Low
12h
52h
System Memory Map 0 End Address High
13h
53h
Card Memory Map 0 Offset Address Low
14h
54h
67
Card Memory Map 0 Offset Address High
15h
55h
68
Misc Control 1
16h
56h
FIFO Control
17h
57h
System Memory Map 1 Start Address Low
18h
58h
System Memory Map 1 Start Address High
19h
59h
System Memory Map 1 End Address Low
1Ah
5Ah
System Memory Map 1 End Address High
1Bh
5Bh
Card Memory Map 1 Offset Address Low
1Ch
5Ch
Card Memory Map 1 Offset Address High
1Dh
Misc Control 2
Chip Information
System Memory Map 2 Start Address Low
5Dh
1Eh
2
1Fh
2
20h
“Extension
Registers” on
page 70
“Memory Window
Mapping Registers”
on page 64
“Memory Window
Mapping Registers”
on page 64
“Extension
Registers” on
page 70
21h
61h
System Memory Map 2 End Address Low
22h
62h
System Memory Map 2 End Address High
23h
63h
Card Memory Map 2 Offset Address Low
24h
64h
Card Memory Map 2 Offset Address High
25h
65h
64
65
66
61
67
68
72
74
66
66
68
26h
66h
Scratchpad
27h
67h
–
System Memory Map 3 Start Address Low
28h
68h
System Memory Map 3 Start Address High
29h
69h
6Ah
72
67
ATA Control
2Ah
70
65
“Memory Window
Mapping Registers”
on page 64
“Extension
Registers” on
page 70
System Memory Map 3 End Address Low
66
64
60h
System Memory Map 2 Start Address High
66
75
–
64
65
“Memory Window
Mapping Registers”
on page 64
60
System Memory Map 3 End Address High
2Bh
6Bh
Card Memory Map 3 Offset Address Low
2Ch
6Ch
66
67
Card Memory Map 3 Offset Address High
2Dh
6Dh
68
1. Socket B is available on the dual-socket PD6722.
2. This register affects both sockets (it is not specific to either socket).
3. These registers are not available on the PD6710.
Datasheet
43
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 11. Index Registers (Sheet 3 of 3)
Index Value
Register Name
Page
Number
Chapter
Socket A
Socket B1
2Eh
6Eh
Extended Index:3
Scratchpad
Data Mask 0
Data Mask 1
Extension Control 1 (formerly DMA Control)
Maximum DMA Acknowledge Delay
Reserved
External Data
Extension Control 2
77
Extended index 00h
Extended index 01h
Extended index 02h
Extended index 03h
Extended index 04h
Extended index 05h–09h
Extended index 0Ah
‘Extended index 0Bh
–
77
78
78
79
–
81
83
“Extension
Registers” on
page 70
Extended Data
2Fh
6Fh
77
System Memory Map 4 Start Address Low
30h
70h
64
System Memory Map 4 Start Address High
31h
71h
System Memory Map 4 End Address Low
32h
72h
65
“Memory Window
Mapping Registers”
on page 64
66
System Memory Map 4 End Address High
33h
73h
Card Memory Map 4 Offset Address Low
34h
74h
66
62
Card Memory Map 4 Offset Address High
35h
75h
68
Card I/O Map 0 Offset Address Low
36h
76h
62
“I/O Window
Mapping Registers”
on page 58
Card I/O Map 0 Offset Address High
37h
77h
Card I/O Map 1 Offset Address Low
38h
78h
62
Card I/O Map 1 Offset Address High
39h
79h
62
Setup Timing 0
3Ah
7Ah
84
85
62
Command Timing 0
3Bh
7Bh
Recovery Timing 0
3Ch
7Ch
Setup Timing 1
3Dh
7Dh
Command Timing 1
3Eh
7Eh
85
Recovery Timing 1
3Fh
7Fh
86
“Timing Registers” on
page 84
86
84
1. Socket B is available on the dual-socket PD6722.
2. This register affects both sockets (it is not specific to either socket).
3. These registers are not available on the PD6710.
6.2
Data
Register Name: Data
Register Per: chip
Index: n/a
Bit 7
Register Compatibility Type 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data
44
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
The Data register is accessed at 03E1h. This register indicates the contents of the register at the
Device/Socket/Register Index selected by the Index register.
Datasheet
45
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
7.0
Chip Control Registers
7.1
Chip Revision
Register Name: Chip Revision
Register Per: chip
Index: 00h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Interface ID
R:10
Bit 2
Bit 1
Bit 0
Revision
R:0
R:0
R:00101
1. Value for the current stepping only.
Bits 3:0 — Revision
This field indicates compatibility with the 82365SL A-step.
Bits 7:6 — Interface ID
00
I/O only.
01
Memory only.
10
Memory and I/O.
11
Reserved.
These bits identify what type of interface this controller supports.
46
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
7.2
Interface Status
Register Name: Interface Status
Register Per: socket
Index: 01h
Bit 7
Register Compatibility Type: 365
Bit 6
-VPP_VALID
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY
WP
-CD2
-CD1
BVD2
BVD1
VPP Valid
Card Power
On
Ready/Busy*
Write Protect
Card Detect
Battery Voltage Detect
R1
R:0
R2
R3
R4
R5
1.
2.
3.
4.
5.
Bit 7 is the inversion of the value of the -VPP_VALID pin (Table 1).
Bit 5 is the value of the RDY/-IREQ pin (Table 2).
Bit 4 is the value of the WP/-IOIS16 pin (Table 2).
Bits 3:2 are the inversion of the values of the -CD1 and -CD2 pins (Table 2).
Bits 1:0 are the values of the BVD1/-STSCHG and BVD2/-SPKR pins (Table 2).
Bits 1:0 — Battery Voltage Detect
BVD2 Input Level
BVD1 Input Level
Bit 1
Bit 0
PC Card Interpretation
Low
Low
0
0
Card data lost
Low
High
0
1
Battery low warning
High
Low
1
0
Card data lost
High
High
1
1
Battery/data okay
These bits are used by PC Card support software and firmware to indicate the amount of capacity
left in the battery in battery-backed cards in Memory Card Interface mode only. In I/O Card
Interface mode, bit 0 indicates the state of the BVD1/-STSCHG pin ( Table 2). Bit 1 status should
be ignored in I/O Card Interface mode.
Bits 3:2 — Card Detect
-CD2 Level
-CD1 Level
Bit 3
Bit 2
Card Detect Status
High
High
0
0
Either no card or card is not fully inserted
High
Low
0
1
Card is not fully inserted
Low
High
1
0
Card is not fully inserted
Low
Low
1
1
Card is fully inserted
These bits indicate the state of the -CD1 and -CD2 pins ( Table 2).
Datasheet
47
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 4 — Write Protect
0
Card is not write protected.
1
Card is write protected.
This bit indicates the state of the WP/-IOIS16 pin ( Table 2) on the card and has meaning only in
Memory Card Interface mode.
Bit 5 — Ready/Busy*
0
Card is not ready.
1
Card is ready.
This bit indicates the state of the RDY/-IREQ pin ( Table 2) on the card. If the card has been
configured for I/O, then this bit will not be valid.
Bit 6 — Card Power On
0
Power to the card is not on.
1
Power to the card is on.
This status bit indicates whether power to the card is on. Refer to Table 11 on page 42 for details.
Bit 7 — VPP Valid
0
This status bit indicates a logic high at the -VPP_VALID pin.
1
This status bit indicates a logic low at the -VPP_VALID pin.
This bit indicates the status of the -VPP_VALID pin ( Table 1).
7.3
Power Control
Register Name: Power Control
Register Per: socket
Index: 02h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Card Enable
Compatibility
Bit
Auto-Power
VCC Power
Compatibility Bits
VPP1 Power
RW:0
RW:0
RW:0
RW:0
RW:00
RW:00
48
Bit 3
Bit 2
Bit 1
Bit 0
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 12. Enabling of Socket Power Controls
PWRGOOD
Level
Power Control
Register
Interface Status
Register
(see page 47)
-CD1 and
-CD2 Both
Active Low
-VCC_3
and
-VCC_5
Levels
VPP1_PGM and
VPP1_VCC
Levels
Bit 4:
VCC Power
Bit 5:
Auto- Power
Low
X
X
X
0
Inactive high
Inactive low
High
0
X
X
0
Inactive high
Inactive low
High
1
0
X
1
Activated per
Misc Control 1
register, bit 1
Bit 6: Card Power
On
High
1
1
No
0
Inactive high
High
1
1
Yes
1
Activated per
Misc Control 1
register, bit 1
Activated per
Power Control
register,
bits 1 and 0
Inactive low
Activated per
Power Control
register,
bits 1 and 0
Table 13. Enabling of Outputs to Card Socket
Datasheet
PWRGOOD
Level
-CD1 and
-CD2 Both
Active Low
Low
Power Control Register
PD67XX Signal
Outputs to Socket
Bit 4:
VCC Power
Bit 7:
Card Enable
X
X
X
High impedance
High
No
X
X
High impedance
High
Yes
0
0
High impedance
High
Yes
0
1
Enabled
High
Yes
1
0
High impedance
High
Yes
1
1
Enabled
Bit Name
Value
Description
VCC Power
1
Enables VCC to level described by VCC 3.3V (see “Bit 4 — VCC Power” on
page 50)
Auto-Power
1
Enables Auto-power mode
Card Enable
1
Enables socket output drivers
49
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bits 1:0 — VPP1 Power
VPP1 Power
Bit 1
Bit 0
VPP_PGM
VPP_VCC
PC Card Intended Socket Function
0
0
Inactive low
Inactive low
Zero volts to PC Card socket VPP1 pin
0
1
Inactive low
Active high1
Selected card VCC to PC Card socket VPP1
pin
1
0
Active high a
Inactive low
+12V to PC Card socket VPP1 pin
1
1
Inactive low
Inactive low
Zero volts to PC Card socket VPP1 pin
1. Under conditions where VPP1 power is activated. See “Power Control” on page 48.
These bits are intended to be used to control the power to the VPP1 pin of the PC Card.
Bit 4 — VCC Power
0
Power is not applied to the card: the -VCC_3 and -VCC_5 socket power control pins are
inactive high.
1
Power is applied to the card: if bit 5 is ‘0’, or bit 5 is ‘1’ and -CD2 and -CD1 are active low,
then the selected -VCC_3 or -VCC_5 socket power control pin is active low.
Depending on the value of bit 5 below, setting this bit to ‘1’ will cause power to be applied to the
card. The VCC 3.3V bit (see bit 1, “Misc Control 1” on page 70) determines whether 3.3V or 5V
power is applied.
Bit 5 — Auto-Power
0
VCC and VPP1 power control signals are activated independent of the socket’s -CD2 and CD1 input levels.
1
VCC and VPP1 power control signals are only activated if the socket’s -CD2 and -CD1 inputs
are active low.
When this bit is set to ‘1’, the PD67XX causes power to the card to be turned on and off
automatically with the insertion and removal of a PC card from the socket.
Bit 7 — Card Enable
0
Outputs to card socket are not enabled and are floating.
1
Outputs to card socket are enabled if -CD1 and -CD2 are active low and bit 4 is ‘1’.
When this bit is ‘1’, the outputs to the PC Card are enabled if a card is present and card power is
being supplied. The pins affected include: -CE2, -CE1, -IORD, -IOWR, -OE, -REG, RESET,
A[25:0], D[15:0], and -WE (see Table 2).
50
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
7.4
Interrupt and General Control
Register Name: Interrupt and General Control
Register Per: socket
Index: 03h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Ring Indicate
Enable
Card Reset*
Card Is I/O
Enable
Manage Int
Card IRQ Select
RW:0
RW:0
RW:0
RW:0
RW:0000
Bit 0
Bits 3:0 — Card IRQ Select
0000
IRQ disabled
0001
Reserved
0010
Reserved
0011
IRQ 3
0100
IRQ 4
0101
IRQ 5
0110
Reserved
0111
IRQ 7
1000
Reserved
1001
IRQ 9 (On the PD6722, this output may alternately be used as an ISA bus DACK* signal)
1010
IRQ 10 (On the PD6722, this output may alternately be used as an ISA bus DRQ signal)
1011
IRQ 11
1100
IRQ 12 (This output may alternately be used for LED)
1101
Reserved
1110
IRQ 14
1111
IRQ 15 (This output may alternately be used for ring indicate)
These bits determine which IRQ will occur when the card causes an interrupt through the RDY/
-IREQ pin on the PC Card connector.
Bit 4 — Enable Manage Int
0
Card status management interrupts occur as programmed by Management IRQ Select bits (bits
7:4 of Management Interrupt Configuration register, see “Bits 7:4 — Management IRQ
Select” on page 55).
1
Card status management interrupts are redirected to the -INTR line instead of the programmed
IRQ pin.
This bit determines how management interrupts will occur.
Datasheet
51
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 5 — Card Is I/O
0
Memory Card Interface mode: card socket configured to support memory cards. Dual-function
socket interface pins perform memory card-type interface functions.
1
I/O Card Interface mode: card socket configured to support I/O/memory card-type interface
functions. Dual-function socket interface pins perform I/O/memory card-type interface functions.
This bit determines how dual-function socket interface pins will be used.
Bit 6 — Card Reset*
0
The RESET signal to the card socket is set active (high for normal, low for ATA mode).
1
The RESET signal to the card socket is set inactive (low for normal, high for ATA mode).
This bit determines whether the RESET signal (see Table 2 on page 20) to the card is active or
inactive. When the Card Enable bit (see “Bit 7 — Card Enable” on page 50) is ‘0’, the RESET
signal to the card will be high-impedance. See Chapter 10 for further description of ATA mode
functions.
Bit 7 — Ring Indicate Enable
0
BVD1/-STSCHG pin is status change function.
1
BVD1/-STSCHG pin is ring indicate input pin from card.
This bit determines whether the -STSCHG input pin is used to activate the IRQ15 pin in
conjunction with Misc Control 2, IRQ15 Is RI Out (see “Bit 7 — IRQ15 Is RI Out” on page 74).
This bit has no significance when the card socket is configured for memory card operation.
7.5
Card Status Change
Register Name: Card Status Change
Register Per: socket
Index: 04h
Bit 7
R:0
Register Compatibility Type: 365
Bit 6
R:0
Bit 5
R:0
Bit 4
R:0
Bit 3
Bit 2
Bit 1
Bit 0
Card Detect
Change
Ready
Change
Battery
Warning
Change
Battery Dead
Or Status
Change
R:0
R:0
R:0
R:0
• This register indicates the source of a management interrupt generated by the PD67XX.
Note:
52
The corresponding bit in the Management Interrupt Configuration register must be set to ‘1’ to
enable each specific status change detection.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 0 — Battery Dead Or Status Change
0
A transition (from high to low for memory card support or either high to low or low to high for I/O
card support) on the BVD1/-STSCHG pin has not occurred since this register was last read.
1
A transition on the BVD1/-STSCHG pin has occurred.
When the socket is configured for memory card support, this bit is set to ‘1’ when a BVD1 battery
dead high-to-low transition has been detected. When the socket is configured for I/O card support,
this bit is set to ‘1’ when the BVD1/-STSCHG pin (see Table 2 on page 20) changes from either
high to low or low to high. This bit is reset to ‘0’ whenever this register is read. In I/O Card
Interface mode, function of this bit is not affected by bit 7 of the Interrupt and General Control
register.
Bit 1 — Battery Warning Change
0
A transition (from high to low) on the BVD2 pin has not occurred since this register was last
read.
1
A transition on the BVD2 pin has occurred.
When a socket is configured for memory card support, this bit is set to ‘1’ when a high-to-low
transition on BVD2 occurs indicating a battery warning was detected. This bit should be ignored
when the socket is configured for I/O card support. This bit is reset to ‘0’ whenever this register is
read.
Bit 2 — Ready Change
0
A transition on the RDY/-IREQ pin has not occurred since this register was last read.
1
A transition on the RDY/-IREQ pin has occurred.
When this bit is ‘1’, a change has occurred in the card RDY/-IREQ pin (see Table 2 on page 20).
This bit will always read 0 when the card is configured as an I/O card. This bit is reset to ‘0’
whenever this register is read.
Bit 3 — Card Detect Change
0
A transition on the -CD1 or -CD2 pins has not occurred since this register was last read.
1
A transition on the -CD1 or -CD2 pins has occurred.
When this bit is ‘1’, a change has occurred on the -CD1 or -CD2 pins (see Table 2 on page 20).
This bit is reset to ‘0’ whenever this register is read.
Datasheet
53
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
7.6
Management Interrupt Configuration
Register Name; Management Interrupt Configuration
Register Per: socket
Index: 05h
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Management IRQ Select
Card Detect
Enable
Ready
Enable
Battery
Warning
Enable
Battery Dead
Or Status
Change
Enable
RW:0000
RW:0
RW:0
RW:0
RW:0
This register controls which status changes may cause management interrupts and at which pin the
management interrupts will appear.
Bit 0 — Battery Dead Or Status Change Enable
0
Battery Dead Or Status Change management interrupt disabled.
1
If Battery Dead Or Status Change is ‘1’, a management interrupt will occur.
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s
Battery Dead Or Status Change bit (see “Bit 0 — Battery Dead Or Status Change” on page 53) is
‘1’. This allows management interrupts to be generated on changes in level of the BVD1/
-STSCHG pin.
Bit 1 — Battery Warning Enable
0
Battery Warning Change management interrupt disabled.
1
If Battery Warning Change is ‘1’, a management interrupt will occur.
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s
Battery Warning Change bit (see “Bit 1 — Battery Warning Change” on page 53) is ‘1’. This bit is
ignored when the card socket is in I/O mode.
Bit 2 — Ready Enable
0
Ready Change management interrupt disabled.
1
If Ready Change is ‘1’, a management interrupt will occur.
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s
Ready Change bit (see “Bit 1 — Battery Warning Change” on page 53) is ‘1’.
54
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 3 — Card Detect Enable
0
Card Detect Change management interrupt disabled.
1
If Card Detect Change is ‘1’, a management interrupt will occur.
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s
Card Detect Change bit (see “Bit 3 — Card Detect Change” on page 53) is ‘1’.
Bits 7:4 — Management IRQ Select
0000
IRQ disabled
0001
Reserved
0010
Reserved
0011
IRQ 3
0100
IRQ 4
0101
IRQ 5
0110
Reserved
0111
IRQ 7
1000
Reserved
1001
IRQ 9 (On the PD6722, this output may alternately be used as an ISA bus DACK* signal)
1010
IRQ 10 (On the PD6722, this output may alternately be used as an ISA bus DRQ signal)
1011
IRQ 11
1100
IRQ 12 (This output may alternately be used for LED)
1101
Reserved
1110
IRQ 14
1111
IRQ 15 (This output may alternately be used for ring indicate)
These bits determine which interrupt pin will be used for card status change management
interrupts.
7.7
Mapping Enable
Register Name: Mapping Enable
Register Per: socket
Index: 06h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Map 1
Enable
I/O Map 0
Enable
MEMCS16
Full Decode
Memory Map
4 Enable
Memory Map
3 Enable
Memory Map
2 Enable
Memory Map
1 Enable
Memory Map
0 Enable
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Datasheet
55
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 0 — Memory Map 0 Enable
0
Memory Mapping registers for Memory Space 0 disabled.
1
Memory Mapping registers for Memory Space 0 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 0 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 1 — Memory Map 1 Enable
0
Memory Mapping registers for Memory Space 1 disabled.
1
Memory Mapping registers for Memory Space 1 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 1 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 2 — Memory Map 2 Enable
0
Memory Mapping registers for Memory Space 2 disabled.
1
Memory Mapping registers for Memory Space 2 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 2 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 3 — Memory Map 3 Enable
0
Memory Mapping registers for Memory Space 3 disabled.
1
Memory Mapping registers for Memory Space 3 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 3 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 4 — Memory Map 4 Enable
0
Memory Mapping registers for Memory Space 4 disabled.
1
Memory Mapping registers for Memory Space 4 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 4 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 5 — MEMCS16 Full Decode
This bit is not used. All addresses are used to determine the level of MEMCS16*.
56
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 6 — I/O Map 0 Enable
0
I/O Mapping registers for I/O Space 0 disabled.
1
I/O Mapping registers for I/O Space 0 enabled.
When this bit is ‘1’, the I/O Mapping registers for I/O Space 0 will be enabled and the controller
will respond to I/O accesses in the I/O space defined by those registers.
Bit 7 — I/O Map 1 Enable
0
I/O Mapping registers for I/O Space 1 disabled.
1
I/O Mapping registers for I/O Space 1 enabled.
When this bit is ‘1’, the I/O Mapping registers for I/O Space 1 will be enabled and the controller
will respond to I/O accesses in the I/O space defined by those registers.
Datasheet
57
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.0
I/O Window Mapping Registers
The I/O windows must never include 3E0h and 3E1h.
8.1
I/O Window Control
Register Name: I/O Window Control
Register Per: socket
Index: 07h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timing
Register
Select 1
Compatibility
Bit
Auto-Size I/O
Window 1
I/O Window 1
Size
Timing
Register
Select 0
Compatibility
Bit
Auto-Size I/O
Window 0
I/O Window 0
Size
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Bit 0 — I/O Window 0 Size
0
8-bit data path to I/O Window 0.
1
16-bit data path to I/O Window 0.
When bit 1 below is ‘0’, this bit determines the size of the data path to I/O Window 0. When bit 1 is
‘1’, this bit is ignored.
Bit 1 — Auto-Size I/O Window 0
0
I/O Window 0 Size (see bit 0 above) determines the data path to I/O Window 0.
1
The data path to I/O Window 0 will be determined based on -IOIS16 returned by the card.
This bit determines the data path to I/O Window 0. Note that when this bit is ‘1’, the -IOIS16 signal
(see Table 2 on page 20) determines the width of the data path to the card.
Bit 3 — Timing Register Select 0
0
Accesses made with timing specified in Timing Set 0.
1
Accesses made with timing specified in Timing Set 1.
This bit determines the access timing specification for I/O Window 0 (see “Setup Timing 0–1” on
page 84).
58
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 4 — I/O Window 1 Size
0
8-bit data path to I/O Window 1.
1
16-bit data path to I/O Window 1.
When bit 5 below is ‘0’, this bit determines the size of the data path to I/O Window 1. When bit 5 is
‘1’, this bit is ignored.
Bit 5 — Auto-Size I/O Window 1
0
I/O Window 1 Size (see bit 4) determines the data path to I/O Window 1.
1
The data path to I/O Window 1 will be determined based on -IOIS16 returned by the card.
This bit determines the width of the data path to I/O Window 1. Note that when this bit is ‘1’, the
-IOIS16 signal (see Table 2 on page 20) determines the window size. This bit must be set for
proper ATA mode operation (see “ATA Mode Operation” on page 88).
Bit 7 — Timing Register Select 1
0
Accesses made with timing specified in Timing Set 0.
1
Accesses made with timing specified in Timing Set 1.
This bit determines the access timing specification for I/O Window 1 (see “Setup Timing 0–1” on
page 84).
8.2
System I/O Map 0–1 Start Address Low
Register Name: System I/O Map 0–1 Start Address Low
Register Per: socket
Index: 08h, 0Ch
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 7:0
RW:00000000
There are two separate System I/O Map Start Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index
8h
Ch
Datasheet
System I/O Map Start Address Low
System I/O Map 0 Start Address Low
System I/O Map 1 Start Address Low
59
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bits 7:0 — Start Address 7:0
This register contains the least-significant byte of the address that specifies the beginning of the I/O
space within the corresponding I/O map. I/O accesses that are equal or above this address and equal
or below the corresponding System I/O Map End Address will be mapped into the I/O space of the
corresponding PC Card.
The most-significant byte is located in the System I/O Map 0–1 Start Address High register (see
“System I/O Map 0–1 Start Address High” on page 60).
8.3
System I/O Map 0–1 Start Address High
Register Name: System I/O Map 0–1 Start Address High
Register Per: socket
Index: 09h, 0Dh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 15:8
RW:00000000
There are two separate System I/O Map Start Address High registers, each with
identical fields. These registers are located at the following indexes:
Index
9h
Dh
System I/O Map Start Address High
System I/O Map 0 Start Address High
System I/O Map 1 Start Address High
Bits 15:8 — Start Address 15:8
This register contains the most-significant byte of the Start Address. See the description of the Start
Address field associated with bits 7:0 of the System I/O Map 0–1 Start Address Low register.
8.4
System I/O Map 0–1 End Address Low
Register Name: System I/O Map 0–1 End Address Low
Register Per: socket
Index: 0Ah, 0Eh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Address 7:0
RW:00000000
There are two separate System I/O Map End Address Low registers, each with identical fields.
These registers are located at the following indexes:
60
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Index
Ah
Eh
System I/O Map End Address Low
System I/O Map 0 End Address Low
System I/O Map 1 End Address Low
Bits 7:0 — End Address 7:0
This register contains the least-significant byte of the address that specifies the termination of the I/
O space within the corresponding I/O map. I/O accesses that are equal or below this address and
equal or above the corresponding System I/O Map Start Address will be mapped into the I/O space
of the corresponding PC Card.
The most-significant byte is located in the System I/O Map 0–1 End Address High register (see
“System I/O Map 0–1 End Address High” on page 61).
8.5
System I/O Map 0–1 End Address High
Register Name: System I/O Map 0–1 End Address High
Register Per: socket
Index: 0Bh, 0Fh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Address 15:8
RW:00000000
There are two separate System I/O Map End Address High registers, each with
identical fields. These registers are located at the following indexes:
Index
Bh
Fh
System I/O Map End Address High
System I/O Map 0 End Address High
System I/O Map 1 End Address High
Bits 15:8 — End Address 15:8
This register contains the most-significant byte of the End Address. See the description of the End
Address field associated with bits 7:0 of the System I/O Map 0–1 End Address Low register (see
“System I/O Map 0–1 End Address Low” on page 60).
Datasheet
61
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.6
Card I/O Map 0–1 Offset Address Low
Register Name: Card I/O Map 0–1 Offset Address Low
Register Per: socket
Index: 36h, 38h
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 7:1
01
RW:0000000
RW:0
1. This bit must be programmed to ‘0’.
There are two separate Card I/O Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index
36h
38h
Card I/O Map Offset Address Low
Card I/O Map 0 Offset Address Low
Card I/O Map 1 Offset Address Low
Bits 7:1 — Offset Address 7:1
This register contains the least-significant byte of the quantity that will be added to the host I/O
address; this will determine the PC Card I/O map location where the I/O access will occur.
The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register (see
“Card I/O Map 0–1 Offset Address High” on page 62).
8.7
Card I/O Map 0–1 Offset Address High
Register Name: Card I/O Map 0–1 Offset Address High
Register Per: socket
Index: 37h, 39h
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 15:8
RW:00000000
There are two separate Card I/O Map Offset Address High registers, each with identical fields.
These registers are located at the following indexes:
Index
37h
39h
62
Card I/O Map Offset Address High
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address High
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bits 15:8 — Offset Address 15:8
This register contains the most-significant byte of the Offset Address. See the description of the
End Address field associated with bits 7:1 of the Card I/O Map 0–1 Offset Address Low register
(see “Card I/O Map 0–1 Offset Address Low” on page 62).
Datasheet
63
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
9.0
Memory Window Mapping Registers
The following information about the memory map windows is important:
• The memory window mapping registers determine where in the ISA memory space and PC
Card memory space accesses will occur. There are five memory windows that can be used
independently.
• The memory windows are enabled and disabled using the Mapping Enable register (see
“Mapping Enable” on page 55).
• To specify where in the ISA space a memory window is mapped, start and end addresses are
specified. A memory window is selected whenever the appropriate Memory Map Enable bit
(see “Mapping Enable”) is set, and when the ISA address is greater than or equal to the
appropriate System Memory Map Start Address register (see “System Memory Map 0–4
Start Address Low” on page 64) and the ISA address is less than or equal to the appropriate
System Memory Map End Address register (see “System Memory Map 0–4 End Address
Low” on page 66).
• Start and end addresses are specified with ISA Address bits 23:12. This sets the minimum size
of a memory window to 4K bytes. Memory windows are specified in the ISA address from 64
Kbytes to 16 Mbytes (0010000h–FFFFFFh). Note that no memory window can be mapped in
the first 64 Kbytes of the ISA address space.
• To ensure proper operation, none of the windows can overlap in the ISA address space.
9.1
System Memory Map 0–4 Start Address Low
Register Name: System Memory Map 0–4 Start Address Low
Register Per: socket
Index: 10h, 18h, 20h, 28h, 30h
Bit 7
Bit 6
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 19:12
RW:00000000
There are five separate System Memory Map Start Address Low registers, each with identical
fields. These registers are located at the following indexes:
Index
10h
18h
20h
28h
30h
64
System Memory Map Start Address Low
System Memory Map 0 Start Address Low
System Memory Map 1 Start Address Low
System Memory Map 2 Start Address Low
System Memory Map 3 Start Address Low
System Memory Map 4 Start Address Low
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bits 7:0 — Start Address 19:12
This register contains the least-significant byte of the address that specifies where in the memory
space the corresponding memory map will begin. Memory accesses that are equal or above this
address and equal or below the corresponding System Memory Map End Address will be mapped
into the memory space of the corresponding PC Card.
The most-significant four bits are located in the System Memory Map 0–4 Start Address High
register (see “System Memory Map 0–4 Start Address High” on page 65).
9.2
System Memory Map 0–4 Start Address High
Register Name: System Memory Map 0–4 Start Address High
Register Per: socket
Index: 11h, 19h, 21h, 29h, 31h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Window Data
Size
Compatibility
Bit
Scratchpad Bits
Start Address 23:20
RW:0
RW:0
RW:00
RW:0000
Bit 0
There are five separate System Memory Map Start Address High registers, each with identical
fields. These registers are located at the following indexes:
Index
11h
19h
21h
29h
31h
System Memory Map Start Address High
System Memory Map 0 Start Address High
System Memory Map 1 Start Address High
System Memory Map 2 Start Address High
System Memory Map 3 Start Address High
System Memory Map 4 Start Address High
Bits 3:0 — Start Address 23:20
This field contains the most-significant four bits of the Start Address. See the description of the
Start Address field associated with bits 7:0 of the System Memory Map 0–4 Start Address Low
register (see “System Memory Map 0–4 Start Address Low” on page 64).
Bit 7 — Window Data Size
0
8-bit data path to the card.
1
16-bit data path to the card.
This bit determines the data path size to the card.
Datasheet
65
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
9.3
System Memory Map 0–4 End Address Low
Register Name: System Memory Map 0–4 End Address Low
Register Per: socket
Index: 12h, 1Ah, 22h, 2Ah, 32h
Bit 7
Bit 6
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Address 19:12
RW:00000000
There are five separate System Memory Map End Address Low registers, each with identical
fields. These registers are located at the following indexes:
Index
12h
1Ah
22h
2Ah
32h
System Memory Map End Address Low
System Memory Map 0 End Address Low
System Memory Map 1 End Address Low
System Memory Map 2 End Address Low
System Memory Map 3 End Address Low
System Memory Map 4 End Address Low
Bits 7:0 — End Address 19:12
This register contains the least-significant byte of the address that specifies where in the memory
space the corresponding memory map will end. Memory accesses that are equal or below this
address and equal or above the corresponding System Memory Map Start Address will be mapped
into the memory space of the corresponding PC Card.
The most-significant four bits are located in the System Memory Map 0–4 End Address High
register (see “System Memory Map 0–4 End Address High” on page 66).
9.4
System Memory Map 0–4 End Address High
Register Name: System Memory Map 0–4 End Address High
Register Per: socket
Index: 13h, 1Bh, 23h, 2Bh, 33h
Bit 7
Bit 6
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Card Timer Select
Scratchpad Bits
End Address 23:20
RW:00
RW:00
RW:0000
Bit 0
There are five separate System Memory Map End Address High registers, each with identical
fields. These registers are located at the following indexes:
Index
13h
1Bh
66
System Memory Map End Address High
System Memory Map 0 End Address High
System Memory Map 1 End Address High
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
23h
2Bh
33h
9.4.0.1
System Memory Map 2 End Address High
System Memory Map 3 End Address High
System Memory Map 4 End Address High
Bits 3:0 — End Address 23:20
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7:0 of the System Memory Map 0–4 End Address Low register
(see “System Memory Map 0–4 End Address Low” on page 66).
Bits 7:6 — Card Timer Select
00
Selects Timer Set 0.
01
Selects Timer Set 1.
10
Selects Timer Set 1.
11
Selects Timer Set 1.
This field selects the Timeset registers used to control socket timing for card accesses in this
window address range. Timeset 0 and 1 reset to values compatible with PC Card standards. The
mapping of bits 7:6 to Timeset 0 and 1, as shown in the preceding table, is done for software
compatibility with older ISA bus-based PC Card controllers that use ISA bus wait states instead of
Timeset registers (see “Setup Timing 0–1” on page 84).
9.5
Card Memory Map 0–4 Offset Address Low
Register Name: Card Memory Map 0–4 Offset Address Low
Register Per: socket
Index: 14h, 1Ch, 24h, 2Ch, 34h
Bit 7
Bit 6
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 19:12
RW:00000000
There are five separate Card Memory Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index
14h
1Ch
24h
2Ch
34h
Datasheet
Card Memory Map Offset Address Low
Card Memory Map 0 Offset Address Low
Card Memory Map 1 Offset Address Low
Card Memory Map 2 Offset Address Low
Card Memory Map 3 Offset Address Low
Card Memory Map 4 Offset Address Low
67
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bits 7:0 — Offset Address 19:12
This register contains the least-significant byte of the quantity that will be added to the host
memory address, which will determine where the memory access will occur in the PC Card
memory map.
The most-significant six bits are located in the Card Memory Map 0–4 Offset Address High
register (see “Card Memory Map 0–4 Offset Address High” on page 68).
9.6
Card Memory Map 0–4 Offset Address High
Register Name: Card Memory Map 0–4 Offset Address High
Register Per: socket
Index: 15h, 1Dh, 25h, 2Dh, 35h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Write Protect
REG Setting
Offset Address 25:20
RW:0
RW:0
RW:000000
Bit 1
Bit 0
There are five separate Card Memory Map Offset Address High registers, each with identical
fields. These registers are located at the following indexes:
Index
15h
1Dh
25h
2Dh
35h
Card Memory Map Offset Address High
Card Memory Map 0 Offset Address High
Card Memory Map 1 Offset Address High
Card Memory Map 2 Offset Address High
Card Memory Map 3 Offset Address High
Card Memory Map 4 Offset Address High
Bits 5:0 — Offset Address 25:20
This field contains the most-significant six bits of the Offset Address. See the description of the
Offset Address field associated with bits 7:0 of the Card Memory Map 0–4 Offset Address Low
register (see “Card Memory Map 0–4 Offset Address Low” on page 67).
Bit 6 — REG Setting
0
-REG (see Table 2 on page 20) is not active for accesses made through this window.
1
-REG is active for accesses made through this window.
This bit determines whether -REG ( Table 2) will be active for accesses made through this window.
Card Information Structure (CIS) memory is accessed by setting this bit to ‘1’.
68
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 7 — Write Protect
0
Writes to the card through this window are allowed.
1
Writes to the card through this window are inhibited.
This bit determines whether writes to the card through this window are allowed. This bit only
applies to Memory Card Interface mode.
Note:
Datasheet
This bit must be set to ‘0’ and a memory card’s ‘WP’ switch must be turned off to allow writes to a
card using a memory interface, such as an SRAM card.
69
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
10.0
Extension Registers
10.1
Misc Control 1
Register Name: Misc Control 1
Register Per: socket
Index: 16h
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Inpack
Enable
Scratchpad Bits
RW:0
RW:00
Bit 4
Bit 3
Bit 2
Bit 1
Speaker
Enable
Pulse System
IRQ
Pulse
Management
Interrupt
VCC 3.3V
RW:0
RW:0
RW:0
RW:0
Bit 0
5 V Detect
(PD6710)
Reserved1
(PD6722)
R:X W:0
1. On some versions of the PD6722, this bit can be used to read levels of the A_GPSTB and B_GPSTB pins.
Bit 0 — 5 V Detect (PD6710 only)
0
3.3 V card detected.
1
Old or 5 V card detected.
This bit is connected to pins VS1 and VS2. Cards that will only operate at 3.3 V will drive this bit
to ‘0’.
Bit 1 — VCC 3.3V
0
-VCC_5 activated when card power is to be applied.
1
-VCC_3 activated when card power is to be applied.
This bit determines which output pin is to be used to enable VCC power to the socket when card
power is to be applied; it is used in conjunction with bits 5:4 of the Power Control register (see
“Power Control” on page 48).
Bit 2 — Pulse Management Interrupt
0
Card status change management interrupts are passed to the appropriate IRQ[XX] or -INTR pin
as level-sensitive.
1
When a card status change management interrupt occurs, the appropriate IRQ[XX] or -INTR
pin is driven with the pulse train shown in Figure 11 and allows for interrupt sharing.
This bit selects Level or Pulse mode operation of the IRQ[XX] or -INTR pin being used for card
status change management interrupts (see Table 1). Note that a clock must be present on the
incoming CLK for pulsed interrupts to work.
70
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Figure 11. Pulse Mode Interrupts
Driven high
High-Z
-INTR or
IRQ[XX]
High-Z
Driven low
Bit 3 — Pulse System IRQ
0
RDY/-IREQ generated interrupts are passed to the IRQ[XX] pin as level-sensitive.
1
When a RDY/-IREQ interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in
Figure 11 and allows for interrupt sharing.
This bit selects Level or Pulse mode operation of the IRQ[XX] pins for interrupts from a PC Card
RDY/-IREQ pin ( Table 2).
Bit 4 — Speaker Enable
0
SPKR_OUT* is high-impedance.
1
SPKR_OUT* is driven from the XOR of -SPKR from each enabled socket.
This bit determines whether the card -SPKR pin will drive SPKR_OUT* ( Table 1).
Bit 7 — Inpack Enable
0
-INPACK pin (Table 2) ignored.
1
-INPACK pin used to control data bus drivers during I/O read from the socket.
This bit is used to determine when to drive data onto the ISA bus.
Datasheet
71
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
10.2
FIFO Control
Register Name: FIFO Control
Register Per: socket
Index: 17h
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Empty Write
FIFO
Scratchpad Bitsa
RW
RW:0000000
Bit 2
Bit 1
Bit 0
1. Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
a.
Bit 7 — Empty Write FIFO
Value
I/O Read
I/O Write
0
FIFO not empty
No operation occurs; default on reset
1
FIFO empty
Flush the FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is written to ‘1’, all data in
the FIFO is lost. During read operations when this bit is ‘1’, the FIFO is empty. During read
operations when this bit is ‘0’, data is still in the FIFO. This bit is used to ensure the FIFO is empty
before changing timing registers.
FIFO contents will be lost whenever any of the following occur:
• PWRGOOD pin ( Table 1) is ‘0’.
• The card is removed.
• VCC Power bit (see “Bit 4 — VCC Power” on page 50) is programmed to ‘0’.
10.3
Misc Control 2
Register Name: Misc Control 2
Register Per: chip
Index: 1Eh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ15 Is RI
Out
DMA System
(PD6722)
Three-State
Bit 7
Drive LED
Enable
5V Core
Suspend
Low-Power
Dynamic
Mode
Bypass
Frequency
Synthesizer
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:1
RW:0
72
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 0 — Bypass Frequency Synthesizer
0
Normal operation, internal clock = CLK input frequency x 7/4.
1
Internal clock = CLK input frequency (see Table 1).
This bit determines internal time base.
Bit 1 — Low-Power Dynamic Mode
0
Clock runs always.
1
Normal operation, stop clock when possible.
This bit determines whether Low-Power Dynamic mode is enabled. For maximum operational
power savings, keep this bit set to ‘1’.
Bit 2 — Suspend
0
Normal operation.
1
Stop Frequency Synthesizer, enable all Low-Power modes and disable socket access.
This bit enables Suspend mode. After entering Suspend, AEN should be pulled high for lowest
power consumption. When this bit is high and AEN is high, all ISA bus interface inputs are turned
off. In 82386SL systems when the processor is in Suspend mode, the ISA bus interface signals
float; this feature will prevent high current flow in the PD67XX inputs.
Bit 3 — 5V Core
0
Normal operation: use when CORE_VDD pin is connected to 3.3 volts.
1
Selects input thresholds for use when 5.0 volts is connected to the PD67XX CORE_VDD pins.
This bit selects input threshold circuits for use when 3.3 or 5.0 volts is connected to the PD67XX
CORE_VDD pins. This bit must be set to ‘0’ when the CORE_VDD pins are connected to 3.3 volts
to preserve TTL-compatible input thresholds to the card socket.
Bit 4 — Drive LED Enable
Note:
Datasheet
0
IRQ12 operates normally.
1
IRQ12 becomes an open-drain output suitable for driving an LED (driven whenever the card SPKR output is turned on, and the corresponding Speaker Is LED input bit (see “Bit 1 —
Speaker Is LED Input” on page 76) is set).
This bit should be set to ‘0’ if in Memory Card Interface mode. This bit determines whether -SPKR
is used to drive an LED on the IRQ12 ( Table 1) for disk drives.
73
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 5 — Three-State Bit 7
0
Normal operation.
1
For socket I/O at address 03F7h and 0377h, do not drive bit 7.
This bit enables floppy change bit compatibility.
Bit 6 — DMA System (PD6722 only)
0
Configured for non-DMA mode on the PD6722.
1
Configured for DMA mode on the PD6722.
On the PD6710, this bit is reserved.
On the PD6722, this bit is used to configure system interface signals for normal or DMA operation.
At reset, the signals IRQ9, IRQ10, and -VPP_VALID are in non-DMA mode, and this bit is set to
‘0’. When this bit is set to ‘1’, the IRQ9, IRQ10, and -VPP_VALID pins are reconfigured for
system bus DMA interfacing. Refer to “DMA Operation (PD6722 only)” on page 97 for a
functional description of these pins during DMA operation.
Bit 7 — IRQ15 Is RI Out
0
Normal IRQ15 operation.
1
IRQ15 is connected to Ring Indicate pin on the host processor.
This bit determines the function of the IRQ15 pin. When configured for ring indicate, IRQ15 is
used to resume a processor with NMI or SMI such as an 82486SL when a high-to-low change is
detected on the -STSCHG pin.
10.4
Chip Information
Register Name: Chip Information
Register Per: chip
Index: 1Fh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC Card Controller Identification
Dual/Single
Socket*
PD67XX Revision Level
Reserved
R:11
R:n1
R:nnnn2
R:n3
1. The value for PD6710 is ‘0’, and the value for PD6722 is ‘1’.
2. This read-only value depends on the revision level of the PD67XX chip.
3. The value for PD6722 is ‘1’. The value for the PD6710 is ‘0’.
74
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bits 4:1 — PD67XX Revision Level
This field identifies the revision of the controller. The initial value is ‘111’.
Bit 5 — Dual/Single Socket*
0
Chip identified as a single-socket controller.
1
Chip identified as a dual-socket controller.
This bit specifies the number of sockets supported by the PD67XX.
Bits 7:6 — PC Card Controller Identification
00
Second read after I/O write to this register.
11
First read after I/O write to this register.
This field identifies a PC Card controller device. After chip reset or doing an I/O write to this
register, the first read of this register will return ‘11’. On the next read, this field will be ‘00’. This
pattern of toggling data on subsequent reads can be used by software to determine presence of a PC
Card controller in a system or to determine occurrence of a device reset.
10.5
ATA Control
Register Name: ATA Control
Register Per: socket
Index: 26h
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A25/CSEL
A24/M/S*
A23/VU
A22
A21
Scratchpad
Bit
Speaker Is
LED Input
ATA Mode
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Bit 0 — ATA Mode
0
Normal operation.
1
Configures the socket interface to handle ATA-type disk drives.
This bit reconfigures the particular socket as an ATA drive interface. Refer to Table 17 on page 88
for PC Card socket pin definitions in ATA mode.
Datasheet
75
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 1 — Speaker Is LED Input
0
Normal operation.
1
The PC Card -SPKR pin will be used to drive IRQ12 if Drive LED Enable (see “Bit 4 — Drive
LED Enable” on page 73) is set.
This bit changes the function of the BVD2/-SPKR/-LED pin (see Table 2 on page 20) from digital
speaker input to disk status LED input. When in I/O Card Interface mode or ATA mode, setting this
bit to ‘1’ reconfigures the BVD2/-SPKR/-LED input pin to serve as a -LED input from the socket.
Note:
This bit should be set to ‘0’ if in Memory Card Interface mode.
Bit 3 — A21
In ATA mode, the value in this bit is applied to the ATA A21 pin and is vendor-specific. Certain
ATA drive vendor-specific performance enhancements beyond the PC Card Standard may be
controlled through use of this bit. This bit has no hardware control function when not in ATA mode.
Bit 4 — A22
In ATA mode, the value in this bit is applied to the ATA A22 pin and is vendor-specific. Certain
ATA drive vendor-specific performance enhancements beyond the PC Card Standard may be
controlled through use of this bit. This bit has no hardware control function when not in ATA mode.
Bit 5 — A23/VU
In ATA mode, the value in this bit is applied to the ATA A23 pin and is vendor-specific. Certain
ATA drive vendor-specific performance enhancements beyond the PC Card Standard may be
controlled through use of this bit. This bit has no hardware control function when not in ATA mode.
Bit 6 — A24/M/S*
In ATA mode, the value in this bit is applied to the ATA A24 pin and is vendor-specific. Certain
ATA drive vendor-specific performance enhancements beyond the PC Card Standard may be
controlled through use of this bit. This bit has no hardware control function when not in ATA mode.
Bit 7 — A25/CSEL
In ATA mode, the value in this bit is applied to the ATA A25 pin and is vendor-specific. Certain
ATA drive vendor-specific performance enhancements beyond the PC Card Standard may be
controlled through use of this bit. This bit has no hardware control function when not in ATA mode.
76
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
10.6
Extended Index
Register Name: Extended Index
Register Per: socket
Index: 2Eh
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Extended Index
RW:00000000
In the PD6722 only, this register controls which of the following registers at index 2Fh can be
accessed:
10.7
Register Name at Index 2Fh
Extended
Register Index
Scratchpad
00h
Data Mask 0
01h
Data Mask 1
02h
Extension Control 1
(formerly named DMA Control)
03h
Maximum DMA Acknowledge Delay
04h
Reserved
05h–09h
External Data
0Ah
Extension Control 2
0Bh
Extended Data
Register Name: Extended Data
Register Per: socket
Index: 2Fh
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Extended Data
The data in this register allows the registers indicated by the Extended Index register to be read
and written. The value of this register is the value of the register selected by the Extended Index
register.
Datasheet
77
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
10.7.1
Data Mask 0–1
Register Name: Data Mask 0–1
Register Per: socket
Extended Index: 01h, 02h
Index: 2Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Compatibility Type: ext.
Bit 2
Bit 1
Bit 0
Data Mask Select 0–1
RW:00000000
Data Mask 0 is the mask register for I/O Map 0. For each bit set in the Data Mask Select 0 field,
the corresponding data bit will not be driven when the host addresses PC Card I/O addresses in the
I/O Map 0 range. If this register is set to 00h, then all data bits will be driven from the PC Card to
the ISA bus (this is the reset condition). If any bits are set to ‘1’, accesses to the I/O Map 0 range of
I/O on the PC Card will be forced to 8-bit operation on the ISA side. If, for example, I/O Map 0
registers are set for the range 3F7h to 3F7h, I/O Map 1 registers are set for the range 3F0h to 3F6h,
Data Mask Select 0 is set to 7Fh, and a floppy drive is the PC Card device, then the conflict
between the floppy address 3F7h and the hard disk register at 3F7h would not cause a conflict on
the ISA bus — the floppy change bit would be correctly presented to the host.
The Data Mask 1 register operates the same as the Data Mask 0 register but acts on I/O addresses
in the range indicated by the I/O Map 1 registers.
10.7.2
Extension Control 1 (PD6722 only, formerly DMA Control)
Register Name: Extension Control 1
Register Per: socket
Extended Index: 03h
Index: 2Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Compatibility Type: ext.
Bit 2
Bit 1
Bit 0
DMA Enable
(PD6722)
Pull-up
Control
Reserved
LED Activity
Enable
Auto Power
Clear Disable
VCC Power
Lock
RW:00
RW:0
RW:00
RW:0
RW:0
RW:0
Bit 0 — VCC Power Lock
0
The VCC Power bit (bit 4 of Power Control register) is not locked.
1
The VCC Power bit (bit 4 of Power Control register) cannot be changed by software.
This bit can be used to prevent card drivers from overriding the Socket Services’ task of controlling
power to the card, thus preventing situations where cards are powered incorrectly.
Bit 1 — Auto Power Clear Disable
78
0
The VCC Power bit (bit 4 of Power Control register) is reset to ‘0’ when the card is removed.
1
The VCC Power bit (bit 4 of Power Control register) is not affected by card removal.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bit 2 — LED Activity Enable
0
LED activity disabled.
1
LED activity enabled.
This bit allows the LED_OUT* pin to reflect any activity in the card. Whenever PC Card cycles are
in process to or from a card in either socket, LED_OUT* will be active (low).
Bit 5 — Pull-up Control
0
Pull-ups on CD2, CD1, A_GPSTB, and B_GPSTB (PD6722) are in use.
1
Pull-ups on CD2, CD1, A_GPSTB, and B_GPSTB (PD6722) are turned off.
This bit turns off the pull-ups on CD2, CD1, and A_GPSTB and B_GPSTB (PD6722). Turning off
these pull-ups can be used in addition to Suspend mode to even further reduce power when cards
are inserted but no card accessibility is required. Even though power may or may not still be
applied, all pull-ups and their associated inputs will be disabled.
Bit 7:6 — DMA Enable (PD6722 only)
On the PD6722, DMA Enable bits 6 and 7 enable the DMA operation of the PC Card socket. At
reset these bits are set to ‘0’, and this is non-DMA mode. If either or both of these bits is set, the
socket is in DMA mode. The three codes that cause DMA mode also select the use of one of three
pins for the active-low -DREQ input at the PC Card interface.
Bit 7
Bit 6
Pin Used
0
1
-INPACK
1
0
WP/-IOIS16
1
1
BVD2/-SPKR
For cards requiring DMA services but also needing input acknowledge functionality, or needing to
indicate the size of I/O registers within a window, or needing digital speaker or LED operation, the
selection of the -DREQ signal to the socket is made to be as flexible as possible.
10.7.3
Maximum DMA Acknowledge Delay (PD6722 only)
Register Name: Maximum DMA
Acknowledge Delay
Register Per: socket
Extended Index: 04h
Index: 2Fh
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Maximum DMA Acknowledge Delay
RW:00000000
Datasheet
79
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
During a DMA data transfer process, an ISA-based system typically follows its issuance of a DMA
acknowledge with a DMA read or write cycle. However, during a DMA write-verify operation, a
system can issue a DMA acknowledge without following it with a DMA read or write cycle.
Because a DMA-capable PC Card receives DMA acknowledgment only by reception of a DMA
read or write cycle, conditions may occur where the card never receives a DMA acknowledge. To
prevent this from happening in an ISA-based system, a maximum DMA acknowledge delay feature
has been added that generates a ‘dummy’ DMA write cycle (reads DMA data from the card) if
there are no system-generated DMA read or write cycles to the card within a programmable time.
Once a DMA acknowledge is received from the system, the PD6722 starts counting the time from
the assertion of the DACK* signal until the system issues a DMA read or write command (IOR* or
IOW*). If this interval exceeds the programmed time, the PD6722 assumes that a system writeverify is in progress and generates a dummy DMA write cycle at the PC Card interface. This allows
the passing of the DMA acknowledge (and terminal count status) to the card so it can perform any
intended verify-cycle functions.
Figure 12. Selection of Acknowledge Time-out Interval
DREQ
t2
t1
DACK*
AEN
IOR*/IOW*
t1 = time delay from DMA acknowledge to IOR* or IOW* command (specified by system design).
t2 = time to program into the Maximum DMA Acknowledge Delay register for when IOR* or IOW* falling edge does not occur (t2 > t1).
The maximum DMA acknowledge delay (t2 as shown in Figure 12) should be programmed to a
time greater than the maximum time required from the system’s issuance of a DMA acknowledge
to its issuance of a DMA read or write cycle (t1 as shown in Figure 12). The t1 time is indicated in
the specifications for the systems DMA cycle timing.
Typical system specifications for t1 are 190–270 ns, making a value of 80h for the Maximum
DMA Acknowledge Delay register suitable for many applications. If the PD6722 is used in an
add-in card application, a value of 20h may be suitable. Table 14 shows Maximum DMA
Acknowledge Delay register values to be programmed for a desired maximum DMA acknowledge
delay.
Table 14. Maximum DMA Acknowledge Delay Register Values (Sheet 1 of 2)
80
Register Value
Maximum DMA Acknowledge Delay
(25-MHz internal clock and default Setup timing)
80h
7 clocks = 280 ns
40h
8 clocks = 320 ns
C0h
9 clocks = 360 ns
20h
10 clocks = 400 ns
A0h
11 clocks = 440 ns
60h
12 clocks = 480 ns
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 14. Maximum DMA Acknowledge Delay Register Values (Sheet 2 of 2)
10.7.4
Register Value
Maximum DMA Acknowledge Delay
(25-MHz internal clock and default Setup timing)
E0h
13 clocks = 520 ns
10h
14 clocks = 560 ns
90h
15 clocks = 600 ns
50h
16 clocks = 640 ns
D0h
17 clocks = 680 ns
30h
18 clocks = 720 ns
B0h
19 clocks = 760 ns
External Data (PD6722 only, Socket A, Index 2Fh)
Register Name: External Data
Register Per: socket
Extended Index: 0Ah
Index: 2Fh only
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3
External Data
2
External Data
1
External Data
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Bits 7:0 — External Data
This register is updated and accessed according to the setting of bits 3 and 4 of the Socket A
Extension Control 2 register (Index 2Fh, Extended Index 0Bh).
Table 15. Functions of Socket A External Data Register
Socket A Extension Control 2
Note:
Function of Socket A External Data Register
Bit 4: GPSTB
on IOW*
Bit 3: GPSTB
on IOR*
0
0
Scratchpad
0
1
External read port: A_GPSTB is a read buffer enable for external data on
SD[15:8]
1
0
External write port: A_GPSTB is a write latch enable for SD[15:8] to get
latched to an external register. Reads of Socket A External Data register
produce the value written to the latch.
1
1
Reserved
For software compatibility of external data access accross the PC Card (PCMCIA) controller
product line, the Socket A External Data register should only be used as a write port and not as a
read port. Also for compatibility, only the lower nibble of External Data should be accessed and
the upper nibble should be ignored.
Refer to “Using GPSTB Pins for External Port Control (PD6722 only)” on page 91 for more
information on the use of the External Data register.
Datasheet
81
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
10.7.5
External Data (PD6722 only, Socket A, Index 6Fh)
Register Name: External Data
Register Per: socket
Extended Index: 0Ah
Index: 6Fh only
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3 or
B_VS2# Input
External Data
2 or
B_VS1# Input
External Data
1 or
A_VS2# Input
External Data
0 or
A_VS1# Input
RW:0
RW:0
RW:0
RW:0
R:0
R:0
R:0
R:0
Bits 7:0 — External Data
This register is updated and accessed according to the setting of bits 3 and 4 of the Socket B
Extension Control 2 register (Index 6Fh, Extended Index 0Bh).
Table 16. Functions of Socket B External Data Register (PD6722 only)
Socket B Extension Control 2
Note:
Function of Socket B External Data Register
Bit 4: GPSTB
on IOW*
Bit 3: GPSTB
on IOR*
0
0
Bits 7:4 — scratchpad
Bits 3:2 — Socket B VS2# and VS1# levels (PD6722 only)
Bits 1:0 — Socket A VS2# and VS1# levels
0
1
External read port: B_GPSTB is a read buffer enable for external data on
SD[15:8].
1
0
External write port: B_GPSTB is a write latch enable for SD[15:8] to get
latched to an external register. Reads of Socket B External Data register
produce the value written to the latch.
1
1
Reserved
For software compatibility of external data access accross the PC Card (PCMCIA) controller
product line, the Socket B External Data register should only be used as a read port and not as a
write port. Also for compatibility, only the lower nibble of External Data should be accessed and
the upper nibble should be ignored. For software compatibility with VS1# and VS2# detection
software, when Socket B is used as a read port, socket VS1# and VS2# signals should be connected
to the external read buffer as shown in Figure 15 on page 96.
Refer to “Using GPSTB Pins for External Port Control (PD6722 only)” on page 91 for more
information on the use of the External Data register, and “VS1# and VS2# Voltage Detection” on
page 95 for more information on VS1# and VS2# detection.
82
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
10.7.6
Extension Control 2 (PD6722 only)
Register Name: Extension Control 2
Register Per: socket
Extended Index: 0Bh
Index: 2Fh
Bit 7
Bit 6
Register Compatibility Type: ext.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
RW:00
Bit 5 — Active-high GPSTB
0
GPSTB ouputs are active-low.
1
GPSTB ouputs are active-high.
Bit 4 — GPSTB on IOW* (PD6722 only)
0
A_GPSTB (PD6722) pins are used as voltage sense.
1
A_GPSTB (PD6722) pins are used to strobe I/O writes on SD[15:8].
Note that setting this bit forces the pull-ups on A_GPSTB (PD6722) to be off, independent of the
setting of the Pull-Up Control bit (index 2Fh, extended index 03h, bit 5). See “External Data
(PD6722 only, Socket A, Index 6Fh)” on page 82, “Using GPSTB Pins for External Port Control
(PD6722 only)” on page 91, and “VS1# and VS2# Voltage Detection” on page 95.
Bit 3 — GPSTB on IOR* (PD6722 only)
0
B_GPSTB (PD6722) pins (socket B) are used as voltage sense.
1
B_GPSTB (PD6722) pins are used to strobe I/O reads on SD[15:8].
Note that setting this bit forces the pull-ups on B_GPSTB (PD6722) to be off, independent of the
setting of the Pull-Up Control bit (index 6Fh, extended index 03h, bit 5). See “External Data
(PD6722 only, Socket A, Index 6Fh)”, “Using GPSTB Pins for External Port Control (PD6722
only)”, and “VS1# and VS2# Voltage Detection”.
Bit 2 — Totem-pole GPSTB
0
GPSTB ouputs are open-collector.
1
GPSTB ouputs are totem-pole.
When GPSTB outputs are totem-pole, their ‘high’ level is driven to the level of the +5V pin,
instead of high-impedance.
Datasheet
83
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
11.0
Timing Registers
The following information about the timing registers is important:
• All timing registers take effect immediately and should only be changed when the FIFO is
empty (see the FIFO Control register on “FIFO Control” on page 72).
• Selection of Timing 0 or Timing 1 register sets is controlled by I/O Window Control, bit 3
and/or bit 7 (see “I/O Window Control” on page 58).
11.1
Setup Timing 0–1
Register Name: Setup Timing 0–1
Register Per: socket
Index: 3Ah, 3Dh
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Setup Prescalar Select
Setup Multiplier Value
RW:00
RW:000001
Bit 1
Bit 0
There are two separate Setup Timing registers, each with identical fields. These registers are
located at the following indexes:
Index
3Ah
3Dh
Setup Timing
Setup Timing 0
Setup Timing 1
The Setup Timing register for each timing set controls how long a PC Card cycle’s command (that
is, -OE, -WE, -IORD, -IOWR; see Table 2 on page 20) setup will be, in terms of the number of
internal clock cycles.
The overall command setup number of clocks S is programmed by selecting a 2-bit prescaling
value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a
multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command
setup timing length according to the following formula:
S = (Npres × Nval) + 1
The value of S, representing the number of internal clock cycles for command setup, is then
multiplied by the internal clock’s period to determine the command setup time (see “PC Card Bus
Timing Calculations” on page 109 for further discussion).
Bits 5:0 — Setup Multiplier Value
This field indicates an integer value Nval from 0 to 63; it is combined with a prescalar value (bits
7:6) to control the length of setup time before a command becomes active.
84
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bits 7:6 — Setup Prescalar Select
00
Npres = 1
01
Npres = 16
10
Npres = 256
11
Npres = 8192
This field chooses one of four prescalar values Npres that are combined with the value of the Setup
Multiplier Value (bits 5:0) to control the length of setup time before a command becomes active.
11.2
Command Timing 0–1
Register Name: Command Timing 0–1
Register Per: socket
Index: 3Bh, 3Eh
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Command Prescalar Select
Command Multiplier Value
RW:00
RW:000110/0011111
Bit 1
Bit 0
1. Timing set 0 (index 3Bh) resets to 06h for socket timing equal to standard AT-bus-based cycle times. Timing set 1 (3Eh)
resets to 0Fh for socket timings equal to standard AT-bus timing using one additional wait state.
There are two separate Command Timing registers, each with identical fields. These registers are
located at the following indexes:
Index
3Bh
3Eh
Command Timing
Command Timing 0
Command Timing 1
The Command Timing register for each timing set controls how long a PC Card cycle’s command
(that is, -OE, -WE, -IORD, -IOWR; see Table 2 on page 20) active time will be, in terms of the
number of internal clock cycles.
The overall command timing length C is programmed by selecting a 2-bit prescaling value (bits 7:6
of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value
(bits 5:0) to which that prescalar is multiplied to produce the overall command timing length
according to the following formula:
C = (Npres × Nval) + 1
The value of C, representing the number of internal clock cycles for a command, is then multiplied
by the internal clock’s period to determine the command active time (see “PC Card Bus Timing
Calculations” on page 109 for further discussion).
Datasheet
85
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bits 5:0 — Command Multiplier Value
This field indicates an integer value Nval from 0 to 63; it is combined with a prescalar value (bits
7:6) to control the length that a command is active.
Bits 7:6 — Command Prescalar Select
00
Npres = 1
01
Npres = 16
10
Npres = 256
11
Npres = 8192
This field chooses one of four prescalar values Npres that are combined with the value of the
Command Multiplier Value (bits 5:0) to control the length that a command is active.
11.3
Recovery Timing 0–1
Register Name: Recovery Timing 0–1
Register Per: socket
Index: 3Ch, 3Fh
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Recovery Prescalar Select
Recovery Multiplier Value
RW:00
RW:000011
Bit 1
Bit 0
There are two separate Recover Timing registers, each with identical fields. These registers are
located at the following indexes:
Index
3Ch
3Fh
Recovery Timing
Recovery Timing 0
Recovery Timing 1
The Recovery Timing register for each timing set controls how long a PC Card cycle’s command
(that is, -OE, -WE, -IORD, -IOWR; see Table 2 on page 20) recovery will be, in terms of the
number of internal clock cycles.
The overall command recovery timing length R is programmed by selecting a 2-bit prescaling
value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a
multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command
recovery timing length according to the following formula:
R = (Npres × Nval) + 1
The value of R, representing the number of internal clock cycles for command recovery, is then
multiplied by the internal clock’s period to determine the command recovery time (see “PC Card
Bus Timing Calculations” on page 109 for further discussion).
86
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Bits 5:0 — Recovery Multiplier Value
This field indicates an integer value Nval from 0 to 63; it is combined with a prescalar value (bits
7:6) to control the length of recovery time after a command is active.
Bits 7:6 — Recovery Prescalar Select
00
Npres = 1
01
Npres = 16
10
Npres = 256
11
Npres = 8192
This field chooses one of four prescalar values Npres that are combined with the value of the
Recovery Multiplier Value (bits 5:0) to control the length of recovery time after a command is
active.
Datasheet
87
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
12.0
ATA Mode Operation
The PD67XX PC Card interfaces can be dynamically configured to support a PC Card–compatible
ATA disk interface (commonly known as ‘IDE’) instead of the standard PC Card interface. Disk
drives that can be made mechanically-compatible with PC Card dimensions can thus operate
through the socket using the ATA electrical interface.
Configuring a socket to support ATA operation changes the function of certain card socket signals
to support the needs of the ATA disk interface. Table 17 lists each interface pin and its function
when a PD67XX card socket is operating in ATA mode. Refer to application note AN-PD5,
Configuring PCMCIA Sockets for ATA Drive Interface, for more information.
All register functions of the PD67XX are available in ATA mode, including socket power control,
interface signal disabling, and card window control. No memory operations are allowed in ATA
mode.
Table 17. ATA Pin Cross-Reference (Sheet 1 of 3)
Function
PC Card Socket
Pin Number
PC Card
Interface
ATA Interface
1
Ground
Ground
2
D3
D3
3
D4
D4
4
D5
D5
5
D6
D6
6
D7
D7
7
-CE1
-CS0
8
A10
n/c
9
-OE
-ATA (always low)
10
A11
n/c
11
A9
CS1*
12
A8
n/c
13
A13
n/c
14
A14
n/c
15
-WE
n/c
16
-IREQ
IREQ
17
VCC
VCC
18
VPP1
n/c
19
A16
n/c
20
A15
n/c
21
A12
n/c
22
A7
n/c
1. Not supported by the PD67XX.
88
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 17. ATA Pin Cross-Reference (Sheet 2 of 3)
Function
PC Card Socket
Pin Number
PC Card
Interface
ATA Interface
23
A6
n/c
24
A5
n/c
25
A4
n/c
26
A3
n/c
27
A2
A2
28
A1
A1
29
A0
A0
30
D0
D0
31
D1
D1
32
D2
D2
33
-IOIS16
-IOIS16
34
Ground
Ground
35
Ground
Ground
36
-CD1
-CD1
37
D11
D11
38
D12
D12
39
D13
D13
40
D14
D14
41
D15
D15
42
-CE2
-CS1
43
VS1
VS1
44
-IORD
-IORD
45
-IOWR
-IOWR
46
A17
n/c
47
A18
n/c
48
A19
n/c
49
A20
n/c
50
A21
n/c
51
VCC
VCC
52
VPP2
n/c
53
A22
n/c
54
A23
VU
55
A24
-M/S
56
A25
CSEL
57
VS2
VS2
1. Not supported by the PD67XX.
Datasheet
89
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 17. ATA Pin Cross-Reference (Sheet 3 of 3)
Function
PC Card Socket
Pin Number
PC Card
Interface
ATA Interface
58
RESET
RESET*
59
-WAIT
IOCHRDY
60
-INPACK
DREQ1
61
-REG
-DACK1
62
-SPKR
-LED
63
-STSCHG
-PDIAG1
64
D8
D8
65
D9
D9
66
D10
D10
67
-CD2
-CD2
68
Ground
Ground
1. Not supported by the PD67XX.
90
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
13.0
Using GPSTB Pins for External Port Control
(PD6722 only)
The PD6722 provides pins that can be programmed to function as general-purpose strobes to
external latches or buffers, allowing them to serve as read ports or write ports mapped into the
PD6722 register set.
Configuring a GPSTB pin as a read port allows an easy way to read additional card status such as
VS1# and VS2# levels, a card socket microswitch status, a card port cover microswitch status, card
eject solenoid position status, or general system signal status.
Configuring a GPSTB pin as a write port allows an easy way to control additional features such as
card-state LEDs, card mechanism solenoids, or motor eject mechanisms.
13.1
Control of GPSTB Pins
The Extension Control 2 register controls the GPSTB pins.
For the PD6722, the A_GPSTB pin is controlled by the Extension Control 2 register at Socket A
(index 2Fh, extended index 0Bh), and the B_GPSTB pin is controlled by the Extension Control 2
register at Socket B (index 6Fh, extended index 0Bh).
The following table summarizes how the GPSTB pins are configured and how data is accessed
from external ports created by using a GPSTB pin to control an external read or write port.
Table 18. Registers for Control and Data of GPSTB Pins
Pin Name
GPSTB Control Access
External Port Data Access
A_GPSTB (PD6722)
Set register 2E to 0Bh,
access Extension Control 2 register at 2F
Set register 2E to 0Ah,
access External Data register at 2F
B_GPSTB (PD6722)
Set register 6E to 0Bh,
access Extension Control 2 register at 6F
Set register 6E to 0Ah,
access External Data register at 6F
Programming the Extension Control 2 Register
There is one Extension Control 2 register per GPSTB pin. Each register has identical GPSTB
control bits, as follows. See also the description of this register in “Extension Control 2 (PD6722
only)” on page 83.
Register Name: Extension Control 2
Index: 2Fh and 6Fh
Bit 7
Bit 6
Register Per: socket
Extended Index: 0Bh
Register Compatibility Type: ext.
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
RW:00
Datasheet
Bit 1
Bit 0
91
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 5 allows programming of the active level of GPSTB, with the default being active-low. Setting
bit 5 to ‘1’ causes a GPSTB output to be low normally and high (active) upon external data access.
Bit 4 controls use of the respective GPSTB pin as a write strobe for an external general-purpose
latch. When the respective extended index is set to 0Ah and the index register is set to the
respective 2Fh or 6Fh setting, I/O writes that access address 3E1h will result in the respective
GPSTB signal being driven active for the duration of the ISA bus IOW* signal being driven low.
Bit 3 controls use of the respective GPSTB pin a read strobe for an external general-purpose buffer.
When the respective extended index is set to 0Ah and the index register is set to the respective 2Fh
or 6Fh setting, I/O reads that access address 3E1h will result in the respective GPSTB signal being
driven active for the duration of the ISA bus IOR* signal being driven low.
Bit 2 cause the GPSTB output to be totem-pole instead of the default open-collector configuration.
When GPSTB outputs are totem-pole, their ‘high’ level is driven to the voltage of the ‘+5V’ pin,
instead of to high-impedance.
If neither bit 3 nor bit 4 is set, the respective GPSTB pin functions as a reserved input in a PD6722
that is an internal pull-up to the ‘+5V’ pin. This internal pull-up is turned off whenever the GPSTB
pin is configured as a general-purpose strobe, or when the respective socket’s Pull-up Control bit is
set to ‘1’.
Bits 7:6 and 1:0 are reserved and must be programmed to ‘0’. These bits should not be used as
scratchpad bits.
External Data Port Access through the External Data Register
Data to be accessed from an external read or write port is mapped to the respective External Data
register at Extended Index 0Ah. This allows external data to be accessed as if it were a register in
the PD67XX register set.
To achieve this mapping, the external data port’s buffer or latch data connections should be made to
SD[15:8] of the system bus for 16-bit systems, and to SD[7:0] of the system bus for 8-bit systems.
To support readback of data written to an external I/O port by use of a GPSTB pin, a shadow of the
external data register exists, which is read when an I/O read is done from the external data register
location corresponding to a GPSTB pin programmed as a write strobe.
For more information on the Socket A and Socket B versions of this register, see the description of
this register in “External Data (PD6722 only, Socket A, Index 2Fh)” on page 81 and “External Data
(PD6722 only, Socket A, Index 6Fh)” on page 82.
Register Name: External Data
Register Per: socket
Extended Index: 0Ah
Index: 2Fh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3
External Data
2
External Data
1
External Data
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
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Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
13.2
Example Implementations of GPSTB-Controlled Read and
Write Ports
Figure 13. Example GPSTB Write Port (Extension Control 2 bits 4:3 are ‘10’)
Pull-up†
PD6722
IOW*
Latch
(for example, ’374)
IOW*
EXT_WR*
GPSTB
CK
O7
General-
SD[15:0]
SD[15:0]
Purpose
(16-bit bus)
Outputs
SD[15:8]
D
O0
RES
PWRGOOD
†
Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
In this mode, Extension Control 2 register bit 4 is set to ‘1’ enabling the GPSTB pin to function as
a write strobe. Writes to the respective extended index 0Ah cause the respective GPSTB to go
active (low) for the duration of the system’s IOW* pulse.
On writes, data is written to both the external latch and the internal shadow copy of the External
Data register. A read of the respective extended index 0Ah would produce the last value written to
the latch.
Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes
all ‘0’s at its outputs when the PD67XX is reset.
Figure 14. Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘01’)
PD6722
IOR*
Tristate Buffer
(for example, ’244)
IOR*
GPSTB
SD[15:0]
EXT_RD*
D7
GeneralPurpose
SD[15:0]
Pull-up
(16-bit bus)
†
SD[15:8]
Inputs
O
D0
OE
†
Datasheet
Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
93
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
In this mode, Extension Control 2 register bit 3 is set to ‘1’, enabling the respective GPSTB pin to
function as a read strobe. Reads from the corresponding extended index 0Ah cause GPSTB to go
active (default active level is low) for the duration of the system’s IOR* pulse.
Note:
13.3
Data is still written to the shadowed External Data register on writes to Extended Index 0Ah but is
not visible.
GPSTB in Suspend Mode
GPSTB read and write strobes operate while the device is in suspend mode, but they are not
allowed when the device is in hardware-assisted ‘Super-Suspend’ mode (AEN held high while in
Suspend mode).
A clock to the PD6722 is not required for the external signal at GPSTB to occur, but shadowing of
write values in the internal register at Extended Index 0Ah requires that the PD67XX is not in
Suspend mode so there is an active internal clock for register writes.
94
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
14.0
VS1# and VS2# Voltage Detection
The PD6722 provides support for VS1# and VS2# voltage sense for environments where special
low-voltage keyed PC Card sockets are to be used. With a low-voltage keyed socket, it is necessary
to determine the operating voltage range of a card before applying power to it. The PD6722
supports reading of the levels on a socket’s VS1# and VS2# pins through a uniform extended
register programming model using Socket B extended register 0Ah. The programming model is as
follows:
Register Name: External Data
Register Per: socket
Extended Index: 0Ah
Index: 6Fh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
B_VS2 Input
B_VS1 Input
A_VS2 Input
A_VS1 Input
RW:0
RW:0
RW:0
RW:0
R:0
R:0
R:0
R:0
For voltage detection on the PD6710, refer to the 5V_DET pin.
On the PD6722, the B_GPSTB pin is programmed as a general-purpose read strobe. The VS1# and
VS2# pins from the A and B sockets are connected to the external half of a ’244 buffer as follows
(which allows Socket A VS1 and VS2 to appear as bits 0 and 1, and Socket B VS1 and VS2 to
appear as bits 2 and 3):
Datasheet
95
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 15. VS1# and VS2# Sensing on a PD6722
(Socket B Extension Control 2 bit 3 is ‘1’)
5-V Supply
PD6722
VS_RD*
+5V
IOR*
IOR*
†
B_GPSTB
SD[15:0]
Tristate Buffer (such as 1/2 of a ’244)
SD[15:0]
(16-bit bus)
D3
SD[11:8]
D0
OE
Socket A
VS1#
Pin 43
VS2#
Pin 57
Socket B
†
96
VS1#
Pin 43
VS2#
Pin 57
Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
15.0
DMA Operation (PD6722 only)
15.1
DMA Capabilities of the PD6722
The PD6722 include support of a DMA-capable PC Card slave and the movement of DMA data to/
from the card with the ISA bus as a DMA master.
Only one socket at a time should be enabled for DMA transfer because the ISA bus DMA
handshake signals are shared between both socket interfaces.
DMA transfers to and from the DMA-capable PC Card may be 8- or 16-bit, as indicated by the size
of the ISA bus DMA cycle.
Note:
15.2
Transfer size at socket interface is the same as transfer size on an ISA bus. For 8-bit DMA
transfers, connect PD6722 DMA handshake signals to ISA bus DMA channels 0, 1, 2, or 3. For 16bit transfers, connect PD6722 DMA handshake signals to ISA bus DMA channels 5, 6, or 7.
DMA-Type PC Card Cycles
Transfer of DMA data to or from a card is achieved through use of a special DMA-type PC Card
interface cycle. This cycle is defined to not conflict with standard PC Card memory or I/O cycles.
A card that is DMA-capable can distinguish PC Card interface cycle types presented by the
PD6722 according to the following table:
Table 19. Four Card Cycle Types for DMA-Type PC Card Interface
Socket Interface Cycle Type
Function of -WE/-OE
Function of
-IORD/-IOWR
Function of -REG
Card Memory Read/Write
Data transfer signaling
Always inactive high
Always inactive high
Attribute Memory Read/Write
Data transfer signaling
Always inactive high
Always low
Card I/O Read/Write
Always inactive high
Data transfer signaling
Low = non-DMA I/O cycle
Card DMA Data Read/Write
Terminal count outputs
Data transfer signaling
High = DMA cycle
Note:
Bits 7 and 6 of the Extension Control 1 register must be nonzero for Table 19 to be true; otherwise
only standard PC Card cycles will be issued to the card.
The PC Card address is also undefined during the DMA read or write cycle.
Card DMA data read and write cycles transfer DMA data to or from a DMA-capable PC Card.
These cycles are distinguished from normal card I/O cycles by the -REG signal being high during
the cycle, which is an undefined condition in the PC Card Standard.
Datasheet
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
15.3
ISA Bus DMA Handshake Signal
A DMA request from the card is passed to the ISA bus as long as the socket interface FIFO is
empty. IRQ10 is used as the DMA request output to the ISA bus when bit 2 of the Misc Control 2
register is ‘1’. When bit 2 of the Misc Control 2 register is ‘1’, IRQ9 is redefined as the active-low
DMA acknowledge input from the ISA bus. This signal must remain active for all DMA transfers
through the PD6722.
Figure 16. DMA Handshake Connections to the ISA Bus
to Make the PD6722 DMA-Capable
PD6722
ISA
DREQ
IRQ10
-DACK
IRQ9
Bus
TC
-VPP_VALID
Terminal counts are passed through to the card from the PD6722 -VPP_VALID pin when bit 6 of
the Misc Control 2 register is ‘1’. For a DMA write process, the last-cycle terminal count
condition is indicated by -OE being active-low during a card DMA data read cycle. For a DMA
read process, terminal count is indicated by -WE being active-low during the last card cycle.
15.4
Configuring the PD6722 Registers for a DMA Transfer
Program the registers as follows to configure a PD6722 socket interface for DMA transfer to/from
a DMA-capable PC Card:
1. Select which pin on the PC Card interface will serve as the DMA request input.
2. Configure the socket interface as I/O-capable.
3. Prevent dual-interpretation of socket interface DMA handshake signals.
4. Set the DMA Enable bit.
15.4.1
Programming the DMA Request Pin from the Card
The PD6722 allows selection of one from three PC Card interface inputs to be redefined as the
DMA request input, and it also allows programming of the active level of the selected input. This is
done by setting bits 7 and 6 of the Extension Control 1 register to the desired values matching
those of the DMA-capable PC Card to be used.
Once this selection of DMA request input is complete, the PC Card interface is configured at the
signal level for DMA card interfacing.
The following table shows how the PD6722 socket interface signals are redefined when a card is in
DMA card interface mode:
98
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Standard I/O Card
Interface Signal Name
DMA-Capable Card Interface
Signal Usage
When Signal Redefinition for DMA Interface
is Effective
-IOIS16
-IOIS16 or may be selected as the active-low
DMA request input
Extension Control 1 register bits 7-6 = ‘10’
(BVD2/)
-SPKR/-LED
-SPKR/-LED or may be selected as the activelow DMA request input
Extension Control 1 register bits 7-6 = ‘11’
-INPACK
-INPACK or may be selected as the active-low
DMA request input
Extension Control 1 register bits 7-6 = ‘01’
-REG
-REG during standard cycles, active-high
DACK during DMA read/write cycles
Only during actual card DMA read or write
cycle
-OE
-OE during standard cycles, active-low -TC
during DMA write cycles
During DMA write cycles (that is, when -REG is
high and -IORD is low)
-WE
-WE during standard cycles, active-low -TC
during DMA read cycles
During DMA read cycles (that is, when -REG is
high and -IOWR is low)
Figure 17. Card DMA Request and Acknowledge Handshake with Terminal Count
PD6722
-IOIS16, -SPKR, or -INPACK
-REG
-OE/-WE
a
-DREQ
DACKa
-TC
PC Card
-IOIS16, -SPKR, or -INPACK
-REG
-OE/-WE
A DMA cycle is the DMA acknowledge to the card.
Notice that the DMA acknowledge to the card as -REG high is only active during the actual DMA
read or write card cycle. This means there is no mechanism to deassert DACK to the card: The card
must understand that receiving the first DMA cycle is its DMA acknowledgment.
15.4.2
Configuring the Socket Interface for I/O
For DMA support, bit 5 of the Interrupt and General Control register must be set to ‘1’ to put the
card interface in I/O Card Interface mode.
15.4.3
Preventing Dual Interpretation of DMA Handshake Signals
If the WP/-IOIS16 pin is being used as the DMA request line, the following should be considered:
1. Bit 4 of the Interface Status register is now the level of the DMA request line from the card.
2. Bit 5 of the socket’s two I/O Window Control registers should be set to ‘0’.
If a socket’s BVD2/-SPKR pin is being used as the DMA request line, speaker or LED output from
that socket is not available.
If -INPACK is selected as the DMA request input, then bit 7 of the Misc Control 1 register should
be set to ‘0’ to disable use of this signal as input acknowledge control.
Datasheet
99
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
No other register bits require special settings to accommodate DMA support on a socket interface.
15.4.4
Turning On DMA System
The DMA System bit (bit 6 of the Misc Control 2 register) should be programmed to ‘1’ to allow
DMA operation and to redefine ISA bus interface pins for DMA support as in Figure 16.
15.4.5
The DMA Transfer Process
As soon as the selected DMA request input from the card becomes active (low) and the FIFO
empties, IRQ10 becomes active (high), signifying a DMA request to the system. The system then
responds with an active (low) -DACK at IRQ9, which enables the PD6722 to decode any ISA bus
DMA transfers that may occur and perform the corresponding transfers at the card. Normal card I/
O or memory reads or writes may be interspersed with DMA read and write cycles.
15.4.6
Terminal Count to Card at Conclusion of Transfer
At the conclusion of each transfer process, systems send active (high) TC (terminal count) pulses to
the -VPP_VALID pin during the last DMA cycles to the PD6722.
For a DMA write cycle, TC active is signaled at the socket interface as the -OE pin going low
during DMA-type read cycles from the PC Card.
For a DMA read cycle, TC active is signaled as the -WE pin going low during DMA-type write
cycles to the PC Card.
100
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
16.0
Electrical Specifications
16.1
Absolute Maximum Ratings
Caution:
16.2
Ambient temperature under bias
0°C to 70°C
Storage temperature
−65°C to 150°C
Voltage on any pin (with respect to ground)
−0.5 volts to 0.5 volts greater than voltage of +5V pin,
respective to ground
Operating power dissipation
500 mW
Suspend power dissipation
10 mW
Power supply voltage
7 volts
Injection current (latch up)
25 mA
Stresses above those listed may cause permanent damage to system components. These are stress
ratings only; functional operation at these or any conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect system reliability.
DC Specifications
Table 20. General DC Specifications
Symbol
CIN
COUT
Parameter
MAX
Unit
Input Capacitance
10.0
pF
Output Capacitance
10.0
pF
−10.0
10.0
µA
−30
−400
µA
IIL
Input Leakage
IPU
Internal Pull-up Current
MIN
Conditions
0 < VIN < respective VCC supply pin
Table 21. PC Card Bus Interface DC Specifications (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Unit
SOCKET_VCC5V
Power Supply Voltage
4.5
5.5
V
SOCKET_VCC3V
Power Supply Voltage
3.0
3.6
V
VIH
VIL
Datasheet
Conditions
Normal operation
2.0
V
CORE_VDD = 3.0 V,
Misc Control 2 register, bit 3 is ‘0’
2.0
V
CORE_VDD = 4.5 V,
Misc Control 2 register, bit 3 is ‘1’
0.8
V
CORE_VDD = 3.6 V,
Misc Control 2 register, bit 3 is ‘0’
0.8
V
CORE_VDD = 5.5 V,
Misc Control 2 register, bit 3 is ‘1’
Input High Voltage
Input Low Voltage
101
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 21. PC Card Bus Interface DC Specifications (Sheet 2 of 2)
Symbol
Parameter
VIHC
Input High Voltage CMOS
VILC
Input Low Voltage CMOS
VOH
Output High Voltage
VOHC
Output High Voltage CMOS
MIN
MAX
Unit
Conditions
V
CORE_VDD = 4.5 V,
Misc Control 2 register, bit 3 is ‘0’
V
CORE_VDD = 5.5 V,
Misc Control 2 register, bit 3 is ‘0’
2.4
V
At rated IOH,
respective SOCKET_VCC = 3.0 V
SOCKET_VC
C – 0.5
V
At rated IOHC,
respective SOCKET_VCC = 3.0 V
V
At rated IOL
0.7 VDD
0.2 VDD
VOL
Output Low Voltage
IOH
Output High Current
−2
mA
Respective SOCKET_VCC = 3.0 V,
VOH = 2.4V
IOHC
Output High Current CMOS
−1
mA
Respective SOCKET_VCC = 3.0 V,
VOHC = SOCKET_VCC – 0.5 V
Output Low Current
2
mA
Respective SOCKET_VCC = 3.0 V,
VOL = 0.5 V
IOL
0.5
Table 22. ISA Bus Interface DC Specifications (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Unit
Conditions
ISA_VCC5V
Power Supply Voltage
4.5
5.5
V
Normal operation
ISA_VCC3V
3.6
V
Normal operation
V
CORE_VDD = 3.0 V
V
CORE_VDD = 3.6 V
V
CORE_VDD = 4.5 V
V
CORE_VDD = 5.5 V
2.4
V
At rated IOH, ISA_VCC = 3.0 V
ISA_VCC
– 0.5
V
At rated IOHC, ISA_VCC = 3.0 V
V
At rated IOL
Power Supply Voltage
3.0
1
Input High Voltage
2.0
VIL1
Input Low Voltage
VIH
VIHC
1
1
Input High Voltage CMOS
VILC
Input Low Voltage CMOS
VOH
Output High Voltage
VOHC
VOL
IOH
IOHC
Output High Voltage CMOS
0.8
0.7 VDD
1
2
0.2 VDD
Output Low Voltage
0.5
Output Current High,
2-mA-type driver
−2
mA
Output Current High,
12-mA-type driver
−5
mA
Output Current High,
16-mA-type driver
−5
mA
Output Current High CMOS,
2-mA-type driver
−1
mA
Output Current High CMOS,
12-mA-type driver
−1
mA
Output Current High CMOS,
16-mA-type driver
−1
mA
ISA_VCC = 3.0 V,
VOH = 2.4 V
ISA_VCC = 3.0 V,
VOHC = ISA_VCC – 0.5 V
1. When the CORE_VDD voltage is 3.3 V, input thresholds are TTL compatible; when the CORE_VDD voltage is 5 V, input
thresholds are CMOS compatible.
2. The value of the input threshold level is dependent on the voltage applied to VDD pins of the PD67XX.
102
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 22. ISA Bus Interface DC Specifications (Sheet 2 of 2)
Symbol
IOL
Parameter
MIN
MAX
Unit
Output Current Low,
2-mA-type driver
2
mA
Output Current Low,
12-mA-type driver
12
mA
Output Current Low,
16-mA-type driver
16
mA
Conditions
ISA_VCC = 3.0 V,
VOL = 0.5 V
1. When the CORE_VDD voltage is 3.3 V, input thresholds are TTL compatible; when the CORE_VDD voltage is 5 V, input
thresholds are CMOS compatible.
2. The value of the input threshold level is dependent on the voltage applied to VDD pins of the PD67XX.
Table 23. Power Control Interface (+5V Powered) DC Specifications
Symbol
Parameter
MIN
MAX
Unit
5.5
V
V
+5V pin voltage = 4.5 V
0.8
V
+5V pin voltage = 5.5 V
2.4
V
+5V pin voltage = 4.5 V, IOH = −5 mA
+5V
voltage –
0.5
V
+5V pin voltage = 4.5 V, IOH = −1 mA
+5V
+5V Supply Voltage
Highest
VCC – 0.3
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
VOH
Output High Voltage
VOHC
Output High Voltage CMOS
Conditions
VOL
Output Low Voltage
IOH
Output Current High,
16-mA-type driver
-5
mA
Respective +5V pin voltage = 4.5 V,
VOH = 2.4 V
IOHC
Output Current High CMOS,
16-mA-type driver
−1
mA
Respective +5V pin voltage = 4.5 V,
VOHC = +5V pin voltage – 0.5 V
Output Current Low,
16-mA-type driver
16
mA
Respective +5V pin voltage = 4.5 V,
VOL = 0.5 V
IOL
0.5
V
Table 24. Operating Current Specifications
Symbol
Parameter
MIN
TYP
MAX
Unit
Conditions
<6
8
< 20
mA
CORE_VDD = 3.3 V;
+5V, SOCKET_VCC, and
ISA_VCC = 5.0 V;
PDISS = < 85 mW
Icctot(1)
Power Supply Current,
operating
Icctot(2)
Power Supply Current,
Suspend1
< 150
µA
CORE_VDD = 3.3 V;
+5V, SOCKET_VCC, and
ISA_VCC = 5.0 V;
PDISS = < 2 mW
Icctot(3)
Power Supply Current, Super
Suspend,
No Clocks1
< 20
µA
CORE_VDD = 3.3 V;
+5V, SOCKET_VCC, and
ISA_VCC = 5.0 V;
PDISS = < 1 mW
1. No cards in sockets; for PD6722, bit 5 of the DMA Control register is ‘1’.
Datasheet
103
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
16.3
AC Timing Specifications
This section includes system timing requirements for the PD67XX. Timings are provided in
nanoseconds (ns), at TTL input levels, with the ambient temperature varying from 0°C to 70°C,
and VCC varying from 3.0 to 3.6 V or 4.5 to 5.5 V DC. The AT bus speed is 10 MHz unless
otherwise noted. Note that an asterisk (*) denotes an active-low signal for the ISA bus interface,
and a dash (-) denotes an active-low signal for the PC Card socket interface.
• Additionally, the following statements are true for all timing information:
• All timings assume a load of 50 pF.
• TTL signals are measured at TTL threshold; CMOS signals are measured at CMOS threshold.
Table 25. List of AC Timing Specifications
Title
16.4
Page Number
Table 26 “ISA Bus Timing”
104
Table 27 “Reset Timing”
107
Table 28 “Pulse Mode Interrupt Timing”
107
Table 29“General-Purpose Strobe Timing”
108
Table 30 “Input Clock Specification”
108
Table 31 “Memory Read/Write Timing (Word Access)”
111
Table 32 “Word I/O Read/Write Timing”
112
Table 33 “PC Card Read/Write Timing when System Is 8-Bit”
113
Table 34 “Normal Byte Read/Write Timing”
114
Table 35 “16-Bit System to 8-Bit I/O Card: Odd Byte Timing”
115
Table 36 “DMA Read Cycle Timing (PD6722 only)”
116
Table 37 “DMA Write Cycle Timing (PD6722 only)”
118
Table 38 “DMA Request Timing (PD6722 only)”
119
ISA Bus Timing
Table 26. ISA Bus Timing (Sheet 1 of 2)
Symbol
1.
2.
3.
4.
5.
Parameter
MIN
MAX
Unit
40
ns
t1
MEMCS16* active delay from LA[23:17] valid
t1a
LA[23:17] setup to ALE inactive
30
ns
t1b
LA[23:17] hold from ALE inactive
5
ns
t2
IOCS16* active delay from SA[15:0]1
40
ns
AEN must be inactive for t2, t3, and t6 timing specifications to be applicable.
Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
104
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 26. ISA Bus Timing (Sheet 2 of 2)
Symbol
t2a
t3
t4
MIN
IOCS16* inactive delay from SA[15:0]1
MAX
40
Unit
ns
SA[16:0], SBHE* setup to any Command active1, 2
30
ns
LA[23:17] latching by ALE to any Command active
90
ns
Any Command active to IOCHRDY inactive (low)
t4a
IOCHRDY three-state from Command inactive
3
4
40
5
ns
30
t5
MEMCS16* inactive delay from unlatched LA[23:17]
t6a
IOW* or IOR* pulse width1
140
ns
t6b
MEMW* or MEMR* pulse width1
180
ns
t7
Any Command inactive to next Command active
100
ns
t8
Address or SBHE* hold from any Command inactive
t9
40
0
ns
ns
Data valid from MEMW* active5
40
ns
Data valid from IOW* active
40
ns
Data hold from MEMW* inactive
5
ns
Data hold from IOW* inactive
5
ns
t11
Data delay from IOR* active, for internal registers
0
130
t12
Data delay from IOCHRDY active
15
ns
t13
Data hold from IOR* or MEMR* inactive
0
30
ns
t14
AEN inactive setup to valid IOR* or IOW* active
40
ns
t15
AEN hold from IOR* or IOW* inactive
5
ns
t16
REFRESH* inactive setup to valid MEMR* or MEMW* active
40
ns
t17
REFRESH* inactive hold from MEMR* or MEMW* active
0
ns
t18
MEMCS16* active delay from SA[16:12] valid
40
ns
t19
*ZWS delay from MEMW* active
30
ns
t20
*ZWS hold from MEMW* inactive
15
ns
t10
1.
2.
3.
4.
5.
Parameter
ns
AEN must be inactive for t2, t3, and t6 timing specifications to be applicable.
Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
Datasheet
105
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 18. Bus Timing — ISA Bus
ALE
t1a
LA[23:17]
t1b
VALID
VALID
SA[16:0]
SBHE*
VALID
t1
t8
MEMCS16*
t18
t5
t2
t2a
IOCS16*
t3
t7
t6a, t6b
MEMR*, MEMW*
IOR*, IOW*
t4a
t4
IOCHRDY
t10
t9
WRITE DATA
t13
t11
READ DATA
t14
t12
t15
AEN
REFRESH*
t17
t16
t19
t20
ZWS*
106
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
16.4.1
Reset Timing
Table 27. Reset Timing
Symbol
Parameter
MIN
MAX
Units
t1
PWRGOOD generated reset pulse width
500
ns
t2
Clock active before end of reset1
500
ns
t3
End of PWRGOOD generated reset to first Command
500
ns
1. Clock input must be active for a minimum of 500 ns before PWRGOOD goes active to allow sufficient internal clocks to
initialize internal circuitry.
Figure 19. Reset Timing
t1
PWRGOOD
t2
CLK
MEMR*, MEMW*
IOR*, IOW*
t3
16.4.2
System Interrupt Timing
Table 28. Pulse Mode Interrupt Timing
Symbol
t1
Datasheet
Parameter
IRQ[XX] low or high
MIN
MAX
2 CLK – 10 ns
2 CLK + 10 ns
107
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 20. Pulse Mode Interrupt Timing
High-Z
High-Z
IRQ[XX]
t1
t1
High-Z = high impedance
NOTE: Each time indicated is 2 clock periods of the CLK input to the PD67XX, independent of setting of the
Bypass Frequency Synthesizer bit.
16.4.3
General-Purpose Strobe Timing (PD6722 only)
Table 29. General-Purpose Strobe Timing
Symbol
Parameter
MIN
MAX
Units
t1
GPSTB delay after IOR* or IOW* active
40
ns
t2
GPSTB delay after IOR* or IOW* inactive
40
ns
Figure 21. General-Purpose Strobe Timing
t2
t1
IOR*, IOW*
GPSTB
16.4.4
Input Clock Specification
Table 30. Input Clock Specification (Sheet 1 of 2)
Symbol
MIN
MAX
Units
t1
CLK pin input rise time
1
7
ns
t2
CLK pin input fall time
1
7
ns
t3
CLK input low period
0.4 TCLKP
0.6 TCLKP
ns
t4
CLK input high period
0.4 TCLKP
0.6 TCLKP
ns
0.5 VDD
0.5 VDD
V
Vcenter
108
Parameter
Center voltage at which period
specified
Conditions
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 30. Input Clock Specification (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Units
Conditions
TCLKP
Input clock period,
internal clock
69.84 – 0.1%
69.84 + 0.1%
ns
Normal synthesizer
operation. Misc Control 2
register, bit 0 = ‘0’. CLK
pin at 14.318 MHz.
TCLKP
Input clock period,
external clock
40 – 0.1%
40 + 0.1%
ns
Synthesizer bypassed.
Misc Control 2 register,
bit 0 = ‘1’.
CLK pin at 25 MHz.
V
CORE_VDD = 3.0 V
0.8
V
CORE_VDD = 3.6 V
V
CORE_VDD = 4.5 V
V
CORE_VDD = 5.5 V
VIHmin
CLK input high voltage
VILmax
CLK input low voltage
VIHCmin
CLK input high voltage
VILCmax
CLK input low voltage
2.0
0.7 VDD
0.2 VDD
Figure 22. Input Clock Specification
t1
t2
VIHmin, VIHCmin
Vcenter
VILmax, VILCmax
CLK
t4
t3
TCLKP
16.4.5
PC Card Bus Timing Calculations
Calculations for minimum PC Card cycle Setup, Command, and Recovery timings are made by
first calculating factors derived from the applicable timer set’s timing registers and then by
applying the factor to an equation relating it to the internal clock period.
The PC Card cycle timing factors, in terms of the number of internal clocks, are calculated as
follows:
S = (Npres × Nval) + 1
C = (Npres × Nval) + 1
R = (Npres × Nval) + 1
Datasheet
109
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Npres and Nval are the specific selected prescaler and multiplier value from the timer set’s Setup,
Command, and Recovery Timing registers (see “Timing Registers” on page 84 for a description of
these registers).
From this, a PC Card cycle’s Setup, Command, and Recovery time for the selected timer set are
calculated as follows:
Setup time = (S × Tcp) ± 10 ns
Command time = (C × Tcp) ± 10 ns
Recovery time = (R × Tcp) ± 10 ns
When the internal synthesizer is used, the calculation of the internal clock period Tcp is:
Tcp = TCLKP × 4/7
where TCLKP is the period of the clock supplied to the CLK input pin. An input frequency of
14.318 MHz at the CLK input pin results in an internal clock period of Tcp = 40 ns.
When the internal synthesizer is bypassed, Tcp = TCLKP. An input frequency of 25 MHz in this
circumstance would also result in an internal clock period of Tcp = 40 ns.
The timing diagrams that follow were derived for a PD67XX using the internal synthesizer and a
14.318-MHz CLK pin input. The internal clock frequency of the PD67XX is 7/4 of this incoming
signal (Tcp = 40 ns). The examples are for the default values of the Timing registers for Timer Set
0, as follows:
Timing Register Name
(Timer Set 0)
Index
Value
(Default)
Resultant Npres
Resultant Nval
Setup Timing 0
3Ah
01h
1
1
Command Timing 0
3Bh
06h
1
6
Recovery Timing 0
3Ch
03h
1
3
Thus the minimum times for the default values are as follows:
Default minimum Setup time = (S × Tcp) – 10 ns = {2 × 40 ns} – 10 ns = 70 ns
Default minimum Command time = (C × Tcp) – 10 ns = {7 × 40 ns} – 10 ns = 270 ns
Default minimum Recovery time = (R × Tcp) – 10 ns = {4 × 40 ns} – 10 ns = 150 ns
110
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
16.4.5.1
PC Card Socket Timing
Table 31. Memory Read/Write Timing (Word Access)
Symbol
Parameter
MIN
MAX
Units
t1
-CE[2:1], -REG, Address, and Write Data setup to Command
active1
(S × Tcp) – 10
ns
t2
Command pulse width2
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
Address hold and Write Data valid from Command inactive
t3
3
4
t4
-WAIT active from Command active
t5
Command hold from -WAIT inactive
t6
Data valid from -WAIT inactive
t7
Data setup before -OE inactive
t8
Data hold after -OE inactive
(C – 2)Tcp – 10
(2 Tcp) + 10
ns
ns
Tcp + 10
ns
(2 Tcp) + 10
ns
0
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
4. For typical active timing programmed at 280 ns, maximum -WAIT timing is 190 ns after Command active.
Figure 23. Memory Read/Write Timing
-REG, -CE[2:1],
A[25:0]
t1
t3
t2
-OE, -WE
t5
t4
-WAIT
D[15:0]
Write Cycle
t6
t7
t8
D[15:0]
Read Cycle
Datasheet
111
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 32. Word I/O Read/Write Timing
Symbol
Parameter
MIN
MAX
Units
t1
-REG or Address setup to Command active1
(S × Tcp) – 10
ns
t2
Command pulse width2
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
t3
Address hold and Write Data valid from Command inactive
t4
-WAIT active from Command active
3
4
t5
Command hold from -WAIT inactive
tref
Card -IOIS16 delay from valid Address (PC Card specification)
t6
-IOIS16 setup time before Command end
t7
-CE2 delay from -IOIS16 active
5
t6
Data valid from -WAIT inactive
t9
Data setup before -IORD inactive
t10
Data hold after -IORD inactive
(C – 2)Tcp – 10
(2 Tcp) + 10
ns
ns
35
ns
(3 Tcp) + 10
ns
Tcp – 10
ns
Tcp + 10
ns
(2 Tcp) + 10
ns
0
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
4. For typical active timing programmed at 280 ns, maximum -WAIT timing is 190 ns after Command active.
5. -IOIS16 must go low within 3Tcp + 10 ns of the cycle beginning or -IOIS16 will be ignored and -CE will not be activated.
112
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Figure 24. Word I/O Read/Write Timing
-REG,
A[25:0]
t1
t3
t2
-IOWR, -IORD
t5
t4
-WAIT
tref
t6
-IOIS16
-CE1
t7
-CE2
D[15:0]
Write Cycle
t8
t9
t10
D[15:0]
Read Cycle
Table 33. PC Card Read/Write Timing when System Is 8-Bit
Symbol
Parameter
MIN
MAX
Units
t1
-REG or Address setup to Command active1
(S × Tcp) – 10
ns
t2
Command pulse width2
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
(2 Tcp) + 10
ns
0
ns
t3
Address hold from Command inactive
t4
Data setup before Command inactive
t5
Data hold after command inactive
3
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
Datasheet
113
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 25. PC Card Read/Write Timing When System Is 8-Bit (SBHE Tied High)
-REG,
A[25:0]
t1
t3
t2
-OE, -WE
-IOWR, -IORD,
-CE1
D[7:0]
Odd/even Data
Write Cycle
t4
D[7:0]
t5
Odd/Even Data
Read Cycle
D[15:8]
Read or
Write Cycle
XX
Table 34. Normal Byte Read/Write Timing
Symbol
t1
t2
t3
Parameter
Address setup to Command active1
Command pulse width
2
Address hold from Command inactive
3
MIN
MAX
Units
(S × Tcp) – 10
ns
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
114
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Figure 26. Normal Byte Read/Write Timing
-REG,
A[25:0]
t3
t1
t2
IOWR, -IORD,
-OE, -WE
-CE1
-CE2
D[7:0]
Write Cycle
Odd/Even Data
D[7:0]
Read Cycle
Odd/Even Data
D[15:8]
Read or
Write Cycle
XX
NOTE: Figure 26 applies to all other byte accesses, including odd I/O cycles where -IOIS16 is low.
Table 35. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
Symbol
Parameter
t1
Address change to -IOIS16 inactive
t2
-IOIS16 inactive to -CE2 inactive
MIN
4
t3
-IOIS16 inactive to -CE1 active
t4
Address setup to Command active1
t5
Command pulse width2
t6
Address hold from Command inactive
MAX
Units
(3Tcp) + 10
ns
20
ns
20
3
ns
(S × Tcp) – 10
ns
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
4. -IOIS16 level from card should be valid before -IOWR/-IORD goes active. For a typical setup time of 70 ns, a PC Card
meeting the PCMCIA specification for -IOIS16 from A[25:0] change will meet this condition.
Datasheet
115
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 27. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
-REG,
A[25:0]
t1
-IOIS16
t2
-CE2
t3
-CE1
t4
t6
t5
-IOWR, -IORD
D[7:0]
Write Cycle
Odd Data
D[7:0]
Read Cycle
Odd Data
D[15:8]
Read or
Write Cycle
XX
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Units
t1
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
40
ns
t2
-CE[2:1], -REG, -IORD, -OE, and Write Data setup to -IOWR
active1
(S × Tcp) – 10
ns
t3
Command: -IOWR pulse width2
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
t4
Recovery: -IOWR inactive to end of cycle
t5
-WAIT active from -IOWR active
t6
-WAIT inactive to -IOWR inactive
3
(C – 2)Tcp – 10
2 Tcp
ns
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
4. Based on an internal clock period of 40 ns (25 MHz).
116
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 36. DMA Read Cycle Timing (PD6722 only) (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Units
t7
System TC (-VPP_VALID high) to -IOWR
−40
t8
-IOWR to begin of card TC (-WE)4
25
50
ns
t9
End of card TC (-WE) to -IOWR inactive4
25
50
ns
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
4. Based on an internal clock period of 40 ns (25 MHz).
Figure 28. DMA Read Cycle Timing
IRQ10
(DRQ)
IRQ9
(DACK*)
t1
-IORD, -OE
(high)
-REG
(DACK* to card)
-CE[2:1]
t2
t4
t3
-IOWR
t5
t6
-WAIT
DMA DATA[15:0]
to card
t7
-VPP_VALID
(TC from system)
t8
t9
-WE
(TC to card)
Datasheet
117
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 37. DMA Write Cycle Timing (PD6722 only)
Symbol
Parameter
MIN
MAX
Units
t1
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
40
ns
t2
-CE[2:1], -REG, -IOWR, -WE, and Write Data setup to -IORD
active1
(S × Tcp) – 10
ns
t3
Command: -IORD pulse width2
(C × Tcp) – 10
ns
(R × Tcp) – 10
ns
t4
Recovery: -IORD inactive to end of cycle
t5
-WAIT active from -IORD active
t6
-WAIT inactive to -IORD inactive
t7
System TC (-VPP_VALID high) to -IORD
t8
-IORD to begin of card TC (-OE)
3
(C – 2)Tcp – 10
4
4
ns
2 Tcp
ns
−40
ns
25
50
ns
25
50
ns
t9
End of card TC (-OE) to -IORD inactive
t10
Data valid from -WAIT inactive
Tcp + 10
ns
t11
Data setup before -OE inactive
(2 Tcp) +10
ns
t12
Data hold after -OE inactive
0
ns
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (Npres × Nval + 1), see “PC Card Bus Timing Calculations” on
page 109.
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (Npres × Nval + 1), see page 109.
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (Npres × Nval + 1), see page 109.
4. Based on an internal clock period of 40 ns (25 MHz).
118
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Figure 29. DMA Write Cycle Timing
IRQ10
(DRQ)
IRQ9
(DACK*)
t1
-IOWR, -WE
(high)
-REG
(DACK* to card)
-CE[2:1]
t2
t4
t3
-IORD
t6
t5
-WAIT
DMA DATA[15:0]
to card
t7
-VPP_VALID
(TC from system)
t8
t9
-OE
(TC to card)
t10
t11
t12
DMA DATA[15:0]
from card
Table 38. DMA Request Timing (PD6722 only)
Symbol
t1
Parameter
DMA request from socket interface to system
MIN
1
40
MAX
Units
ns
1. After FIFO empty, DMA requests held off from being presented to the system until all write data to a card has been emptied
from the socket interface FIFO.
Datasheet
119
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 30. DMA Request Timing
t1
-INPACK, WP/-IOIS16,
or BVD2/-SPKR 2
(-DREQ from card)
IRQ10
(DRQ to system)
2
120
DMA Control register bits 7 and 6 define which of these three signals serve as the active-low DMA request from the card.
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
17.0
Package Specifications
17.1
144-Pin LQFP Package
21.60 (0.850)
22.40 (0.882)
19.90 (0.783)
20.10 (0.791)
0.10 (0.004)
0.30 (0.012)
19.90 (0.783)
20.10 (0.791)
21.60 (0.850)
22.40 (0.882)
DZPD6710VCB
144-Pin LQFP
17.50
(0.689)
REF
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 144
Pin 1
17.50 (0.689) REF
0.45 (0.018)
0.75 (0.030)
1.25 (0.049)
1.50 (0.059)
0.10 (0.004)
0.20 (0.008)
1.00
(0.039)
REF
0° MIN
7° MAX
1.40 (0.055)
1.65 (0.065)
0.05 (0.002)
0.15 (0.006)
NOTES:
1. Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2. Before beginning any new design with this device, please contact Intel Corp. for the latest package
information.
Datasheet
121
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
17.2
208-Pin MQFP Package
30.35 (1.195)
30.85 (1.215)
27.90 (1.098)
28.10 (1.106)
0.13 (0.005)
0.28 (0.011)
27.90 (1.098)
28.10 (1.106)
SPD6722QCCE
30.35 (1.195)
30.85 (1.215)
25.50
(1.004)
REF
208-Pin MQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
25.50 (1.004) REF
0.40 (0.016)
0.75 (0.030)
3.17 (0.125)
3.67 (0.144)
1.30 (0.051) REF
0.09 (0.004)
0.23 (0.009)
0° MIN
7° MAX
4.07 (0.160) MAX
0.25 (0.010) MIN
NOTES:
1. Dimensions are in millimeters (inches), and controlling dimension is inches.
2. Drawing above does not reflect exact package pin count.
3. Before beginning any new design with this device, please contact Intel Corp. for the latest package
information.
122
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
17.3
208-Pin LQFP Package
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
DZPD6722VCCE
29.60 (1.165)
30.40 (1.197)
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
0.45 (0.018)
0.75 (0.030)
1.35 (0.053)
1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
1.40 (0.055)
1.60 (0.063)
0.05 (0.002)
0.15 (0.006)
NOTES:
1. Dimensions are in millimeters (inches), and controlling dimension is inches.
2. Drawing above does not reflect exact package pin count.
3. Before beginning any new design with this device, please contact Intel Corp. for the latest package
information.
Datasheet
123
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
18.0
Order Numbers Example
The example order numbers for PD67XX devices are as follows:
DZPD6710VCB
Product Line:
Portable Products
Part Number
Revision
Temperature Range:
C = Commercial
Package Type: LQFP
Low-profile quad flat pack
SPD6722QCCE
Product Line:
Portable Products
Part Number
Revision
Temperature Range:
C = Commercial
Package Type: MQFP
Metric quad flat pack
DZPD6722VCCE
Product Line:
Portable Products
Part Number
124
Revision
Temperature Range:
C = Commercial
Package Type: LQFP
Low-profile quad flat pack
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
19.0
Appendix A
19.1
Register Summary Tables
19.1.1
Operation Registers
Register Name: Index
Register Per: chip
Index: n/a
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Device Index
Socket Index
Register Index
RW:0
RW:0
RW:000000
Bit 1
Register Name: Data
Bit 0
Register Per: chip
Index: n/a
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data
19.2
Chip Control Registers
Register Name: Chip Revision
Register Per: chip
Index: 00h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Interface ID
R:10
Bit 3
Bit 2
Bit 1
Bit 0
Revision
R:0
R:0
R:0011
1. Value for the current stepping only.
Datasheet
125
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Register Name: Interface Status
Register Per: socket
Index: 01h
Bit 7
Register Compatibility Type: 365
Bit 6
-VPP_VALID
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY
WP
-CD2
-CD1
BVD2
BVD1
VPP Valid
Card Power
On
Ready/Busy*
Write Protect
Card Detect
Battery Voltage Detect
R1
R:0
R2
R3
R4
R5
1.
2.
3.
4.
5.
Bit 7 is the inversion of the value of the -VPP_VALID pin (see Table 1 on page 16).
Bit 5 is the value of the RDY/-IREQ pin (see Table 2 on page 20).
Bit 4 is the value of the WP/-IOIS16 pin (see Table 2).
Bits 3:2 are the inversion of the values of the -CD1 and -CD2 pins (see Table 2).
Bits 1:0 are the values of the BVD1/-STSCHG and BVD2/-SPKR pins (see Table 2).
Register Name: Power Control
Register Per: socket
Index: 02h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Card Enable
Compatibility
Bit
Auto-Power
VCC Power
Compatibility Bits
VPP1 Power
RW:0
RW:0
RW:0
RW:0
RW:00
RW:00
Register Name: Interrupt and General Control
Register Per: socket
Index: 03h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Ring Indicate
Enable
Card Reset*
Card Is I/O
Enable
Management
Interrupts
Card IRQ Select
RW:0
RW:0
RW:0
RW:0
RW:0000
Bit 3
Bit 2
Bit 1
Register Name: Card Status Change
R:0
126
Bit 0
Register Per: socket
Index: 04h
Bit 7
Bit 0
Register Compatibility Type: 365
Bit 6
R:0
Bit 5
R:0
Bit 4
R:0
Bit 3
Bit 2
Bit 1
Bit 0
Card Detect
Change
Ready
Change
Battery
Warning
Change
Battery Dead
Or Status
Change
R:0
R:0
R:0
R:0
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Register Name: Management Interrupt Configuration
Register Per: socket
Index: 05h
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Management IRQ Select
Card Detect
Enable
Ready
Enable
Battery
Warning
Enable
Battery Dead
Or Status
Change
Enable
RW:0000
RW:0
RW:0
RW:0
RW:0
Register Name: Mapping Enable
Register Per: socket
Index: 06h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Map 1
Enable
I/O Map 0
Enable
MEMCS16
Full Decode
Memory Map
4 Enable
Memory Map
3 Enable
Memory Map
2 Enable
Memory Map
1 Enable
Memory Map
0 Enable
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
19.3
I/O Window Mapping Registers
Register Name: I/O Window Control
Register Per: socket
Index: 07h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timing
Register
Select 1
Compatibility
Bit
Auto-Size I/O
Window 1
I/O Window 1
Size
Timing
Register
Select 0
Compatibility
Bit
Auto-Size I/O
Window 0
I/O Window 0
Size
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Register Name: System I/O Map 0–1 Start Address Low
Register Per: socket
Index: 08h, 0Ch
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 7:0
RW:00000000
Datasheet
127
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Register Name: System I/O Map 0–1 Start Address High
Register Per: socket
Index: 09h, 0Dh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 15:8
RW:00000000
Register Name: System I/O Map 0–1 End Address Low
Register Per: socket
Index: 0Ah, 0Eh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Address 7:0
RW:00000000
Register Name: System I/O Map 0–1 End Address High
Register Per: socket
Index: 0Bh, 0Fh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Address 15:8
RW:00000000
Register Name: Card I/O Map 0–1 Offset Address Low
Register Per: socket
Index: 36h, 38h
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 7:1
01
RW:0000000
RW:0
1. This bit must be programmed to ‘0’.
Register Name: Card I/O Map 0–1 Offset Address High
Register Per: socket
Index: 37h, 39h
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 15:8
RW:00000000
128
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
19.4
Memory Window Mapping Registers
Register Name: System Memory Map 0–4 Start Address Low
Register Per: socket
Index: 10h, 18h, 20h, 28h, 30h
Bit 7
Bit 6
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 19:12
RW:00000000
Register Name: System Memory Map 0–4 Start Address High
Register Per: socket
Index: 11h, 19h, 21h, 29h, 31h
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Window Data
Size
Compatibility
Bit
Scratchpad Bits
Start Address 23:20
RW:0
RW:0
RW:00
RW:0000
Register Name: System Memory Map 0–4 End Address Low
Register Per: socket
Index: 12h, 1Ah, 22h, 2Ah, 32h
Bit 7
Bit 6
Bit 0
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
End Address 19:12
RW:00000000
Register Name: System Memory Map 0–4 End Address High
Register Per: socket
Index: 13h, 1Bh, 23h, 2Bh, 33h
Bit 7
Bit 6
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Card Timer Select
Scratchpad Bits
End Address 23:20
RW:00
RW:00
RW:0000
Register Name: Card Memory Map 0–4 Offset Address Low
Register Per: socket
Index: 14h, 1Ch, 24h, 2Ch, 34h
Bit 7
Bit 6
Bit 0
Register Compatibility Type: 365
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 19:12
RW:00000000
Datasheet
129
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Register Name: Card Memory Map 0–4 Offset Address High
Register Per: socket
Index: 15h, 1Dh, 25h, 2Dh, 35h
Register Compatibility Type: 365
Bit 7
Bit 6
Write Protect
REG Setting
Offset Address 25:20
RW:0
RW:0
RW:000000
19.5
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Extension Registers
Register Name: Misc Control 1
Register Per: socket
Index: 16h
Bit 7
Inpack
Enable
Register Compatibility Type: ext.
Bit 6
Bit 5
Scratchpad Bits
RW:0
RW:00
Bit 4
Speaker
Enable
RW:0
Bit 3
Bit 2
Pulse System
IRQ
Pulse
Management
Interrupt
VCC 3.3V
RW:0
RW:0
RW:0
Bit 1
Bit 0
5 V Detect
(PD6710)
Reserved
(PD6722)
Register Name: FIFO Control
R:X W:0
Register Per: socket
Index: 17h
Bit 7
Bit 0
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Empty Write
FIFO
Scratchpad Bits1
RW
RW:0000000
Bit 2
Bit 1
Bit 0
1. Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
Register Name: Misc Control 2
Register Per: chip
Index: 1Eh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ15 Is RI
Out
DMA System
(PD6722)
Three-State
Bit 7
Drive LED
Enable
5V Core
Suspend
Low-Power
Dynamic
Mode
Bypass
Frequency
Synthesizer
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:1
RW:0
130
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Register Name: Chip Information
Register Per: chip
Index: 1Fh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC Card Controller
Identification
Dual/Single
Socket*
PD67XX Revision Level
Reserved
R:11
R:n1
R:nnnn2
R:n3
1. The value for PD6710 is ’0’, and the value for PD6722 is ’1’.
2. This read-only value depends on the revision level of the PD67XX chip.
3. The value for PD6722 is ‘1’.
Register Name: ATA Control
Register Per: socket
Index: 26h
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A25/CSEL
A24/M/S*
A23/VU
A22
A21
Scratchpad
Bit
Speaker Is
LED Input
ATA Mode
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Register Name: Extended Index (PD6722 only)
Register Per: socket
Index: 2Eh
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Extended Index
RW:00000000
Register Name: Extended Data (PD6722 only)
Register Per: socket
Index: 2Fh
Bit 7
Register Compatibility Type: ext.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Extended Data
Register Name: Data Mask 0 (PD6722 only)
Index: 2Fh
Bit 7
Bit 6
Bit 5
Register Per: socket
Extended Index: 01h
Bit 4
Bit 3
Register Compatibility Type: ext.
Bit 2
Bit 1
Bit 0
Data Mask Select 0
RW:00000000
Datasheet
131
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Register Name: Data Mask 1 (PD6722 only)
Bit 7
Bit 6
Register Per: socket
Extended Index: 02h
Index: 2Fh
Bit 5
Bit 4
Register Compatibility Type: ext.
Bit 3
Bit 2
Bit 1
Bit 0
Data Mask Select 1
RW:00000000
Register Name: Extension Control 1
(PD6722 only)
Register Per: socket
Extended Index: 03h
Register Compatibility Type: ext.
Index: 2Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA Enable
Pull-up
Control
Reserved
LED Activity
Enable
Auto Power
Clear Disable
VCC Power
Lock
RW:00
RW:0
RW:00
RW:0
RW:0
RW:0
Register Name: Maximum DMA
Acknowledge Delay (PD6722 only)
Register Per: socket
Extended Index: 04h
Register Compatibility Type: ext.
Index: 2Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Maximum DMA Acknowledge Delay
RW:00000000
Register Name: External Data (PD6722 only)
Index: 2Fh
Register Per: socket
Extended Index: 0Ah
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3
External Data
2
External Data
1
External Data
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Register Name: External Data (PD6722 only)
Index: 6Fh
Register Per: socket
Extended Index: 0Ah
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3 or
B_VS2 Input
External Data
2 or
B_VS1 Input
External Data
1 or
A_VS2 Input
External Data
0 or
A_VS1 Input
RW:0
RW:0
RW:0
RW:0
R:0
R:0
R:0
R:0
132
Datasheet
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Register Name: Extension Control 2
(PD6722 only)
Register Per: socket
Extended Index: 0Bh
Register Compatibility Type: ext.
Index: 2Fh and 6Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
RW:00
19.6
Bit 1
Bit 0
Timing Registers
Register Name: Setup Timing 0–1
Register Per: socket
Index: 3Ah, 3Dh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Setup Prescalar Select
Setup Multiplier Value
RW:00
RW:000001
Bit 1
Register Name: Command Timing 0–1
Register Per: socket
Index: 3Bh, 3Eh
Bit 7
Bit 0
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Command Prescalar Select
Command Multiplier Value
RW:00
RW:000110/0011111
Bit 1
Bit 0
1. Timing set 0 (index 3Bh) resets to 06h for socket timing equal to standard AT-bus-based cycle times. Timing set 1 (3Eh)
resets to 0Fh for socket timings equal to standard AT-bus timing using one additional wait state.
Register Name: Recovery Timing 0–1
Register Per: socket
Index: 3Ch, 3Fh
Bit 7
Register Compatibility Type: 365
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Recovery Prescalar Select
Recovery Multiplier Value
RW:00
RW:000011
Datasheet
Bit 1
Bit 0
133
Index
Symbols
C
+5V 25
C_SEL 19
Card Detect bits 47
Card Detect Change bit 53
Card Detect Enable bit 55
Card Enable bit 50
Card I/O Map 0–1 Address Offset High registers 62
Card I/O Map 0–1 Address Offset Low registers 62
Card Is I/O bit 52
Card Memory Map 0–4 Offset Address High
registers 68
Card Memory Map 0–4 Offset Address Low
registers 67
Card Power On bit 48
Card Reset* bit 52
Card Status Change register 52
Card Timer Select bits 67
-CD[2:1] 22
-CE[2:1] 22
Chip Information register 74
Chip Revision register 46
CLK 19
Command Multiplier Value bits 86
Command Prescalar Select bits 86
Command Timing 0–1 registers 85
conventions
bit naming 40
numbers and units 11
pin naming 14
register headings 39
Numerics
5V Core bit 73
A
A[25:0] 20
A21 bit 76
A22 bit 76
A23/VU bit 76
A24/M/S* bit 76
A25/CSEL bit 76
Active-high GPSTB bit 83
AEN 17
ALE 17
ATA Control register 75
ATA mode
description 88
overview 36
pin cross reference 88
ATA Mode bit 75
Auto Power Clear Disable bit 78
Auto-Power bit 50
Auto-Size I/O Window 0 bit 58
Auto-Size I/O Window 1 bit 59
B
Battery Dead Or Status Change bit 53
Battery Dead Or Status Change Enable bit 54
Battery Voltage Detect bits 47
Battery Warning Change bit 53
Battery Warning Enable bit 54
bus sizing 35
BVD1/-STSCHG/-RI 23
BVD2/-SPKR/-LED 23
Bypass Frequency Synthesizer bit 73
Datasheet
D
D[15:0] 20
Data Mask 0–1 register 78
Data Mask Select 0–1 bits 78
Data register 44
135
Device Index bit 41
DMA Enable bits 79
DMA mode
description 97
overview 36
DMA Read Cycle timing 116
DMA Request timing 119
DMA System bit 74
DMA Write Cycle timing 118
Drive LED Enable bit 73
Dual/Single Socket* bit 75
E
Empty Write FIFO bit 72
Enable Manage Int bit 51
End Address
19:12 bits 66
23:20 bits 67
7:0 bits 61
Extended Data register 77
Extended Index register 77
Extended Register Index bits 77
Extension Control 2 register 83
External Data bits 81, 82
External Data register 81
F
FIFO Control register 72
form factor 1, ??–123
functional blocks 30
G
general-purpose strobe
control 91
example implementations 93
overview 32
suspend mode 94
General-Purpose Strobe timing 108
GND 25
GPSTB 24
GPSTB on IOR* bit 83
GPSTB on IOW* bit 83
136
H
host access to registers 36
I
I/O Map 0 Enable bit 57
I/O Map 0–1 Start Address High registers 60
I/O Map 1 Enable bit 57
I/O Window 0 Size bit 58
I/O Window 1 Size bit 59
I/O Window Control register 58
IDE 88
Index register 41
-INPACK 21
Inpack Enable bit 71
Input Clock specification 108
Interface ID bits 46
Interface Status register 47
Interrupt and General Control register 51
interrupts 30
-INTR 18
IOCHRDY 17
IOCS16* 17
-IOIS16 21
IOR* 16
-IORD 21
IOW* 16
-IOWR 21
-IREQ 21
IRQ[14, 11, 7, 5:3] 18
IRQ10 18
IRQ10 as DRQ, description 32
IRQ12 as LED_OUT*, description 31
IRQ12/LED_OUT* 18
IRQ15 as RI_OUT*, description 31
IRQ15 Is RI Out bit 74
IRQ15/RI_OUT* 18
IRQ9 18
IRQ9 as DACK*, description 32
ISA bus timing 104
ISA_VCC 19
Datasheet
L
LA[23:17] 16
-LED 23
LED Activity Enable bit 79
LED_OUT* 18
Low-Power Dynamic mode 32
Low-Power Dynamic Mode bit 73
M
Management Interrupt Configuration register
54
Management IRQ Select bits 55
Mapping Enable register 55
MEMCS16 Full Decode bit 56
MEMCS16* 17
Memory Map
0 Enable bit 56
MEMR* 17
MEMW* 17
Misc Control 1 register 70
Misc Control 2 register 72
N
Normal Byte Read/Write timing 114
O
Odd Byte timing 115
-OE 20
ordering information 124
P
package
144-pin VQFP 121
208-pin PQFP 122
208-pin VQFP 123
PC Card
basics 27
bus timing calculations 109
Read/Write timing 113
socket timing 111
timing 36
Datasheet
PCMCIA 27
PD67XX Revision Level bits 75
pin descriptions 12–25
pin diagram
144-pin VQFP 13
208-pin PQFP or VQFP 14
pin usage summary 25
power consumption 34
Power Control register 48
power management 32
power-on
configuration 25
setup 38
Pull-up Control bit 79
Pulse Management Interrupt bit 70
Pulse Mode Interrupt timing 107
Pulse System IRQ bit 71
PWRGOOD 17
R
RDY/-IREQ 21
Ready Change bit 53
Ready Enable bit 54
Ready/Busy* bit 48
Recovery Multiplier Value bits 87
Recovery Prescalar Select bits 87
Recovery Timing 0–1 registers 86
REFRESH* 17
-REG 20
REG Setting bit 68
Register Index bits 41
RESET 22
Reset timing 107
Revision bits 46
-RI 23
RI_OUT* 18
Ring Indicate Enable bit 52
S
SA[16:0] 16
SBHE* 16
SD[15:0] 16
137
Setup Multiplier Value bits 84
Setup Prescalar Select bit 85
Setup Timing 0–1 registers 84
SLOT_VCC. See SOCKET_VCC
socket
accessing specific registers 42
register per 39
Socket Index bit 41
socket power features 34
SOCKET_VCC 23
Speaker Enable bit 71
Speaker Is LED Input bit 76
-SPKR 23
SPKR_OUT*/C_SEL 19
-STSCHG 23
Super-Suspend mode, description 33
Suspend bit 73
Suspend mode, description 32
System Interrupt timing 107
T
Three-State Bit 7 bit 74
timing
DMA Read Cycle 116
DMA request 119
DMA Write Cycle 118
General-Purpose Strobe 108
ISA bus 104
Normal Byte Read/Write 114
Odd Byte 115
PC Card bus 109
PC Card Read/Write 113
PC Card socket 111
Pulse Mode Interrupt 107
138
Reset 107
System Interrupt 107
Word I/O Read/Write 112
Timing Register Select 0 bit 58
Timing Register Select 1 bit 59
Totem-pole GPSTB bit 83
V
VCC 3.3V bit 70
VCC Power bit 50
VCC Power Lock bit 78
-VCC_3 24
-VCC_5 24
voltage sense 95–96
overview 32
VPP Valid bit 48
VPP_PGM 24
-VPP_VALID 19
VPP_VCC 24
VPP1 Power bits 50
W
-WAIT 21
-WE 21
Window Data Size bit 65
windowing 27
Word I/O Read/Write timing 112
WP/-IOIS16 21
write FIFO 35
Write Protect bit 48, 69
Z
ZWS* 18
Datasheet