ML12210
Serial Input PLL
Frequency Synthesizer
Legacy Device: Motorola MC12210
The ML12210 is a 2.5 GHz Bipolar monolithic serial input
phase locked loop (PLL) synthesizer with pulse–swallow function.
It is designed to provide the high frequency local oscillator signal
of an RF transceiver in handheld communication applications.
The technology used allows for low power operation at a minimum supply voltage of 2.7 V. The device is designed for operation
over 2.7 to 5.5 V supply range for input frequencies up to 2.5 GHz
with a typical current drain of 9.5 mA. The low power consumption makes the ML12210 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN
or personal communication services. A dual modulus prescaler is
integrated to provide either a 32/33 or 64/65 divide ratio.
16
1
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B
(SO–16)
• Low Power Supply Current of 8.8 mA Typical for ICC
and 0.7 mA Typical for Ip
• Supply Voltage of 2.7 to 5.5 V
• Dual Modulus Prescaler With Selectable Divide Ratios
of 32/33 or 64/65
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a
Binary 14–Bit Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit
Swallow Counter and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First
Stage of the Loop Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of TA = –40 to 85°C
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
LANSDALE
PACKAGE
SO 16
MC12210D
ML12210-5P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
NOTE: Also available is the ML12202, a 1.1 GHz version of this
function.
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
Power Supply Voltage, Pin 4
VCC
–0.5 to 6.0
Vdc
Power Supply Voltage, Pin 3
Vp
VCC to 6.0
Vdc
Storage Temperature Range
Tstg
–65 to 150
°C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation should be restricted to the Recommended
Operating Conditions.
Page 1 of 11
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Issue A
LANSDALE Semiconductor, Inc.
ML12210
φR
φP
16
15
fOUT BISW
14
13
FC
LE
DATA
CLK
12
11
10
9
Pinout: 16–Lead Package (Top View)
1
2
3
OSCin OSCout VP
4
5
6
7
8
VCC
Do
GND
LD
fIN
PIN NAMES
Pin
16–Lead Pkg
Pin No.
I/O
Function
OSCin
I
Oscillator input. A crystal may be connected between OSCin and OSCout. It is
highly recommended that an external source be ac coupled into this pin (see text).
1
OSCout
O
Oscillator output. Pin should be left open if external source is used
2
VP
–
Power supply for charge pumps (VP should be greater than or equal to VCC) VP
provides power to the Do, BISW and φP outputs
3
VCC
–
Power supply voltage input. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
4
Do
O
Internal charge pump output. Do remains on at all times
5
GND
–
Ground
6
LD
O
Lock detect, phase comparator output
7
fIN
I
Prescaler input. The VCO signal is AC–coupled into this pin
8
CLK
I
Clock input. Rising edge of the clock shifts data into the shift registers
9
DATA
I
Binary serial data input
10
LE
I
Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data
stored in the shift register is transferred into the appropriate latch (depending on
the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
internal charge pump is connected to the BISW pin
11
FC
I
Phase control select (with internal pull up resistor). When FC is LOW, the
characteristics of the phase comparator and charge pump are reversed. FC also
selects fp or fr on the fOUT pin
12
BISW
O
Analog switch output. When LE is HIGH or OPEN ("analog switch is ON") the
output of the second charge pump is connected to the BISW pin. When LE is LOW,
BISW is high impedance
13
fOUT
O
Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable
reference divider output; when FC is LOW, fOUT=fp, programmable divider output
14
φP
O
Output for external charge pump. Standard CMOS output level
15
φR
O
Output for external charge pump. Standard CMOS output level
16
NC
–
No connect
–
Page 2 of 11
www.lansdale.com
20–Lead Pkg
Pin No.
Issue A
LANSDALE Semiconductor, Inc.
ML12210
Figure 1. ML12210 Block Diagram
15–BIT SHIFT REGISTER
15
15–BIT LATCH
14
1
PROGRAMMABLE REFERENCE DIVIDER
OSCin
CRYSTAL
OSCILLATOR
OSCout
fr
14–BIT REFERENCE COUNTER
LD
PHASE/FREQUENCY
DETECTOR
FC
φP
φR
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
LE
LE
CONTROL
BIT
DATA
DATA
18–BIT SHIFT REGISTER
7
CLK
11
7–BIT
LATCH
7
fIN
PRESCALER
32/33 or 64/65
DIVIDER
OUTPUT MUX
11–BIT LATCH
fOUT
11
PROGRAMMABLE DIVIDER
7–BIT
SWALLOW
A–COUNTER
11–BIT
PROGRAMMABLE
N–COUNTER
fp
CONTROL LOGIC
Page 3 of 11
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Issue A
LANSDALE Semiconductor, Inc.
ML12210
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts one bit of serial
data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable
pin is HIGH or OPEN.
Control bit:
“H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect
the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to16383) and
the prescaler divide ratio (SW=0 for ÷64/65, SW=1 for ÷32/33). An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:
SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)
MSB
CONTROL BIT (LAST BIT)
LSB
S
R
R
R
R
R
R
R
R
R
R
R
R
R
R
W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C
SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE
REFERENCE COUNTER (R–COUNTER)
DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER
Divide
Ratio R
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PRESCALER SELECT BIT
Page 4 of 11
Prescaler Divide Ratio P
SW
64/65
0
32/33
1
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML12210
PROGRAMMABLE DIVIDER
19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit shift
register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter divide ratio
(16 to 2047). An N–counter divide ratio less than 16 is prohibited.
For Control bit (C) = LOW:
MSB (FIRST BIT)
CONTROL BIT (LAST BIT)
LSB
N
N
N
N
N
N
N
N
N
N
N
A
A
A
A
A
A
A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SETTING BITS FOR
DIVIDE RATIO OF
PROGRAMMABLE N–COUNTER
C
SETTING BITS FOR
DIVIDE RATIO OF
SWALLOW A–COUNTER
DIVIDE RATIO OF PROGRAMMABLE N–COUNTER
DIVIDE RATIO OF SWALLOW A–COUNTER
Divide
Ratio N
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
Divide
Ratio A
A
7
A
6
A
5
A
4
A
3
A
2
A
1
16
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
17
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
127
1
1
1
1
1
1
1
DIVIDE RATIO SETTING
fvco = [(P • N)+A] • fosc ÷ R with A<N
fvco: Output frequency of external voltage controlled oscillator (VCO)
N:
Preset divide ratio of binary 11–bit programmable counter (16 to 2047)
A:
Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)
fosc: Output frequency of the external frequency oscillator
R:
Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)
P:
Preset mode of dual modulus prescaler (32 or 64)
Figure 2. Serial Data Input Timing
DATA
N18:MSB
N17
N8
A7
A1
C = CONTROL BIT (LAST BIT)
(SW:MSB)
(R14)
(R7)
(R6)
(R1)
(C = CONTROL BIT (LAST BIT))
CLK
LE
ts(C→LE)
ts(D)
th(D)
tCW
tEW
NOTES: Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.
ts(D) = Setup Time DATA to CLK
ts(D) ≥ 10 ns
th(D) = Hold Time DATA to CLK
th(D) ≥ 20 ns
tCW = CLK Pulse Width
tCW ≥ 30 ns
tEW = LE Pulse Width
tEW ≥ 20 ns
ts(C→LE) = Setup Time CLK to LE
ts(C→LE) ≥ 30 ns
Page 5 of 11
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Issue A
LANSDALE Semiconductor, Inc.
ML12210
PHASE CHARACTERISTICS/VCO CHARACTERISTICS
The phase comparator in the ML12210 is a high speed digital phase frequency detector circuit. The circuit determines the “lead” or “lag”
phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input. Since these edges
occur only once per cycle, the detector has a range of ±2π radians. The phase comparator outputs are standard CMOS rail–to–rail levels
(VP to GND for φP and VCC to GND for φR), designed for up to 20MHz operation into a 15pF load. These phase comparator outputs
can be used along with an external charge pump to enhance the PLL characteristics.
The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are controlled by
the FC pin. The polarity of the phase comparator outputs, φR and φP, as well as the charge pump output Do can be reversed by switching
the FC pin.
Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms
H
fr
L
H
fp
L
H
LD
L
Source
Z
Sink
Do (FC = H)
BISW (LE = H or Open)
H
φR (FC = H)
L
H
φP (FC = H)
L
Source
Z
Sink
Do (FC = L)
BISW (LE = H or Open)
H
φR (FC = L)
L
H
φP (FC = L)
L
NOTES: Do and BISW are current outputs.
Phase difference detection range: –2π to +2π
Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
Internal Charge Pump Gain ≈
Page 6 of 11
Isource + Isink
= 4mA
4π
4π
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML12210
For FC = HIGH:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φP output will remain in a HIGH state while the φR output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on φR indicates to the VCO to decrease in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φR output will remain in a LOW state while the φP output
pulses from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on
φP indicates to the VCO to increase in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will maintain the loop in its locked state.
When FC = LOW, the operation of the phase comparator is reversed from the above explanation.
For FC = LOW:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φR output will remain in a LOW state while the φP output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on φP indicates to the VCO to increase in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φP output will remain in a HIGH state while the φR output
pulses from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on
φR indicates to the VCO to decrease in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will maintain the loop in its locked state.
The FC pin controls not only the phase characteristics, but also controls the fOUT test pin. The FC pin permits the user to monitor either
of the phase comparator input signals, fr or fp, at the fOUT output providing a test mode where the programming of the dividers and the
output of the counters can be checked. When FC is HIGH, fOUT = fr, the programmable reference divider output. When FC is LOW,
fOUT = fp, the programmable divider output.
Hence,
If VCO characteristics are like (1), FC should be set HIGH or OPEN.
If VCO characteristics are like (2), FC should be set LOW.
fOUT = fr
fOUT = fp
Figure 4. VCO Characteristics
VCO OUTPUT FREQUENCY
(1)
Figure 5. Phase Comparator, Internal Charge Pump, and
fOUT Characteristics
FC = HIGH or OPEN
(2)
FC = LOW
Do
φR
φP
fOUT
Do
φR
φP
fOUT
fp < fr
H
L
L
fr
L
H
H
fp
fp > fr
L
H
H
fr
H
L
L
fp
fp = fr
Z
L
H
fr
Z
L
H
fp
NOTES: Z = High impedance
When LE is HIGH or Open, BISW has the same
characteristics as Do.
VCO INPUT VOLTAGE
Page 7 of 11
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML12210
Legacy Applications Information
Figure 6. Detailed Phase Comparator Block Diagram
fr
UP
0
φP
R
1
fp
PHASE
FREQUENCY
DETECTOR
0
1
DOWN
φR
V
LD
PHASE COMPARATOR
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
FC
LE
LOCK DETECT
The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally
HIGH. LD is designed to be the logical NORing of the phase frequency detector's outputs UP and DOWN. See Figure 6. In typical
applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9.
OSCILLATOR INPUT
For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be between 500 and
2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal amplitude should be closer to
the upper specification limit. This maximizes the slew rate of the signal as it switches against the internal voltage reference.
The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be connected
between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper crystal load capacitance
and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a maximum of 30 pF each including parasitic and stray capacitance). However, using the on–chip reference oscillator greatly increases the synthesized phase noise.
DUAL INTERNAL CHARGE PUMPS (“ANALOG SWITCH”)
Due to the pure Bipolar nature of the ML12210 design, the “analog switch” function is implemented with dual internal charge pumps.
The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output BISW as shown
in Figure 7 below. This enables the VCO to lock in a shorter amount of time.
When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW pin, and
the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is LOW,
BISW is in a high impedance state and Do output is active.
Figure 7. "Analog Switch" Block Diagram
CHARGE
PUMP 1
CHARGE
PUMP 2
Do
LPF–1
LPF–2
VCO
BISW
LE
Page 8 of 11
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML12210
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V; TA = –40 to +85°C, unless otherwise noted.)
Parameter
Supply Current for VCC
Supply Current for VP
Symbol
Min
Typ
Max
Unit
ICC
–
8.8
13.0
mA
–
10.2
16.0
–
0.7
1.1
–
0.8
1.3
FIN
2500
–
–
–
–
500
MHz
Note 5
FOSC
–
12
20
MHz
Crystal Mode
–
–
40
MHz
External Reference Mode
VIN
200
–
1000
mVpp
VOSC
500
–
2200
mVpp
IP
Operating Frequency
fINmax
fINmin
Operating Frequency (OSCin)
Input Sensitivity
fIN
OSCin
Condition
Note 1
Note 2
mA
Note 3
Note 4
Input HIGH Voltage
CLK, DATA, LE, FC
VIH
0.7 VCC
–
–
V
Input LOW Voltage
CLK, DATA, LE, FC
VIL
–
–
0.3 VCC
V
VCC = 5.5 V
Input HIGH Current (DATA and CLK)
IIH
–
1.0
2.0
µA
VCC = 5.5 V
Input LOW Current (DATA and CLK)
IIL
–10
–5.0
–
µA
VCC = 5.5 V
IOSC
–
–
130
–310
–
–
µA
OSCin = VCC
OSCin = VCC – 2.2 V
Input Current (OSCin)
Input HIGH Current (LE and FC)
IIH
–
1.0
2.0
µA
Input LOW Current (LE and FC)
IIL
–75
–60
–
µA
ISource6
ISink6
–2.6
–2.0
–1.4
mA
+1.4
+2.0
+2.6
IHi–Z
–15
–
+15
nA
0.5< VDO < Vp – 0.5
0.5 < VBISW < Vp – 0.5
VOH
4.4
–
–
V
VCC = 5.0 V
2.4
–
–
V
VCC = 3.0 V
–
–
0.4
V
VCC = 5.0 V
–
–
0.4
V
VCC = 3.0 V
–
–
mA
–
–
mA
Charge Pump Output Current
Do and BISW
Output HIGH Voltage (LD, φR, φP, fOUT)
Output LOW Voltage (LD, φR, φP, fOUT)
VOL
Output HIGH Current (LD, φR, φP, fOUT)
IOH
–1.0
Output LOW Current (LD, φR, φP, fOUT)
IOL
1.0
1. VCC = 3.3 V, all outputs open.
2. VCC = 5.5 V, all outputs open.
3. VP = 3.3 V, all outputs open.
VDo = Vp/2; Vp = 2.7 V
VBISW = Vp/2; Vp = 2.7 V
4. Vp = 6.0 V, all outputs open.
5. AC coupling, FIN measured with a 1000 pF capacitor.
6. Source current flows out of the pin and sink current flows into the pin.
Figure 8. Typical External Charge Pump Circuit
Figure 9. Typical Lock Detect Circuit
Vp
VCC
10 kΩ
φP
12 kΩ
100 kΩ
33 kΩ
EXTERNAL CHARGE
PUMP OUTPUT
φR
LD
12 kΩ
0.01 µF
LOCK DETECT
OUTPUT
10 kΩ
10 kΩ
Page 9 of 11
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Issue A
LANSDALE Semiconductor, Inc.
ML12210
Legacy Applications Information
Figure 10. Typical Applications Example
C1
1
2
φR
OSCin
φP
OSCout
16
15
3
100 pF
6
LOCK DETECT
CIRCUIT
(SEE FIGURE 9)
FOUT
VCC
BISW
0.1 µF
5
LOCK
DETECT
VP
14
0.1 µF
4
100 pF
VCO
CHARGE PUMP SELECTION
(INTERNAL OR EXTERNAL)
C2
VP
VCC
LOW PASS
FILTER
(SEE FIGURE 11)
EXTERNAL
CHARGE PUMP
(SEE FIGURE 8)
7
13
ML12210
Do
FC
GND
LE
LD
DATA
12
11
10
47 kΩ
8
fin
CLK
1000 pF
FROM
CONTROLLER
9
47 kΩ
C1, C2: Dependent on Crystal Oscillator
Figure 11. Typical Loop Filter
BISW
Do OR EXTERNAL
CHARGE PUMP
VCO
R
C
Page 10 of 11
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Issue A
LANSDALE Semiconductor, Inc.
ML12210
OUTLINE DIMENSIONS
SO 16 = -5P
PLASTIC PACKAGE
(ML12210-5P)
CASE 751B–05
(SO–16)
ISSUE J
–A
–
16
9
–B
–
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOW ABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
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described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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