LANSDALE ML145506P

ML145506
PCM Codec–Filter Mono–Circuit
Legacy Device: Motorola MC145506
The ML145506 is a per channel codec–filter PCM mono–circuit. This
device performs the voice digitization and reconstruction, as well as the
band limiting and smoothing required for PCM systems. This device has
HCMOS compatible digital outputs and supplements the Lansdale
ML145502 – ML145505 series of PCM codec–filters. The ML145506 is
functionally similar to the ML145502. It is designed to operate in both
synchronous and asynchronous applications and contain an on–chip precision reference voltage. The ML145506 is offered in a 22–pin package
and has the capability of selecting from three peak overload voltages (2.5
V, 3.15 V, and 3.78 V).
This device maintains compatibility with Motorola’s family of
MC3419/MC33120 SLIC products.
The ML1455xx family of PCM codec–filter mono–circuits utilize
CMOS due to its reliable low–power performance and proven capability
for complex analog/digital VLSI functions.
ML145506 Features
• 22–Pin Package, HCMOS Output Version of ML145502
• Selectable Peak Overload Voltages (2.5 V, 3.15 V, 3.78 V)
• Push–Pull Analog Output with Gain Adjust
• 64 kHz to 4.1 MHz Transmit and/or Receive Data Clock Rate
• Operating Temperature Range TA = –40° to +85° C
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Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
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DEVICE DESCRIPTIONS
A codec–filter is a device which is used for digitizing and
reconstructing the human voice. These devices were developed primarily for the telephone network to facilitate voice
switching and transmission. Once the voice is digitized, it may
be switched by digital switching methods or transmitted long
distance (T1, microwave, satellites, etc.) without degradation.
The name codec is an acronym from “coder” for the A/D used
to digitize voice, and “decoder” for the D/A used for reconstructing voice. A codec is a single device that does both the
A/D and D/A conversions.
To digitize intelligible voice requires a signal to distortion of
about 30 dB for a dynamic range of about 40 dB. This may be
accomplished with a linear 13–bit A/D and D/A, but will far
exceed the required signal to distortion at amplitudes greater
than 40 dB below the peak amplitude. This excess performance is at the expense of data per sample. Two methods of data
reduction are implemented by compressing the 13–bit linear
scheme to companded 8–bit schemes. These companding
schemes follow a segmented or “piecewise–linear” curve formatted as a sign bit, 3 chord bits, and 4 step bits. For a given
chord, all 16 of the steps have the same voltage weighting. As
the voltage of the analog input increases, the 4 step bits increment and carry to the 3 chord bits which increment. With the
chord bits incremented, the step bits double their voltage
weighting. This results in an effective resolution of 6 bits (sign
+ chord + 4 step bits) across a 42 dB dynamic range (7 chords
above 0, by 6 dB per chord). There are two companding
schemes used; Mu–255 Law specifically in North America,
and A–Law specifically in Europe. These companding schemes
are accepted world wide. The tables show the linear quantization levels to PCM words for the two companding schemes.
In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal’s highest frequency component. Voice contains spectral energy above 3 kHz, but its
absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a band-width of
3 kHz. This sampling requires a low–pass filter to limit the
high frequency energy above 3 kHz from distorting the inband
signal. The telephone line is also subject to 50/60 Hz power
line coupling which must be attenuated from the signal by a
high–pass filter before the A/D converter. The D/A process
reconstructs a staircase version of the desired inband signal
which has spectral images of the in-band signal modulated
about the sample frequency and its harmonics. These spectral
images are called aliasing components which need to be atten-
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uated to obtain the desired signal. The low–pass filter used to
attenuate these aliasing components is typically called a reconstruction or smoothing filter.
The ML1455xx series PCM codec–filters have the codec,
both presampling and reconstruction filters, a precision voltage reference on chip, and require no external components.
ML145506
The ML145506 PCM codec–filter is the full–featured
22–pin device. It is intended for use in applications requiring
maximum flexibility. The ML145506 is intended for bit interleaved or byte interleaved applications with data clock frequencies which are nonstandard or time varying. One of the five
standard frequencies (listed in CCI Convert Clock Input section) is applied to the CCI input, and the data clock inputs can
be any frequency between 64 kHz and 4.096 MHz. The Vref
pin allows for use of an external shared reference or selection
of the internal reference. The RxG pin accommodates gain
adjustments for the inverted analog output. All three pins of the
input gain setting operational amplifier are present which provide maximum flexibility for the analog interface.
PIN DESCRIPTIONS
DIGITAL
VLS
Logic Level Select Input and HCMOS Digital Ground
VLS controls the logic levels and digital ground reference
for all digital inputs and the digital output. These devices can
operate with logic levels from full supply (VSS to VDD) or
with TTL logic levels using VLS as digital ground. For
VLS = VDD, all I/O is full supply (VSS to VDD swing) with
CMOS switch points. For VSS < VLS < (VDD – 4 V), all
inputs are TTL compatible with VLS being the digital ground
while TDD outputs HCMOS levels from VLS to VDD. The
pins controlled by VLS are inputs MSI, CCI, TDE, TDC, RCE,
RDC, RDD, PDI, and output TDD.
MSI
Master Synchronization Input
MSI is used for determining the sample rate of the transmit
side and as a time base for selecting the internal prescale
divider for the convert clock input (CCI) pin. The MSI pin
should be tied to an 8 kHz clock which may be a frame sync or
system sync signal. MSI has no relation to transmit or receive
data timing, except for determining the internal transmit strobe
as described under the TDE pin description. MSI should be
derived from the transmit timing in asynchronous applications.
In many applications, MSI can be tied to TDE.
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CCI
Convert Clock Input
CCI is designed to accept five discrete clock frequencies. These
are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 2.56 MHz.
The frequency at this input is compared with MSI and prescale
divided to produce the internal sequencing clock at 128 kHz (or 16
times the sampling rate). The duty cycle of CCI is dictated by the
minimum pulse width except for 128 kHz, which is used directly
for internal sequencing and must have a 40% to 60% duty cycle. In
asynchronous applications, CCI should be derived from transmit
timing.
TDC
Transmit Data Clock Input
TDC can be any frequency from 64 kHz to 4.096 MHz, and is
often tied to CCI if the data rate is equal to one of the five discrete
frequencies. This clock is the shift clock for the transmit shift register and its rising edges produce successive data bits at TDD. TDE
should be derived from this clock.
TDE
Transmit Data Enable Input
TDE serves three major functions. The first TDE rising edge following an MSI rising edge, generates the internal transmit strobe
which initiates an A/D conversion. The internal transmit strobe also
transfers a new PCM data word into the transmit shift register (sign
bit first) ready to be output at TDD. The TDE pin is the
high–impedance control for the transmit digital data (TDD) output.
As long as this pin is high, the TDD output stays low impedance.
This pin also enables the output shift register for clocking out the
8–bit serial PCM word. The logical AND of the TDE pin with the
TDC pin, clocks out a new data bit at TDD. TDE should be held
high for eight consecutive TDC cycles to clock out a complete
PCM word for byte interleaved applications. The transmit shift register feeds back on itself to allow multiple reads of the transmit
data. If the PCM word is clocked out once per frame in a byte interleaved system, the MSI pin function is transparent and may be connected to TDE.
The TDE pin may be cycled during a PCM word for bit interleaved applications. TDE controls both the high–impedance state of
the TDD output and the internal shift clock. TDE must fall before
TDC rises (tsu8) to ensure integrity of the next data bit. There must
be at least two TDC falling edges between the last TDE rising edge
of one frame and the first TDE rising edge of the next frame. MSI
must be available separate from TDE for bit interleaved applications.
TDD
Transmit Digital Data Output
The output levels at this pin are controlled by the VLS pin. For
VLS connected to VDD, the output levels are from VSS to VDD.
For a voltage of VLS between VDD – 4 V and VSS, the output
levels are HCMOS compatible with VLS being the digital ground
supply and VDD being the positive logic supply. The TDD pin is a
three–state output controlled by the TDE pin. The timing of this pin
is controlled by TDC and TDE. The data format (Mu–Law, A–Law,
or sign magnitude) is controlled by the Mu/A pin.
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RDC
Receive Data Clock Input
RDC can be any frequency from 64 kHz to 4.096 MHz. This pin
is often tied to the TDC pin for applications that can use a common
clock for both transmit and receive data transfers.The receive shift
register is controlled by the receive clock enable (RCE) pin to clock
data into the receive digital data (RDD) pin on falling RDC edges.
These three signals can be asynchronous with all other digital pins.
RCE
Receive Clock Enable Input
The rising edge of RCE should identify the sign bit of a receive
PCM word on RDD. The next falling edge of RDC, after a rising
RCE, loads the first bit of the PCM word into the receive register.
The next seven falling edges enter the remainder of the PCM word.
On the ninth rising edge, the receive PCM word is transferred to
the receive buffer register and the A/D sequence is interrupted to
commence the decode process. In asynchronous applications with
an 8 kHz transmit sample rate, the receive sample rate should be
between 7.5 kHz and 8.5 kHz. Two receive PCM words may be
decoded and analog summed each transmit frame to allow on–chip
conferencing. The two PCM words should be clocked in as two single PCM words, a minimum of 31.25 µs apart, with a receive data
clock of 512 kHz or faster.
RDD
Receive Digital Data Input
RDD is the receive digital data input. The timing for this pin is
controlled by RDC and RCE. The data format is determined by the
Mu/A pin.
Mu/A
Mu/A Select
This pin selects the companding law and the data format atTDD
and RDD.
Mu/A = VDD; Mu–255 Companding D3 Data Format with Zero
Code Suppress
Mu/A = VAG; Mu–255 Companding with Sign Magnitude
Data Format
Mu/A = VSS; A–Law Companding with CCITT Data Format
Bit Inversions
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To A–Law —
MSB is unchanged (sign)
Invert odd numbered bits
Ignore zero code suppression
PDI
Power Down Input
The power down input disables the bias circuitry and gates
off all clock inputs. This puts the VAG, Txl, RxO, RxO, and
TDD outputs into a high–impedance state. The power dissipation is reduced to 0.1 mW when PDI is a low logic level.
The circuit operates normally with PDI = VDD or with a logic
high as defined by connection at VLS. TDD will not come out
of high impedance for two MSI cycles after PDI goes high.
ANALOG
VAG
Analog Ground Input/Output Pin
VAG is the analog ground power supply input/output. All
analog signals into and out of the device use this as their
ground reference. Each version of the ML1455xx PCM
codec–filter family can provide its own analog ground supply
internally. The dc voltage of this internal supply is 6% positive of the midway between VDD and VSS. This supply can
sink more than 8 mA but has a current source limited to 400
µA. The output of this supply is internally connected to the
analog ground input of the part. The node where this supply
and the analog ground are connected is brought out to the
VAG pin. In symmetric dual supply systems (±5, ±6, etc.),
VAG may be externally tied to the system analog ground supply. When RxO or RxO drive low–impedance loads tied to
VAG, a pull–up resistor to VDD will be required to boost the
source current capability if VAG is not tied to the supply
ground. All analog signals for the part are referenced to VAG,
including noise; therefore, decoupling capacitors (0.1 µF)
should be used from VDD to VAG and VSS to VAG.
Vref
Positive Voltage Reference Input
The Vref pin allows an external reference voltage to be used
for the A/D and D/A conversions. If Vref is tied to VSS, the
internal reference is selected. If Vref > VAG, then the external
mode is selected and the voltage applied to Vref is used for
generating the internal converter reference voltage. In either
internal or external reference mode, the actual voltage used
for conversion is multiplied by the ratio selected by the RSI
pin. The RSI pin circuitry is explained under its pin description below. Both the internal and external references are
inverted within the PCM codec–filter for negative input voltages such that only one reference is required.
External Mode — In the external reference mode (Vref
>VAG), a 2.5 V reference like the MC1403 may be connected
from Vref to VAG. A single external reference may be shared
by tying together a number of Vref pins and VAG pins from
different codec–filters. In special applications, the external
reference voltage may be between 0.5 and 5 V. However, the
reference voltage gain selection circuitry associated with RSI
must be considered to arrive at the desired codec–filter gain.
Internal Mode — In the internal reference mode (Vref
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=VSS), an internal 2.5 V reference supplies the reference voltage for the RSI circuitry.
RSI
Reference Select Input
The RSI input allows the selection of three different overload or full–scale A/D and D/A converter reference voltages
independent of the internal or external reference mode. The
RSI pin is a digital input that senses three different logic
states: VSS, VAG, and VDD. For RSI = VAG, the reference
voltage is used directly for the converters. The internal reference is 2.5 V. For RSI = VSS, the reference voltage is multiplied by the ratio of 1.26, which results in an internal converter reference of 3.15 V. For RSI = VDD, the reference voltage
is multiplied by 1.51, which results in an internal converter
reference of 3.78 V. The device requires a minimum of 1.0 V
of headroom between the internal converter reference to VDD.
VSS has this same absolute valued minimum, also measured
from the VAG pin. The various modes of operation are summarized in Table 2.
RxO, RxO
Receive Analog Outputs
These two complimentary outputs are generated from the
output of the receive filter. They are equal in magnitude and
out of phase. The maximum signal output of each is equal to
the maximum peak–to–peak signal described with the reference. If a 3.15 V reference is used with RSI tied to VAG and a
3 dBm0 sine wave is decoded, the RxO output will be a 6.3 V
peak–to–peak signal. RxO will also have an inverted signal
output of 6.3 V peak–to–peak. External loads may be connected from RxO to RxO for a 6 dB push–pull signal gain or
from either RxO or RxO to VAG. With a 3.15 V reference,
each output will drive 600 Ω to 9 dBm. With RSI tied to
VDD, each output will drive 900 Ω to 9 dBm.
RxG
Receive Output Gain Adjust
The purpose of the RxG pin is to allow external gain adjustment for the RxO pin. If RxG is left open, then the output signal at RxO will be inverted and output at RxO. Thus, the
push–pull gain to a load from RxO to RxO is two times the
output level at RxO. If external resistors are applied from
RxO to RxG (RI) and from RxG to RxO (RG), the gain of
RxO can be set differently from inverting unity. These resistors should be in the range of 10 kΩ. The RxO output level is
unchanged by the resistors and the RxO gain is approximately
equal to minus RG/RI. The actual gain is determined by taking into account the internal resistors which will be in parallel
to these external resistors. The internal resistors have a large
tolerance, but they match each other very closely. This matching tends to minimize the effects of their tolerance on external
gain configurations. The circuit for RxG and RxO is shown in
the Block Diagram.
Txl
Transmit Analog Input
TxI is the input to the transmit filter. It is also the output of
the transmit gain amplifier. The TxI input has an internal gain
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of 1.0, such that a 3 dBm0 signal at TxI corresponds to the peak
converter reference voltage as described in the Vref and RSI pin
descriptions. For a 3.15 V reference, the 3 dBm0 input should be 6.3
V peak–to–peak.
+Tx/ –Tx
Positive Tx Amplifier Input
Negative Tx Amplifier Input
The Txl pin is the input to the transmit band–pass filter. If +Tx or
–Tx is available, then there is an internal amplifier preceding the filter whose pins are +Tx, –Tx, and TxI. These pins allow access to the
amplifier terminals to tailor the input gain with external resistors.
The resistors should be in the range of 10 kΩ.
POWER SUPPLIES
VDD
Most Positive Power Supply
VDD is typically 5 V to 12 V.
VSS
Most Negative Power Supply
VSS is typically 10 V to 12 V negative of VDD. For a ±5 V
dual–supply system, the typical power supply configuration is
VDD = 5 V, VSS = –5 V, VLS = 0 V (digital ground accommodat-
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ing TTL logic levels), and VAG = 0 V being tied to system analog
ground.
For single–supply applications, typical power supply configurations include:
VDD = 10 V to 12 V
VSS = 0 V
VAG generates a mid supply voltage for referencing all analog
signals.
VLS controls the logic levels. This pin should be connected to
VDD for CMOS logic levels from VSS to VDD. This pin should be
connected to digital ground for true TTL logic input levels referenced to VLS, with HCMOS output levels from VLS to VDD.
TESTING CONSIDERATIONS
An analog test mode is activated by connecting MSI and CCI to
128 kHz. In this mode, the input of the A/D (the output of the Tx
filter) is available at the PDI pin. This input is direct coupled to the
A/D side of the codec. The A/D is a differential design. This results
in the gain of this input being effectively attenuated by half. If monitored with a high–impedance buffer, the output of the Tx low–pass
filter can also be measured at the PDI pin. This test mode allows
independent evaluation of the transmit low–pass filter and A/D side
of the codec. The transmit and receive channels of these devices are
tested with the codec–filter fully functional.
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OUTLINE DIMENSIONS
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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