DA9316.003 March 23, 2005 MAS9316 16-BIT DAC · +/- 0.006% DNL and INL · No Laser Trimming · Fast Interface Timing DESCRIPTION The MAS9316 is a 16-bit, monolithic CMOS, multiplying digital-to-analog converter (DAC ) designed for direct microprocessor interface. Its high relative accuracy and monotonicity is achieved without laser trimming. This is made possible by the use of highly accurate, low TCR thin film resistor process and a 4 MSB to 15 decoding design technique. Hidden errors are eliminated by testing all the 65536 different input codes.The device offers advantages like high stability over time and temperature and low sensitivity to output amplifier offset combined to excellent performance-to-cost ratio. The fast input data latches are designed as two 8-bit segments providing data storage when latched or transparent operation when unlatched. All digital inputs have high ESD protection up to 2 kV. FEATURES APPLICATION · Linearity TC 0.5 ppm/C · 2 kV ESD Protection on Digital Inputs · D4 MSB's Decoded · All 65536 Codes Tested · Monolithic CMOS Replacement for SIPEX · DAC 9331-16-4 and SP9316C-4 · 24-pin PDIP Package · Audio applications · Instrumentation · uP Controlled systems BLOCK DIAGRAM VDD BIT1/ MSB . .. BIT16/ LSB VREF RFB 8-BIT INPUT REG. 16-BIT DAC IO1 8-BIT INPUT REG. LBE HBE DGND IO2 1 DA9316.003 March 23, 2005 PIN CONFIGURATION PDIP 24 MAS9316N BIT12 1 BIT11 2 BIT10 3 BIT9 4 BIT8 5 BIT7 6 BIT6 7 BIT5 8 BIT4 9 BIT3 10 BIT2 11 BIT1/MSB 12 24 23 22 21 20 19 18 17 16 15 14 13 BIT13 BIT14 BIT15 BIT16/LSB HBE LBE DGND VDD IO1 IO2 RFB VREF PIN DESCRIPTION Pin name PDIP I/O Function BIT 12 1 I Data bit 12, MSB BIT 11 2 I Data bit 11 BIT 10 3 I Data bit 10 BIT 9 4 I Data bit 9 BIT 8 5 I Data bit 8 BIT 7 6 I Data bit 7 BIT 6 7 I Data bit 6 BIT 5 8 I Data bit 5 BIT 4 9 I Data bit 4 BIT 3 10 I Data bit 3 BIT 2 11 I Data bit 2 BIT 1 12 I Data bit 1 VREF 13 I Reference voltageiInput RFB 14 I Feedback resistor IO2 15 O Current output IO1 16 O Current output VDD 17 P Positive Supply voltage DGND 18 G Digital ground LBE 19 I Low byte enable HBE 20 I High byte enable BIT 16 21 I Data bit 16, LSB BIT 15 22 I Data bit 15 BIT 14 23 I Data bit 14 2 DA9316.003 March 23, 2005 PIN DESCRIPTION Pin name PDIP I/O BIT 13 24 I Function Data bit 13 ABSOLUTE MAXIMUM RATINGS o (Ta = 25 C unless otherwise noted) Parameter Min Max Unit -0.3 +17 V Vref or RFB to DGND -25 +25 V Output Voltage (Pin 15, 16) -0.3 VDD+0.3 V 459 mW 6 mW/ oC Supply Voltage Power Dissipation Symbol Conditions VDD Any package at 75oC PD Derates above 75oC by Die Junction Temperature Storage Temperature o C +150 o C Ts CAUTION: 1.Do not apply voltages higher than VDD or less than GND potential on any terminal other than VREF or RFB. 2.The digital inputs are diode clamp protected against ESD damage. However, permanent damage may occur on unprotected units from high-energy electrostatic fields. Use proper anti-static handling procedures. 3.Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. RECOMMEDED OPERATION CONDITIONS (conditions) Parameter Symbol Conditions Min Typ Max Unit +5 +15 +16 V Supply Voltage VDD Supply Current IDD All digital inputs VIL or VIH 2.0 4.0 mA Supply Current IDD All digital inputs 0V or 5V 0.2 1.0 mA Power Dissipation Pd 60 mW Storage Temperature Ts 0 o C +70 3 DA9316.003 March 23, 2005 ELECTRICAL CHARACTERISTICS Static Performance (test conditions Ta=+25C) Parameter Symbol Resolution N Integral Nonlinearity1 INL Differential Nonlinearity2 DNL Gain error Gfse Output Leakage Current at IO1 (pin 16) Iilk Conditions Min Typ Max Unit s 16 Relative accuracy 13 bits Monotonic to 14 bits Measured Using Internal Rfb DAC Register Loaded With All 1s Bits ±0.004 ±0.006 % ±0.003 ±0.006 % ±0.1 ±0.2 % 10 nA ±0.0005 % Offset Error Temperature Stability (test conditions Ta=+25C) Parameter Symbol Gain error Conditions Min Typ Max Unit s TCTCGFSE ±1.0 ±2.0 pm/C Integral Nonlinearity TC TCINL ±0.1 ±0.5 pm/C Differential Nonlinearity TC TCDNL ±0.1 ±0.5 pm/C Reference Input (test conditions Ta=+25C) Parameter Input Resistance Symbol Conditions Rref Min Typ Max Unit s 2.5 5 7.5 kΩ ±25 v Voltage Range3 Switching Characteristics (test conditions Ta=+25C) Parameter Symbol Conditions Min Typ Max Unit s Strobe Width tSW HBE and LBE Inputs 80 60 ns Data Setup Time tDS Bit 1 to Bit 16 80 70 ns Data Hold Time tDH Bit 1 to Bit 16 40 20 ns NOTES: 1. Integral Nonlinearity is measured as the arithmetic mean value of magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value of any given input combination. 2. Differential Nonlinearity DNL is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 3.Guaranteed by design but not production tested. 4.Logic inputs are MOS gates. Iin typical is less than 1 nA at 25C. 4 DA9316.003 March 23, 2005 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance only and are subject to sample testing only. VDD=+15V, VREF=10V, IO1=IO2=DGND=0V except where stated. Output Amp is HOS-050. (test conditions Ta=+25C) Parameter Symbol Conditions Propagation Delay tPD IO1 load R=100Ω, Cext=13pF All Data Inputs 0V to VDD or VDD to 0V From 50% digital input change to 90% of final analog output. 300 ns CURRENT SETTLING Major Code Transition ts TIMESettling to +0.01% FSR (strobed). 0111111111111111 to 1000000000000000 or 1000000000000000 to 0111111111111111 All Data Inputs 0V to VDD or VDD to 0V 1.5 µS 3.0 µs Digital inputs VIH Digital inputs VIH Digital inputs VIL Digital inputs VIL 170 30 80 100 pF pF pF pF Full Scale Transition Min Typ Max Units OUTPUT CAPACITANCE CIO1 (Pin 16)170 CIO2 (Pin 15) CIO1 (Pin 16) CIO2 (Pin 15) Co Digital to Analog Glitch Energy Q VREF =0V DAC register alternately loaded with all 0s and all 1s 250 nVs Multiplying Feedthrough Error at IO1 FT VREF=20Vpp; f=10kHz sine wave VREF=20Vpp, f=1kHz sine wave 3.0 0.3 mVpp mVpp Power Supply Rejection Ratio PSRR VDD = 14 to 16V ±0.0001 ±0.002 %/% TIMING DIAGRAM DATA t1 LAT CH t1 t2 t2 O UTPU T t3 t1 = Data Setup Tim e (8 0ns) t2 = Stro be W idth (80ns) t3 = Se ttling Tim e (2us typical) 5 DA9316.003 March 23, 2005 APPLICATION INFORMATION VDD VREF VDD VREF 2R Bit 1 (MSB) Bit 1 (MSB) RFB MAS 9316 RFB MAS 9316 R for +/- 5V 2R for +/- 10V Digital Input Digital Input ROS Bit 16 (LSB) IO1 - IO2 + ROS1 IO1 VOUT IO2 Bit 16 (LSB) MSB Latch ROS2 Rb + - VO1 VOUT + MSB Latch DGND LSB Latch DGND LSB Latch UNIPOLAR OPERATION, Transfer Characteristics BIPOLAR OPERATION Transfer Characteristics BINARY INPUT ANALOG OUTPUT OFFSET BINARY INPUT ANALOG OUTPUT 111...111 100...001 100...000 011...111 000...001 000...000 -VREF (1-2-N) -VREF (1/2-2-N) -VREF 1/2 -VREF (1/2-2-N) -VREF (2-N) 0 111...111 100...001 100...000 011...111 000...001 000...000 -VREF (1-2-(N-1)) -VREF (2--(N-1)) 0 +VREF (2(N-1)) -VREF (1-2-(N-1)) +VREF Note: To maintain specified linearity, the external amplifier (A) must be nulled. Apply an ‘all zeroes’ digital input and adjust ROS for VOUT = 0 +/- 1mv. Note: To maintain specified linearity, the external amplifier (A1 and A2) must be nulled. With a digital input of 10...0 and VREF set to zero: a) set ROS1 for VO1 =0, b) set ROS2 for VOUT = 0 c) set VREF to +10v and adjust Rb for VOUT to be 0 volts. DIGITALLY CONTROLLED LOW PASS FILTER Bits 9-16 R3 +5v R2 19 Register MAS9316 5k R1 VIN A1 + 13 C 14 16 16-Bit Register Network 15 A2 + R4 A3 + VOUT +5v 20 Register Bits 1-8 6 DA9316.003 March 23, 2005 PACKAGE OUTLINES 24 LEAD PDIP OUTLINE (600 MIL BODY) 3.18 4.95 5.6 5-7° 15.24 BSC 0.254 2.54 BSC 0.36 0.56 6.35 MAX 29.3 32.7 1.78 12.32 14.73 SEATING PLANE 0.77 1.77 1 PIN ALL MEASUREMENTS IN mm 7 DA9316.003 March 23, 2005 ORDERING INFORMATION Product Code Product Package MAS9316N 16-bit DAC 24 Pin PDIP MAS9316A1ND08 16-bit DAC 24 Pin PDIP Comments Pb free, RoHS compliant LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification 8