MP7636A 15 V CMOS Microprocessor Compatible Double-Buffered, Multiplying 16-Bit Digital-to-Analog Converter FEATURES BENEFITS • • • • • • • • • • High Accuracy Performance at Low Cost • Easy Interface with 8-Bit Microprocessors • Simple Upgrade of MP1230A Family to High Accuracy (Pin Compatible) • Reduced Board Space • 16-Bit Bus Version: MP7626 Four Quadrant Multiplication 16-Bit Monotonicity Lower Data Bus Feedthrough @ CS = 1 Low Feedthrough Error Low Power Consumption TTL/5 V CMOS Compatible Double Buffered Decoded DAC Approach Latch-Up Free pin-for-pin compatibility allows existing systems to be upgraded to 16 bits without hardware modification. GENERAL DESCRIPTION The MP7636A is manufactured using advanced thin film resistors on a double metal CMOS process. The MP7636A incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 16-bit differential non-linearity is achieved with minimal laser trim. The MP7636A provides 16-bit data loading through 8 input data lines for direct interface to 8-bit data buses. All data loading and data transfer operations are identical to the WRITE cycle of a static RAM. The MP7636A uses a unique circuit which significantly reduces transients in the supplies during DATA bus transitions at CS = 1. The MP7636A is packaged in a 20-pin 300 mil wide DIP and is a direct 16-bit replacement for the 12-bit DAC1230 series. Full SIMPLIFIED BLOCK DIAGRAM DB15 (MSB) (DB7) DB14 (DB6) DB13 (DB5) DB12 (DB4) DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0, LSB) 8-Bit Input Latch 16-Bit Register LE When LE = 1 latch outputs follow inputs When LE = 0 Latch outputs are latched RFB 16-Bit MDAC IOUT1 IOUT2 8-Bit Input Latch BYTE1/BYTE2 CS WR1 XFER WR2 LE VDD Rev. 2.00 1 VREF DGND AGND MP7636A ORDERING INFORMATION Package Type Temperature Range SOIC –40 to +85°C SOIC –40 to +85°C INL (LSB) DNL (LSB) MP7636AJS +4 +4 0.1 MP7636AKS +2 +2 0.1 Part No. Gain Error (% FSR) *Contact factory for non-compliant military processing PIN CONFIGURATION See Packaging Section for Package Dimensions CS WR1 AGND DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0, LSB) VREF RFB DGND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VDD BYTE1/BYTE2 WR2 XFER DB12 (DB4) DB13 (DB5) DB14 (DB6) DB15 (MSB) (DB7) IOUT2 IOUT1 20 Pin SOIC (Jedec, 0. 300”) S20 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 CS Chip Select (Active Low) 12 IOUT2 Current Output 2 2 WR1 Write1 (Active Low) 13 3 AGND Analog Ground DB15 (MSB) (DB7) Data Input Bit 15 (Most Significant Bit) Data Input Bit 7 4 DB11 (DB3) Data Input Bit 11 (MSB) Data Input Bit 3 14 DB14 (DB6) Data Input Bit 14 Data Input Bit 6 5 DB10 (DB2) Data Input Bit 10 Data Input Bit 2 15 DB13 (DB5) Data Input Bit 13 Data Input Bit 5 6 DB9 (DB1) Data Input Bit 9 Data Input Bit 1 16 DB12 (DB4) Data Input Bit 12 Data Input Bit 4 7 DB8 (DB0) Data Input Bit 8 Data Input Bit 0 (LSB) 17 XFER Transfer Control Signal (Active Low) 18 WR2 Write 2 (Active Low) 19 BYTE1/ BYTE2 Byte Sequence Control 20 VDD Power Supply 8 VREF Reference Input Voltage 9 RFB Internal Feedback Resistor 10 DGND Digital Ground 11 IOUT1 Current Output 1 Rev. 2.00 2 MP7636A ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, S K, L, T Differential Non-Linearity J, S K, T L Gain Error FSR = Full Scale Range N 16 16 Bits INL Best Fit Straight Line Spec. (Max INL – Min INL) / 2 LSB All grades guaranteed monotonic over full operating temperature range. +4 +2 +4 +2 +1 +4 +2 +2 +0.1 +0.1 % FSR Using Internal RFB +2 ppm/°C ∆Gain/∆Temperature ppm/% |∆Gain/∆VDD| ∆VDD = + 5% nA IOUT1 only To 1/2 LSB RL=100Ω, CEXT=13pF VREF = 20 V p-p Sine wave @ 10kHz DNL GE LSB +4 +2 Gain Temperature Coefficient2 TCGE Power Supply Rejection Ratio PSRR +50 +50 IOUT +10 +200 Output Leakage Current Test Conditions/Comments DYNAMIC PERFORMANCE2 Current Settling Time tS 2 µs AC Feedthrough at IOUT1 FT 2 mV p-p REFERENCE INPUT Input Resistance RIN 2.5 VINH VINL ILKG 3.0 7.5 2.5 7.5 kΩ 0.8 +1 V V µA LOGIC INPUTS3 Input High Voltage Input Low Voltage Input Current Input Capacitance Data Control CIN CIN 2.4 3.0 0.8 +1 5 5 pF pF ANALOG OUTPUTS2 Output Capacitance COUT1 COUT1 COUT2 COUT2 280 120 100 240 Rev. 2.00 3 pF pF pF pF DAC all 1’s DAC all 0’s DAC all 1’s DAC all 0’s MP7636A ELECTRICAL CHARACTERISTICS (CONT’D) Parameter 25°C Typ Max Tmin to Tmax Min Max Symbol Min Units VDD IDD 4.5 CS to WR Set-Up Time tCS 150 ns CS to WR Hold Time Data Valid to WR Set-Up Time Data Valid to WR Hold Time WR, XFER Pulse Width tCH tDS tDH tW 10 70 70 150 ns ns ns ns Test Conditions/Comments POWER SUPPLY5 Functional Voltage Range2 Supply Current 16.5 1 5.0 16.5 1 V mA All digital inputs 0 V or VDD SWITCHING CHARACTERISTICS2, 4 NOTES: (1) (2) (3) (4) (5) Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Storage Temperature Range . . . . . . . . . . . . –65°C to 150°C Package Power Dissipation Rating to 75°C SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . . . 12mW/°C Voltage at Any Digital Input . . . . . GND –0.5 to VDD +0.5 V Voltage at VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V DC Voltage Applied to IOUT1 or IOUT2 GND –0.5 V to +17 V Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . +17 VDC NOTES: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 GND refers to AGND and DGND. 1 APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 4 MP7636A TIMING DIAGRAM tCS VIH tCH 50% CS, BYTE1/BYTE2 50% VIL tW VIH 50% WR VIL VIH DATA BITS 50% tDS tDH 50% 50% VIL tS IOUT1, IOUT2 SETTLED TO +0.01% DEFINITION OF CONTROL SIGNALS: CS: Chip Select (Active low). It will enable WR1. WR1: Write 1 (Active low) The WR1 is used to load the digital data bits (DB) into the input latch. BYTE1/BYTE2: Byte sequence control. The BYTE1/BYTE2 control pin is used to select MSB and LSB both input latches. WR2: Write 2 (Active low). It will enable XFER. XFER: Transfer control signal (Active low). This signal, in combination with WR2, causes the 16-bit data which is available in the input latches to transfer to the DAC register. IOUT2: DAC Current Output 2 Bus. IOUT2 is a complement of IOUT1. The ladder termination has been tied to IOUT2 internally. RFB: Feedback Resistor. This internal feedback resistor should always be used (not an external resistor) since it matches the resistors in the DAC and tracks these resistor over temperature. VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal DAC. The VREF can be selected over the range of +25V to –25V or the analog signal for a 4-quadrant multiplying mode application. VDD: Power Supply Voltage. This is the power supply pin for the part. The VDD can be from +5 V DC to +15 V DC, however optimum voltage is +15 V DC. DB0 to DB15: Digital Inputs. DB0 is the least significant digital input (LSB) and DB15 is the most significant digital input (MSB). AGND: Analog Ground. Back gate of the DAC N-channel current steering switches. IOUT1: DGND: Digital Ground . DAC Current Output 1 Bus. IOUT1 is a maximum for a digital code of all 1’s in the DAC register, and is zero for all 0’s in the DAC register. The timing diagrams for updating the DAC register are shown in Figures 1 and 2. Rev. 2.00 5 MP7636A DATA BUS Valid Valid CS BYTE1/BYTE2 WR1 XFER + WR2 Analog Output Updated Load 8-bit (MSB) Input Latch 8-bit (LSB) Input Latch also changed Overwrite 8-bit (LSB) Input Latch Analog Output Latched Transfer 16-bit word to the DAC Register (Analog Output Updated) and Latched Figure 1. Typical Interface with an 8-bit Data Bus DATA BUS Valid Valid CS BYTE1/BYTE2 + XFER WR1 + WR2 Analog Output Updated Load 8-bit (MSB) Input Latch 8-bit (LSB) Input Latch also changed Overwrite the 8-bit (LSB) Input Latch and Transfer all 16 bits word to the DAC Register Figure 2. Automatic Transfer Rev. 2.00 6 Analog Output Latched MP7636A 20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20 D 20 11 E H 10 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 7 MP7636A LSB PERFORMANCE CHARACTERISTICS Graph 1. Relative Accuracy vs. Digital Code NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 8