MP7614 15 V CMOS Multiplying 14-Bit Digital-to-Analog Converter FEATURES • • • • • Low Sensitivity to Output Amplifier VOS • Low Glitch Energy • 16-Bit Version: MP7616 Full Four-Quadrant Multiplication Excellent Stability Over Temperature and Time Guaranteed Monotonic TTL/5 V CMOS Compatible rather than the standard binary-weighted sources. Each resistor contributes only 1/16 full scale output thus reducing the matching accuracy requirement of the resistor and CMOS switches from 0.0015% to 0.006%. GENERAL DESCRIPTION The MP7614 is a high density 14-bit CMOS multiplying Digital-to-Analog Converter. Silicon nitride passivation and untrimmed silicon chromium resistors have been combined to provide long term stability and reliability. Using the most significant bit (MSB) segmentation technique, the MP7614 features 13-bit (0.012%) differential and 12-bit (0.01%) integral linearity. The decoding technique achieves an eightfold improvement in differential linearity stability over temperature, an eightfold improvement in relative accuracy due to aging effects (long term stability), a fourfold improvement in glitch amplitude, and a tenfold reduction in sensitivity to output amplifier offset voltage. To achieve 13-bit linearity without laser trim, the MP7614 digitally decodes the four MSB’s into 15 equal current sources, SIMPLIFIED BLOCK DIAGRAM VDD VREF R R R R R R R R R R R R R R R 10-Bit DAC IOUT2 IOUT1 RFB To Switches To 10-Bit DAC 4 to 15 Decoder GND 1 (MSB) 4 5 14 (LSB) Rev. 2.00 1 MP7614 ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (% FSR) Plastic Dip –40 to +85°C MP7614JN +4 +4 +0.8 Plastic Dip –40 to +85°C MP7614KN +2 +2 +0.8 SOIC –40 to +85°C MP7614KS +2 +2 +0.8 Ceramic Dip –40 to +85°C MP7614KD +2 +2 +0.8 Ceramic Dip –55 to +125°C MP7614TD* +2 +2 +0.8 *Contact factory for non-compliant military processing PIN CONFIGURATIONS IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 See Packaging Section for Package Dimensions 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 RFB VREF VDD BIT 14 (LSB) BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 20 Pin CDIP, PDIP (0.300”) D20, N20 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 RFB VREF VDD BIT 14 (LSB) BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 20 Pin SOIC (Jedec, 0.300”) S20 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 IOUT1 Current Output 1 11 BIT 8 Data Input Bit 8 2 IOUT2 Current Output 2 12 BIT 9 Data Input Bit 9 3 GND Ground 13 BIT 10 Data Input Bit 10 4 BIT 1 Data Input Bit 1 (MSB) 14 BIT 11 Data Input Bit 11 5 BIT 2 Data Input Bit 2 15 BIT 12 Data Input Bit 12 6 BIT 3 Data Input Bit 3 16 BIT 13 Data Input Bit 13 7 BIT 4 Data Input Bit 4 17 BIT 14 Data Input Bit 14 (LSB) 8 BIT 5 Data Input Bit 5 18 VDD Positive Power Supply 9 BIT 6 Data Input Bit 6 19 VREF Reference Input Voltage 10 BIT 7 Data Input Bit 7 20 RFB Internal Feedback Resistor Rev. 2.00 2 MP7614 ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity5 (Relative Accuracy) J, S K, T Differential Non-Linearity5 J, S K, T Test Conditions/Comments FSR = Full Scale Range N 14 14 Bits INL LSB +4 +2 +4 +2 +4 +2 +4 +2 DNL Best Fit Straight Line Spec. (Max INL – Min INL) / 2 LSB GE 0.8 +0.8 % FSR Using Internal RFB Coefficient2 Gain Temperature Non-Linearity Tempco2 Differential Linearity Tempco2 TCGE +1.0 +0.2 +0.2 +2.0 +0.5 +0.5 ppm/°C ppm/°C ppm/°C ∆Gain/∆Temperature Power Supply Rejection Ratio PSRR +5 +50 +50 ppm/% |∆Gain/∆VDD| ∆VDD = + 5% IOUT +1 +10 +200 Current Settling Time tS 2 Feedthrough at IOUT1 FT 1 2 10 Gain Error Output Leakage Current6 nA DYNAMIC PERFORMANCE2 µs mV p-p To 0.01% of FSR; all digital inputs low to high and high to low VREF = 20 V p-p @ 10 kHz REFERENCE INPUT Input Resistance RIN 1 3 VIH VIL 3.0 2.4 1 10 kΩ 0.8 +1.0 V V µA DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current 3.0 0.8 +1.0 ILKG ANALOG OUTPUTS2 Output Capacitance 100 50 50 100 COUT1 COUT1 COUT2 COUT2 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s V mA All digital inputs = 0 V or all = 5 V POWER SUPPLY4 Functional Voltage Range2 Supply Current VDD IDD 4.5 15 0.4 16 4 Rev. 2.00 3 4.5 16 4 MP7614 ELECTRICAL CHARACTERISTICS (CONT’D) NOTES: 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 Specified values guarantee functionality. Refer to other parameters for accuracy. 5 Linearity error is degraded by 65µV for every mV of voltage offset at output amplifier. 6 Output leakage current refers to IOUT1. 1 LSB of current constantly flows into IOUT2 (30nA at 5 kΩ input impedance, VREF = +10 V) due to ladder termination into IOUT2. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 12mW/°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V Digital Input Voltage to GND . . . . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 4 MP7614 20 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D20 S1 See Note 1 S 11 20 1 10 E1 E D Q Base Plane Seating Plane A L b INCHES SYMBOL A e b1 MAX MIN MAX –– 0.200 –– 5.08 NOTES –– b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– D –– 1.060 –– 26.92 4 E 0.220 0.310 5.59 7.87 4 E1 0.290 0.320 7.37 8.13 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– L1 0.150 –– 3.81 –– –– Q 0.015 0.070 0.381 1.78 3 S –– 0.080 –– 2.03 6 0.005 –– 0.13 –– 6 0° 15° 0° 15° –– S1 α α NOTES MILLIMETERS MIN c L1 Rev. 2.00 5 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. MP7614 20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20 S 20 11 1 10 Q1 E1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN MAX –– 0.200 –– 5.08 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.945 1.060 24.0 26.92 E 0.295 0.325 7.49 8.26 E1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.040 0.080 1.02 2.03 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 6 C MP7614 20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20 D 20 11 E H 10 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 7 MP7614 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 8