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July 12, 1998
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The MAS9128A is voltage regulator IC with three
2.85V LDO regulators providing voltage regulation
for the handset terminal. The output voltages of the
three regulators can be modified through a mask
option. Two enable/disable pins control the state of
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the regulators. In order to save power the device
goes into sleep mode when all regulators are
disabled. An internal thermal protection circuit
prevents the device from overheating. The
maximum output current is limited internally.
$33/,&$7,21
• 2.85V regulators at 100mA, 70mA and 50mA
• Output accuracy <±3%
• Fast dynamic response
• Low output noise
• Low supply current: 150µA per regulator
• SO8 package
• Mobile phones
• Cordless phones
• Battery powered systems
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ENA
&
&
LDO_A
(100mA)
OUTA
LDO_B
(70mA)
OUTB
LDO_C
(50mA)
OUTC
ENBC
&
Temperature
Protection
&
VCC
Bandgap
Reference
VREF
GND
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DA9128A.002
July 12, 1998
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OUTA
1
8
OUTB
OUTC
2
7
VCC
ENBC
3
6
GND
ENA
4
5
VREF
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OUTA
OUTC
ENBC
ENA
VREF
GND
VCC
OUTA
1
2
3
4
5
6
7
8
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2.85V/100mA regulator output
2.85V/50mA regulator output
Enable for regulators B and C
Enable for regulator A
Reference voltage
Ground
Positive supply voltage
2.85V/70mA regulator output
2
DA9128A.002
July 12, 1998
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(All voltages with respect to ground.)
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Supply Voltage
VCC
-0.3
13.0
V
Logic input voltage
VEN
-0.3
VCC+0.3
0
Max. Junction Temperature
TJ
150
C
0
Thermal resistance
RJA
163
C/W
0
Lead temperature
for 10 seconds
230
C
0
Storage Temperature
TS
-55
+150
C
ESD Rating
Note 1: Stresses beyond those listed may cause permanent damage to the device. The device may not operate
under these conditions, but will not be destroyed.
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Supply Voltage
Operating Temperature
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0LQ
VCC
TAMB
7\S
3.1
-20
0D[
6.5
+70
8QLW
V
C
0
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Threshold high
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TH
Threshold low
TL
0LQ
7\S
0D[
130
150
170
0
160
0
120
140
8QLW
C
C
Continuos power dissipation
in operation
TAMB = 250C
0
TAMB = 70 C
644
mW
368
mW
0
NOTE 2:A hysteresis of 10 C avoids oscillation in case of thermal shutdown. After the regulator temperature
has dropped by this value, it will turn on again automatically.
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0
0
0
(TAMB = -20 C to +70 C, unless otherwise noted. Typical value for T
J is 27 C.)
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Input high voltage
VIH
Input low voltage
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V
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July 12, 1998
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0
0
(TAMB = -20 C to +70 C, unless otherwise noted. Typical value for T
J is 27 C Cin=1µF Cout= 1µF,ceramic)
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Output voltage
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VOUT
3.1V < VCC < 6.5V,
0mA < I OUT < I MAX
2.7
2.85
3.0
V
Short circuit current
LDO_A
IMAXA
310
mA
LDO_B
IMAXB
220
mA
LDO_C
IMAXC
170
mA
Load Current
LDO_A
IOUTA
0
100
mA
LDO_B
IOUTB
0
70
mA
LDO_C
IOUTC
0
50
mA
1.1
10
mV
LDO_A
9
45
mV
LDO_B
6
31
mV
5
22
mV
Line regulation
1Vpp at VCC, max. load
Load regulation
0mA < I OUT < I MAX
LDO_C
o
Load transient
TAMB = 25 C
10uA to ½ load in 1us
-60
mV
100uA to max. Load in 1us (4)
-70
mV
10uA to max. Load in 1us (5)
-85
mV
60
dB
f ≤ 10kHz, 1Vpp at VCC = 4.5V
CREF = 10nF
(3)
PSRR
Quiescent current
per regulator
Total quiescent
current
Noise
(4)
50
IQR
ON, max. load
170
uA
IQR
ON, IOUT = 100uA
150
uA
IQR
OFF
<1
uA
IQ
ENA = ENBC = 0V
IOUT = 0 V CC = 6.5V
<1
10Hz < f < 100kHz
typical load, no capacitor at VREF
10Hz < f < 100kHz
typical load, 10nF cap. at VREF
Enables OFF to ON
2.7V < VOUT < 3.0V
10nF cap. at VREF
190
uVrms
50
uVrms
Settling time
30
µA
0.5
1.0
ms
Output capacitor
COUT
0.8
1.0
2.6
uF
ESR
0.01
0.1
1
Ohm
NOTE 3:To get the real quiescent current of the device, the quiescent current of the reference voltage
generator (140uA typ.) has to be added together once for all regulators.
NOTE 4:VOUT does not drop below 2.7V for more than 1us.
NOTE 5:VOUT does not drop below 2.5V for more than 1us or below 2.7V for more than 50us.
4
DA9128A.002
July 12, 1998
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The device is supplied with 3.1V to 6.5V battery
voltage under normal conditions. An internal band
gap voltage reference is used to generate the
reference voltage for all three voltage regulators.
The reference voltage is routed via an internal
20kOhm Resistor to an external pin where a filter
capacitor can be connected in order to reduce the
noise level of all three regulators. The startup time
of the reference voltage is then determined by the
value of the bypass capacitor at pin VREF.
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Each regulator can be enabled/disabled by the two
enable pins ENA and ENBC. Pin ENA controls
regulator LDO_A and pin ENBC controls both
regulators LDO_B and LDO_C. If both enable pins
are forced low, the internal voltage reference and
internal bias source are turned off in order to save
power. A common enable for all three regulator
outputs is designed, but connected to VDD
internally for the SOIC8 version of MAS9128A.
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The device contains three 2.85V low dropout
CMOS regulators with maximum output currents of
100mA, 70mA and 50mA. There is a mask option
to modify the output voltage to 2.55V, 2.70V,
2.85V, 3.00V or 3.15V. The IC has thermal
protection in order to prevent thermal destruction
especially at high ambient temperatures. Maximum
output current of each regulator is limited by an
internal circuitry. The regulation loop of the
regulators is optimized to work with low ESR
ceramic buffer capacitors at the output.
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ON
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ON
1
0
ON
OFF
OFF
ON
0
1
OFF
ON
ON
ON
0
0
OFF
OFF
OFF
OFF
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July 12, 1998
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8 LEAD SO OUTLINE
1.27
BSC
1.35
1.75
0.25 x 45°
0.50 x 45°
PIN 1
3.80
4.00
5.80
6.20
PAD LAYOUT
4.80
5.00
2.39
7.47
0.71
0.10
0.25
0.33
0.51
0.40
1.27
0° - 8°
SEATING
PLANE
PIN 1
1.27
ALL MEASUREMENTS IN mm
6
DA9128A.002
July 12, 1998
25'(5,1*,1)250$7,21
N
MAS9128AS
MAS9128AS-T
LDO Voltage Regulator IC
LDO Voltage Regulator IC
SO8
SO8
Tape and Reel
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Micronas Semiconductor GmbH
Lohweg 29
D-85375 NEUFAHRN, GERMANY
Tel. (08165) 9521 0
Tel. Int. + 49 8165 9521 0
Telefax + 49 8165 9521 99
Micronas Semiconductor SA
Ch. Chapons-des-Prés
CH-2022 BEVAIX, SWITZERLAND
tel. (032) 847 0111
Tel. Int. +41 32 847 0111
Telefax +41 32 846 1930
Micronas Oy
Kamreerintie 2, P.O.Box 51
FIN-02771 ESPOO, FINLAND
Tel. (09) 80521
Tel. Int. +358 9 80521
Telefax +358 9 8053213
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Micronas reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to
supply the best possible products. Micronas assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license
under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent
infringement. Applications for any devices shown in this data sheet are for illustration only and Micronas makes no claim or warranty that such
applications will be suitable for the use specified without further testing or modification.
7
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