MICRONAS MSP3400C

PRELIMINARY DATA SHEET
MICRONAS
INTERMETALL
MSP 3400 C
Multistandard
Sound Processor
MICRONAS
Edition Dec. 8, 1997
6251-377-3PD
MSP 3400C
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
5
1.
Introduction
6
6
6
6
2.
2.1.
2.2.
2.3.
Features of the MSP 3400C
Features of the Demodulator and Decoder Sections
Features of the DSP-Section
Features of the Analog Section
7
7
3.
3.1.
Application Fields of the MSP 3400C
German 2-Carrier System (DUAL FM System)
9
9
9
9
10
10
10
10
10
10
11
11
11
13
13
14
15
4.
4.1.
4.1.1.
4.1.2.
4.1.3.
4.1.4.
4.1.5.
4.1.6.
4.1.7.
4.1.8.
4.2.
4.3.
4.3.1.
4.4.
4.5.
4.6.
4.7.
Architecture of the MSP 3400C
Demodulator Block
Analog Sound IF – Input Section
Quadrature Mixers
Lowpass Filtering Block for Mixed Sound IF Signals
Phase and AM Discrimination
Differentiators
Lowpass Filter Block for Demodulated Signals
High Deviation FM Mode
MSPC-Mute Function in the Dual Carrier FM Mode
Analog Section and SCART Switching Facilities
MSP 3400C Audio Baseband Processing
Dual Carrier FM Stereo/Bilingual Detection
Audio PLL and Crystal Specifications
ADR Bus
S-Bus Interface
I2S Bus Interface
16
17
18
18
18
18
18
19
5.
5.1.
5.2.
5.2.1.
5.2.2.
5.2.3.
5.2.4.
5.3.
I2C Bus Interface: Device and Subaddresses
Protocol Description
Proposal for MSP 3400C I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start Up Sequence
20
20
21
21
23
24
24
26
6.
6.1.
6.2.
6.2.1.
6.2.2.
6.2.3.
6.2.4.
6.2.5.
Programming the Demodulator Part
Registers: Table and Addresses
Registers: Functions and Values
Setting of Parameter AD_CV
Control Register ‘MODE_REG’
FIR-Filter Switches
FIR-Parameter
DCO-Increments
2
MICRONAS INTERMETALL
PRELIMINARY DATA SHEET
MSP 3400C
Contents, continued
Page
Section
Title
27
27
27
28
28
28
6.3.
6.4.
6.4.1.
6.4.2.
6.4.3.
6.4.4.
Sequences to Transmit Parameters and to Start Processing
Software Proposals for Multistandard TV-Sets
Multistandard System B/G German DUAL FM
Satellite Mode
Automatic Search Function for FM-Carrier Detection
Automatic Standard Detection
29
29
31
32
33
33
34
34
35
35
36
36
36
37
37
37
37
37
38
38
38
38
39
39
40
40
41
41
41
42
42
42
42
42
7.
7.1.
7.1.1.
7.1.2.
7.1.3.
7.1.4.
7.1.5.
7.1.6.
7.1.7.
7.1.8.
7.1.9.
7.1.10.
7.1.11.
7.1.12.
7.1.13.
7.1.14.
7.1.15.
7.1.16.
7.1.17.
7.1.18.
7.1.19.
7.1.20.
7.1.21.
7.1.22.
7.1.23.
7.2.
7.3.
7.3.1.
7.3.2.
7.3.3.
7.3.4.
7.3.5.
7.3.6.
7.3.7.
Programming the Audio Processing Part
Summary of the DSP Control Registers
Volume Loudspeaker Channel and Headphone Channel
Balance Loudspeaker and Headphone Channel
Bass Loudspeaker and Headphone Channel
Treble Loudspeaker and Headphone Channel
Loudness Loudspeaker and Headphone Channel
Spatial Effects Loudspeaker Channel
Volume SCART
Channel Source Modes
Channel Matrix Modes
SCART Prescale
FM Prescale
FM Matrix Modes
FM Fixed Deemphasis
FM Adaptive Deemphasis
I2S1 and I2S2 Prescale
ACB Register, Definition of the SCART-Switches and DIG_CTR_OUT Pins
Beeper
Identification Mode
FM DC Notch
Mode Tone Control
Equalizer Loudspeaker Channel
Automatic Volume Correction (AVC)
Subwoofer on Headphone Output
Exclusions
Summary of Readable Registers
Stereo Detection Register
Quasi Peak Detector
DC Level Register
MSP Hardware Version Code
MSP Major Revision Code
MSP Product Code
MSP ROM Version Code
MICRONAS INTERMETALL
3
MSP 3400C
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
43
43
44
48
51
53
53
54
58
8.
8.1.
8.2.
8.3.
8.4.
8.5.
8.5.1.
8.5.2.
8.5.3.
Specifications
Outline Dimensions
Pin Connections and Descriptions
Pin Configuration
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
64
9.
Application of the MSP 3400C
65
10.
DMA Application
67
11.
MSP Application with External Clock
67
12.
ADR Application
68
13.
I2S Bus in Master/Slave Configuration with Standby Mode
69
14.
APPENDIX A: Technical Code History
69
15.
APPENDIX B: Documentation History
4
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
sound IF signal-in, down to processed analog AF-out, is
performed in a single chip. The IC is produced in 0.8 µm
CMOS technology, combined with high performance
digital signal processing.
Multistandard Sound Processor
Release Notes: The hardware description in this
document is valid for the MSP 3400C – C8 and newer
codes. Revision bars indicate significant changes
to the previous version.
The MSP 3400C 0.8 µ CMOS version is fully pin and
software compatible to the 1.0 µ MSP 3400 and MSP
3410. The main difference between the MSP 3400C and
the MSP 3410, consists of the MSP 3410 being able to
decode NICAM signals.
1. Introduction
The MSP 3400C is designed as single-chip Multistandard Sound Processor for applications in analog and
digital TV sets, satellite receivers and video recorders.
The MSP 3400C is available in PLCC68, PSDIP64,
PSDIP52, and PQFP80 package.
The MSP-family, which is based on the MSP 2400, demonstrates the progressive development towards highly
integrated multi-functional ICs.
Note: To achieve compatibility with the functions of MSP
3400 and MSP 3410 (except NICAM), the load sequences must be programmed as described in the data
sheet of MSP 3410.
The MSP 3400C, again, improves function integration:
The full TV sound processing, starting with analog
MSP 3400C Integrated Functions:
– FM-demodulation of all terrestrial standards (incl. identification decoding)
– FM-demodulation of all satellite standards
– various deemphasis types (incl. Panda1)
– volume, balance, bass, treble, loudness for loudspeaker and headphone output
– automatic volume correction (A.V.C.)
– 5 band graphic equalizer
– subwoofer output alternatively with headphone output
– spatial effect (pseudostereo/basewidth enlargement)
– ADR together with DRP 3510 A
– Dolby ProLogic together with DPL 3418/19/20 A
– 3 pairs of D/A converters
– 1 pair of A/D converters
– SCART switches
ADR/SBus I2S
3
5
I2C
2
Sound IF 1
2
Sound IF 2
2
MONO IN
SCART1 IN
SCART2 IN
SCART3 IN
2
LOUDSPEAKER OUT
HEADPHONE OUT
MSP 3400C
2
2
2
2
SCART1 OUT
SCART2 OUT
Fig. 1–1: Main I/O Signals MSP 3400C
MICRONAS INTERMETALL
5
MSP 3400C
2. Features of the MSP 3400C
2.1. Features of the Demodulator and Decoder
Sections
The MSP 3400C is designed to perform demodulation
of FM-mono TV sound and two carrier FM systems according to the German or Korean terrestrial specs. With
certain constraints, it is also possible to do AM-demodulation according to the SECAM system. Alternatively, the
satellite specs can be processed with the MSP 3400C.
For FM carrier detection in satellite operation, the AMdemodulation offers a powerful feature to calculate the
carrier field strength, which can be used for automatic
search algorithms. So, the IC facilitates a first step towards multistandard capability with its very flexible
application and may be used in TV-sets, satellite tuners,
and video recorders.
The MSP 3400C facilitates profitable multistandard capability, offering the following advantages:
– two selectable analog inputs (TV and SAT-IF sources)
– Automatic Gain Control (AGC) for analog input: input
range: 0.14 – 3 Vpp
– integrated A/D converter for sound-IF inputs
– all demodulation and filtering is performed on chip and
is individually programmable
– no external filter hardware is required
– only one crystal clock (18.432 MHz) is necessary
– FM carrier level calculation for automatic search algorithms and carrier mute function
– high deviation FM-mono mode (max. deviation:
approx. 360 kHz)
PRELIMINARY DATA SHEET
2.2. Features of the DSP-Section
– flexible selection of audio sources to be processed
– digital input and output interfaces via I2S-Bus for external DSP-processors, surround sound, ADR etc.
– digital interface to process ADR (Astra Digital Radio)
together with DRP 3510 A
– performance of all deemphasis systems including
adaptive Wegener Panda 1 without external components or controlling
– digitally performed FM-identification decoding and dematrixing
– digital baseband processing: volume, bass, treble,
5-band equalizer, loudness, pseudostereo, and basewidth enlargement
– simple controlling of volume, bass, treble, equalizer
etc.
– increased audio bandwidth for FM-Audio-signals
(20 Hz – 15 kHz, 1 dB)
2.3. Features of the Analog Section
– three selectable analog pairs of audio baseband inputs (= three SCART inputs)
input level: ≤ 2 V RMS,
input impedance: ≥ 25 kΩ
– one selectable analog mono input (i.e. AM sound),
input level: ≤ 2 V RMS,
input impedance: ≥ 10 kΩ
– two high quality A/D converters, S/N-Ratio: ≥ 85 dB
– 20 Hz to 20 kHz Bandwidth for SCART-to-SCARTCopy facilities
– MAIN (loudspeaker) and AUX (headphones): two
pairs of 4-fold oversampled D/A-converters
output level per channel: max. 1.4 V RMS
output resistance: max. 5 kΩ
S/N-Ratio: ≥ 85 dB at maximum volume
max. noise voltage in mute mode: ≤ 10 µV (BW: 20 Hz
...16 kHz)
– one pair of four-fold oversampled D/A-converters supplying two selectable pairs of SCART-Outputs. Output
level per channel: max. 2 V RMS, output resistance:
max. 0.5 kΩ, S/N-Ratio: ≥ 85 dB
(20 Hz...16 kHz)
6
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
3. Application Fields of the MSP 3400C
3.1. German 2-Carrier System (DUAL FM System)
The MSP 3400C processes TV sound according to the
German and Korean two carrier system and the commonly used satellite systems. In the following sections,
a brief overview on the German FM-Stereo system
shows what is required of a multistandard audio IC.
Since September 1981, stereo and dual sound programs have been transmitted in Germany using the
2-carrier system. Sound transmission consists of the already existing first sound carrier and a second sound
carrier additionally containing an identification signal.
More details of this standard are given in Table 3–1.
Table 3–1: European TV standards
TV-System
Position of Sound
Carrier /MHz
Sound
Modulation
Color System
Country
B/G
5.5/5.7421875
FM-Stereo
PAL
Germany
B/G
5.5/5.85
FM-Mono/NICAM
PAL
Scandinavia,Spain
L
6.5/5.85
AM-Mono/NICAM
SECAM-L
France
I
6.0/6.552
FM-Mono/NICAM
PAL
UK
D/K
6.5 /6.2578125 D/K1
6.5/6.7421875 D/K2
6.5/5.85 D/K-NICAM
FM-Stereo
SECAM-East
USSR
M
M-Korea
4.5
4.5/4.724212
FM-Mono
FM-Stereo
NTSC
USA
Korea
Satellite
Satellite
6.5
7.02/7.2
FM-Mono
FM-Stereo
PAL
PAL
Europe (ASTRA)
Europe (ASTRA)
33
34
FM-Mono/NICAM
39 MHz
SAW Filter
5
Hungary
9 MHz
Sound IF Filter
Sound
IF
Mixer
Tuner
Loudspeaker
AM Sound
Vision
Demodulator
MSP 3400C
SCART1
Composite
Video
SCART
Inputs
SCART2
SCART3
According to the mixing characteristics of
the Sound-IF-mixer, the Sound-IF filter
may be omitted.
Headphone
2
2
2
2
SCART1
SCART
Outputs
SCART2
2
I 2S
optional
Feature
Processor
I 2S
SBUS / ADR
AMU and DMA
or DRP
Fig. 3–1: Typical MSP 3400C application
MICRONAS INTERMETALL
7
MSP 3400C
PRELIMINARY DATA SHEET
Table 3–2: Key parameters for B/G, D/K, and M 2-carrier sound system
Sound Carriers
Carrier FM1
B/G
Carrier FM2
D/K
Vision/sound power difference
Frequency deviation
B/G
D/K
13 dB
Sound bandwidth
Pre-emphasis
M
M
20 dB
40 Hz to 15 kHz
50 µs
75 µs
50 µs
75 µs
±50 kHz
±25 kHz
±50 kHz
±25 kHz
Sound Signal Components
Mono transmission
Stereo transmission
Dual sound transmission
mono
(L+R)/2
language A
mono
(L+R)/2
R
(L–R)/2
language B
Identification of Transmission Mode on Carrier FM2
Pilot carrier frequency in kHz
54.6875
55.0699
Type of modulation
AM
Modulation depth
50%
Modulation frequency
mono: unmodulated
stereo: 117.5 Hz
dual:
274.1 Hz
149.9 Hz
276.0 Hz
Note: NICAM decoding can be achieved by using the
MSP 3410 instead of the MSP 3400C. Since the
MSP 3400C and the MSP 3410 are fully pin and software downwards compatible (concerning all features of
MSP 3410), it is possible to decide in the assembly line,
whether the application should be able to decode
NICAM or not.
8
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Some combinations of SAW filters and sound IF mixer
ICs, however, show large picture components on their
outputs. In this case, filtering is recommended. It was
found that the high pass filters formed by the coupling
capacitors at pins ANA_IN1+ and ANA_IN2+ as shown
in the application diagram are sufficient in most cases.
4. Architecture of the MSP 3400C
Fig. 4–1 shows a simplified block diagram of the IC. Its
architecture is split into three functional blocks:
1. demodulator section
2. digital signal processing (DSP) section performing
audio baseband processing
4.1.2. Quadrature Mixers
3. analog section containing two A/D-converters,
6 D/A-converters, and SCART switching facilities
The digital input coming from the integrated A/D converter may contain audio information at a frequency range
of theoretically 0 to 9 MHz corresponding to the selected
standards. By means of two programmable quadrature
mixers two different audio sources, for example FM1
and FM2, may be shifted into baseband position. In the
following, the two main channels are provided to process either:
4.1. Demodulator Block
4.1.1. Analog Sound IF – Input Section
The input pins ANA_IN1+, ANA_IN2+, and ANA_IN–
offer the possibility to connect two different sound IF
sources to the MSP 3400C. By means of bit [8] of
AD_CV (see Table 6–3), either terrestrial or satellite
sound IF signals can be selected. The analog-to-digital
conversion of the preselected sound IF signal is done by
a flash-converter, whose output can be used to control
an automatic gain circuit (AGC), providing optimum level
for a wide range of input levels. It is possible to switch
between automatic gain control and a fixed (setable) input gain. In the optimum case, the input range of the A/D
converter is completely covered by the sound IF source.
– FM2 (channel 1) and FM1 (channel 2).
Two independent digital oscillators are provided to generate two pairs of sin/cos-functions. Two programmable
increments, to be divided up into Low- and High Part, determine frequency of the oscillator, which corresponds
to the frequency of the desired audio carrier. In section
6.1., format and values of the increments are listed.
AUD_CL_OUT XTAL_OUT
I2S_DA_OUT
I2S_CL
XTAL_IN
I2S_WS
I2S_DA_IN_1/2
S_CL / ADR_CL
S_DA_IN / ADR_DA
S_ID / ADR_WS
I2S Interface
SBUS/ADR Interface
Sound IF
ANA_IN1+
– FM mono (channel 2) or
S1..4
I2S1/2L/R I2SL/R
FM1 / AM
Demodulator
ANA_IN2+
Audio PLL
FM2
LOUDSPEAKER L
D/A
DACM_L
LOUDSPEAKER R
D/A
DACM_R
Loudspeaker
DFP
IDENT
Mono
MONO_IN
HEADPHONE L
D/A
DACA_L
SC1_IN_L
HEADPHONE R
D/A
DACA_R
SCART_L
D/A
SC1_OUT_L
SCART_R
D/A
SC1_OUT_R
SCART1
SC1_IN_R
A/D
SC2_IN_L
A/D
SCART_L
SCART_R
SCART2
SCART 1
SC2_IN_R
SC2_OUT_L
SC3_IN_L
SCART3
Headphone
SCART Switching Facilities
SCART 2
SC2_OUT_R
SC3_IN_R
Fig. 4–1: Architecture of the MSP 3400C
MICRONAS INTERMETALL
9
MSP 3400C
PRELIMINARY DATA SHEET
DCO1
ADR_DA
Oscillator
MODE_REG[8]
FIR_REG_1
Phase
Mixer
Lowpass
Differentiator
Phase and
AM Discrimination
Mute
Lowpass
FM2
Mixer
IDENT
VREFTOP
MSPC sound IF channel 1
(MSP-CH1: FM2)
Amplitude
Carrier
Detect
AD_CV[7:1]
ANA_IN1+
AGC
AD_CV[9,10,11]
AD
ANA_IN2+
Carrier
Detect
AD_CV[8]
MSPC sound IF channel 2
(MSP-CH2: FM1, AM)
ANA_IN–
Mixer
Lowpass
Amplitude
Phase and
AM Discrimination
Mute
Phase
FRAME
FM2
DCO2
FIR_REG_2
Pins
Lowpass
FM1/AM
Differentiator
MODE_REG[8]
Oscillator
Internal signal lines
Control registers
DCO2
Fig. 4–2: Demodulator architecture
4.1.3. Lowpass Filtering Block for Mixed Sound IF
Signals
cy of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz.
FM bandwidth limitation is performed by a linear phase
Finite Impulse Response (FIR-filter). Just like the oscillators’ increments, the filter coefficients are programmable and are written into the IC by the CCU via the control bus. Two not necessarily different sets of coefficients
are required, one for channel 1 (FM2) and one for channel 2 (FM1=FM-mono). In section 6.2.4., several coefficient sets are proposed.
4.1.7. High Deviation FM Mode
4.1.4. Phase and AM Discrimination
The filtered sound IF signals are demodulated by means
of the phase and amplitude discriminator block. On the
output, the phase and amplitude is available for further
processing. AM signals are derived from the amplitude
information, whereas the phase information serves for
FM demodulation.
4.1.5. Differentiators
FM demodulation is completed by differentiating the
phase information output.
4.1.6. Lowpass
Signals
Filter
Block
for
Demodulated
The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling frequen10
By means of MODE_REG [9], the maximum FM-deviation can be extended to approximately 360 kHz.
Since this mode can be applied only for the MSPC sound
IF channel 2, the corresponding matrices in the baseband processing must be set to sound A. Apart from this,
the coefficient sets 380 kHz FIR_REG2 or 500 kHz
FIR_REG2 must be chosen for the FIR_REG_2. For a
given deviation, in relation to the normal FM-mode, the
audio level of the high-deviation mode is reduced by
6 dB.
4.1.8. MSPC-Mute Function in the Dual Carrier FM
Mode
To prevent noise effects or FM identification problems in
the absence of one of the two FM carriers, the
MSP 3400 C offers a carrier detection feature, which
must be activated by means of AD_CV[9]. The mute level may be programmed by means of AD_CV[10,11].
(see section 6.2.1.) If no FM carrier is available at the
MSPC channel 1, the corresponding channel FM2 is
muted. If no FM carrier is available at the MSPC channel
2, the corresponding channel FM1 is muted. In case of
the absence of both FM carriers, pure noise will be amplified by the input AGC. Therefore, a proper mute function depends on the noise quality of the TV set’s IF part
and cannot be guaranteed. The mute function is not recommended for the satellite mode.
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
4.2. Analog Section and SCART Switching Facilities
4.3. MSP 3400C Audio Baseband Processing
The analog input and output sections offer a wide range
of switching facilities, which are shown in Fig. 4–3. To
design a TV-set with 3 pairs of SCART-inputs and two
pairs of SCART-outputs, no external switching hardware
is required.
By means of the DFP processor, all audio baseband
functions are performed by digital signal processing
(DSP). The DSP functions are grouped into three processing parts: input preprocessing, channel selection,
and channel postprocessing.
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 7. Programming the Audio Processing Part).
The input preprocessing is intended to prepare the various signals of all input sources in order to form a standardized signal at the input to the channel selector. The
signals can be adjusted in volume, are processed with
the appropriate deemphasis, and are dematrixed if necessary.
If the MSP 3400C is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Standby’-mode), the switches
S1, S2, and S3 maintain their position and function. This
facilitates the copying from selected SCART-inputs to
SCART-outputs in the TV-sets standby mode.
SCART_IN
ACB[1:0]
SC1_IN_L/R
MONO
2
00
2
01
2
10
2
11
to Audio Baseband
Processing (DFP)
SC3_IN_L/R
2
SCARTL/R
S1
ACB[3:2]
00
2
01
2
10
2
11
SCART_OUT
All input and output signals can be processed simultaneously. Note that the NICAM input signals are only
available in the MSP 3410 version. While processing the
adaptive deemphasis, no dual carrier stereo (German or
Korean) is possible. Identification values are not valid either.
2
from Audio Baseband
Processing (DFP)
SCARTL/R
2
The ability to route in an external coprocessor for special
effects like surround and sound field processing is of
special importance. Routing can be done with each input
source and output channel via the I2S inputs and outputs.
A
D
SC2_IN_L/R
Having prepared the signals that way, the channel selector makes it possible to distribute all possible source signals to the desired output channels.
SC1_OUT_L/R
4.3.1. Dual Carrier FM Stereo/Bilingual Detection
D
2
A
S2
ACB[5:4]
2
00
2
01
2
10
2
SC2_OUT_L/R
S3
In the German and Korean TV standard, audio information can be transmitted in three modes: mono, stereo, or
bilingual. To obtain information about the current audio
operation mode, the MSP 3400C detects the so-called
identification signal. Information is supplied via the Stereo Detection Register to an external CCU.
Fig. 4–3: SCART-Switching Facilities
Bold lines determine the default configuration
Stereo
Detection
Filter
IDENT
In case of power-on start or starting from standby, the IC
switches automatically to the default configuration,
shown in Fig. 4–3. This takes place after the first I2C
transmission into the DFP part. By transmitting the ACB
register first, the default setting mode can be changed.
MICRONAS INTERMETALL
Level
Detect
AM
Demodulation
–
Bilingual
Detection
Filter
Stereo
Detection
Register
Level
Detect
Fig. 4–4: Stereo/bilingual detection
11
MSP 3400C
12
Analog
Inputs
SCART
SCARTL
Loudspeaker
Channel
Matrix
Prescale
SCARTR
AVC
Bass/
Treble
or
Equalizer
∑
Loudness
DC level readout FM1
FM1
Demodulated
IF
Inputs
FM2
Adaptive
Deemphasis
Deemphasis
50/75 µs
J17
Complementary
Highpass
Spatial
Effects
Loudspeaker
Outputs
Loudspeaker R
Level
Adjust
Lowpass
FM
Loudspeaker L
Balance
Volume
Subwoofer
Beeper
FM-Matrix
Prescale
Headphone L
DC level readout FM2
Headphone
Channel
Matrix
Bass/
Treble
∑
Headphone
Outputs
Volume
Loudness
Balance
Headphone R
SBUS1
SBUS2
Channel Select
SBUS
Inputs
SBUS3
SBUS4
I 2S Bus
Inputs
I 2S1L
I 2S1
I 2S1R
Prescale
I 2S2L
I 2S2
I 2S2R
Prescale
SCART
Outputs
SCART_R
I 2SL
I 2S
Channel
Matrix
Quasi-PeakChannel
Matrix
SCART_L
I 2S
Outputs
I 2SR
Quasi peak readout L
Quasi-Peak
Detector
Quasi peak readout R
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
Fig. 4–5: Audio baseband processing (DSP-Firmware)
Volume
SCART
Channel
Matrix
MSP 3400C
PRELIMINARY DATA SHEET
Table 4–1: Several examples for recommended channel assignments for demodulator and audio processing part
Mode
MSPC Sound IFChannel 1 / FM2
MSPC Sound IFChannel 2 / FM1
FMMatrix
Channel
Select
Channel
Matrix
B/G-Stereo
FM2 (5.74 MHz): R
FM1 (5.5 MHz): (L+R)/2
B/G Stereo
Speakers: FM
Stereo
B/G-Bilingual
FM2 (5.74 MHz): Sound B
FM1 (5.5 MHz): Sound A
No Matrix
Speakers: FM
H.Phone : FM
Speakers: Sound A
H.Phone : Sound B
Sat-Mono
not used
FM (6.5 MHz): mono
No Matrix
Speakers: FM
Sound A
Sat-Stereo
7.20 MHz: R
7.02 MHz: L
No Matrix
Speakers: FM
Stereo
Sat-Bilingual
7.38 MHz: Sound C
7.02 MHz: Sound A
No Matrix
Speakers: FM
H.Phone : FM
Speakers: Sound A
H.Phone :Sound B=C
Sat High Dev.
Mode (e.g.
EutelSat)
don’t care
6.552 MHz
No Matrix
Speakers: FM
H.Phone : FM
Speakers: Sound A
H.Phone : Sound A
4.4. Audio PLL and Crystal Specifications
The MSP 3400C runs at 18.432 MHz. A detailed specification of the required crystal for different packages and
master/slave applications can be found in Table 8.5.2.
The clock supply of the entire system depends on the
MSP 3400C operation mode:
1. FM-Stereo/I2S Master operation:
The system clock runs free on the crystal’s 18.432 MHz.
2. I2S Slave operation:
In this case, the system clock is synchronizing on the
I2S_WS signal, which is fed into the MSP 3400C
(Mode_Reg[3] = 1).
3. D2-MAC operation:
In this case, the system clock is locked to a synchronizing signal (DMA_SYNC) supplied by the D2-MAC chip
(Mode_Reg[0] = 1). The DMA and the AMU chips can be
driven by the MSP 3400C audio clock (AUD_CL_OUT).
Remark on using the crystal:
External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilizing the frequency in closed-loop operation. The higher the
capacitors, the lower the clock frequency results. The
MICRONAS INTERMETALL
nominal free running frequency should match the center
of the tolerance range between 18.433 and 18.431 MHz
as closely as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application (see also Table 8.5.2.).
4.5. ADR Bus
To be able to process ADR, the MSPC has a special designed interface to work together with DRP 3510A. To be
prepared for an upgrade to ADR with an additional DRP
board, the following lines of MSP 3400C should be provided on a feature connector:
– AUD_CL_OUT
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
– I2S_WS
– I2S_CLK
– S_CL = ADR_CL
– S_ID = ADR_WS
– S_DA_IN = ADR_DA
13
MSP 3400C
PRELIMINARY DATA SHEET
4.6. S-Bus Interface
Digital audio information provided by the DMA 2381 via
the AMU is serially transmitted to the MSP 3400C via the
S-Bus. The MSP 3400C is always in S-Bus master
mode.
The S-Bus interface consists of three pins:
1. S_DA_IN:
Four channels (4*16 bits) per sampling cycle (32 kHz)
are transmitted.
2. S_CL:
Gives the timing for the transmission of S-DATA
(4.608 MHz).
3. S_ID:
After 64 S-CLOCK cycles, the S_ID determines the end
of one sampling period.
A detailed timing diagram is shown in Fig. 4–6.
(Data: MSB first)
H
S-Ident
L
H
S-Clock
64 Clock Cycles
L
H
S-Data
16 Bit Sound 1
16 Bit Sound 2
16 Bit Sound 3
16 Bit Sound 4
L
A
B
Section B
Section A
tS6
H
H
S-Ident
S-Ident
L
L
tS1
tS2
H
S-Clock
4.608 MHz L
tS3
H
S-Clock
4.608 MHz L
tS4
tS5
H
LSB of Sound 1
S-Data
L
H
S-Data
MSB of Sound 4
L
Fig. 4–6: S-Bus timing diagram
14
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
The I2S bus interface consists of five pins:
4.7. I2S Bus Interface
1. I2S_DA_IN1:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
By means of this standardized interface, additional feature processors can be connected to the MSP 3400C.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I2S_WS signal changes at the word boundaries. The so-called PHILIPS format, which is characterized by a change of the I2S_WS signal, one I2S_CL period before the word boundaries, is selected by setting
MODE_REG[4]=1.
2. I2S_DA_IN2:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
3. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
4. I2S_CL:
Gives the timing for the transmission of I2S serial data
(1.024 MHz).
The MSP 3400C normally serves as the master on the
I2S interface. Here, the clock and word strobe lines are
driven by the MSP 3400C. By setting MODE_REG[3]=1,
the MSP 3400C is switched to a slave mode. Now, these
lines are input to the MSP 3400 C, and the master clock
is synchronized to 576 times the I2S_WS rate (32 kHz).
No D2MAC operation is possible in this mode.
5. I2S_WS:
The I2S_WS word strobe line defines the left and right
sample.
A detailed timing diagram is shown in Fig. 4–7.
(Data: MSB first)
FI2SWS
I2S_WS
SONY Mode
PHILIPS Mode
SONY Mode
PHILIPS Mode
PHILIPS/SONY Mode programmable by MODE_REG[4]
Detail C
I2S_CL
Detail A
I2S_DAIN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit right channel
16 bit left channel
Detail B
I2S_DAOUT
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit left channel
Detail C
FI2SCL
16 bit right channel
Detail A,B
I2S_CL
I2S_CL
TI2SWS1
TI2S1
TI2SWS2
I2S_WS as INPUT
TI2S2
I2S_DA_IN
TI2S5
I2S_WS as OUTPUT
TI2S3
TI2S6
TI2S4
I2S_DA_OUT
Fig. 4–7: I2S Bus timing diagram
MICRONAS INTERMETALL
15
MSP 3400C
PRELIMINARY DATA SHEET
of data. Refer to Fig. 5–1 I2C Bus Protocol and section
5.2. Proposal for MSP 3400C I2C Telegrams.
5. I2C Bus Interface: Device and Subaddresses
As a slave receiver, the MSP 3400C can be controlled
via I2C bus. Access to internal memory locations is
achieved by subaddressing. The demodulator part and
the audio processor part (DFP) have two separate subaddressing register banks.
Due to the internal architecture of the MSP 3400C, the
IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the addressed processor is not ready for further transmissions on the I2C
bus, the clock line I2C_CL is pulled low. This puts the
current transmission into a wait state. After a certain period of time, the MSP 3400C releases the clock, and the
interrupted transmission is carried on.
In order to allow for more MSP 3400C ICs to be connected to the control bus, an ADR_SEL pin has been implemented. With ADR_SEL pulled to high, the MSP
3400C responds to changed device addresses, thus two
identical devices can be selected. Other devices of the
same family will have different subaddresses (e.g. 34x0)
The I2C Bus lines can be set tristate by switching the IC
into “Standby”-mode.
I2C-Bus error conditions:
In case of any internal error, the MSP’s wait-period is extended to 1.77 ms. Afterwards, the MSP does not acknowledge (NAK) the device address. The data line will
be left HIGH by the MSP, and the clock line will be released. The master can then generate a STOP condition
to abort the transfer.
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
The IC is selected by asserting a special device address
in the address part of an I2C transmission. A device address pair is defined as a write address (80 hex or 84
hex) and a read address (81 hex or 85 hex). Writing is
done by sending the device write address first, followed
by the subaddress byte, two address bytes, and two
data bytes. For reading, the read address has to be
transmitted first by sending the device write address (80
hex or 84 hex), followed by the subaddress byte, and two
address bytes. Without sending a stop condition, reading of the addressed data is done by sending the device
read address (81 hex or 85 hex) and reading two bytes
By means of NAK, the master is able to recognize the error state and to reset the IC via I2C-Bus. While transmitting the reset protocol (section. 5.2.4.) to ‘CONTROL’,
the master must ignore the not acknowledge bits (NAK)
of the MSP.
A detailed timing diagram is shown in Fig. 5–1 and
Fig. 5–2.
Table 5–1: I2C Bus Device Addresses
ADR_SEL
Low
High
Left Open
Mode
Write
Read
Write
Read
Write
Read
MSP device address
80 hex
81 hex
84 hex
85 hex
88 hex
89 hex
Table 5–2: I2C Bus Device and Subaddresses
16
Name
Binary Value
Hex Value
Function
CONTROL
0000 0000
00
software reset
TEST1
0000 0001
01
only for internal use
TEST2
0000 0010
02
only for internal use
WR_DEM
0001 0000
10
write address demodulator
RD_DEM
0001 0001
11
read address demodulator
WR_DFP
0001 0010
12
write address DFP
RD_DFP
0001 0011
13
read address DFP
AGC
0001 1110
1E
read AGC RMS
PLL_CAP
0001 1111
1F
read / write PLL_Cap
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Table 5–3: Control Register
Name
15
14..0
CONTROL
RESET
0
5.1. Protocol Description
Write to DFP or Demodulator Part (long protocol)
S
daw
Wait
ACK
sub-addr
ACK
addr-byte
high
ACK
addr-byte low
ACK
data-byte high
ACK
daw
Wait
ACK
sub-addr
ACK
addr-byte
high
ACK
addr-byte
low
ACK
S
dar
Wait
ACK
P
ÇÇÇ ÇÇ
ÇÇÇ
ÇÇ
ÇÇÇ ÇÇ
Read from DFP Part (long protocol)
S
data-byte low
ACK
data-byte
high
ACK
data-byte
low
NAK
P
Write to Control / Test / AGC / PLL_Cap Registers (short protocol)
S
daw
Wait
ACK
sub-addr
ACK
data-byte high
ACK
daw
Wait
ACK
sub-addr
ACK
S
dar
Wait
ACK
ACK
P
ÇÇÇ ÇÇÇ
ÇÇÇ ÇÇÇ
Read from Control / Test / AGC / PLL_Cap Registers (short protocol)
S
data-byte low
data-byte high
ACK
data-byte low
NAK
P
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Device Address Write
Device Address Read
Acknowledge-Bit: LOW on I2C_DA from slave (= MSPC, grey)
or master (= CCU, hatched)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate
‘End of Read’ or from MSPC indicating internal error state (not illustrated)
Wait = I2C-Clock line held low by the slave (= MSPC) while interrupt is serviced (<1.77 ms)
Note: S =
P=
daw =
dar =
ACK =
I2C_DA
S
1
0
P
I2C_CL
Fig. 5–1: I2C bus protocol
MICRONAS INTERMETALL
(MSB first; data must be stable while clock is high)
17
MSP 3400C
PRELIMINARY DATA SHEET
(Data: LSB first)
FIM
TI2C4
I2C_CL
TI2C1
TI2C5
TI2C3
TI2C6
TI2C2
I2C_DA as input
TIMOL2
TIMOL1
I2C_DA as output
Fig. 5–2: I2C bus timing diagram
5.2. Proposal for MSP 3400C I2C Telegrams
5.2.1. Symbols
daw
dar
<
>
aa
dd
device address write
device address read
Start Condition
Stop Condition
Address Byte
Data Byte
5.2.2. Write Telegrams
<daw 00 dd dd>
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
software RESET
write data into demodulator register
write data into DFP register
5.2.3. Read Telegrams
<daw 11 aa aa <dar dd dd>
<daw 13 aa aa <dar dd dd>
read data from demodulator
read data from DSP
5.2.4. Examples
<daw 00 80 00>
<daw 00 00 00>
<daw 12 00 08 00 20>
18
RESET MSPC statically
clear RESET
set loudspeaker channel source
to FM and Matrix to STEREO
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
5.3. Start Up Sequence
After power on or RESET, the IC is in an inactive state.
The CCU has to transmit the required coefficient set for
a given operation via the I2C bus. Initialization must start
with the demodulator part. If required for any reason, the
audio processing part can be loaded before the demodulator part.
The reset pin should not be > 0.45 DVSUP (see recommended operation conditions) before the 5 Volt digital
power supply (DVSUP) and the analog power supply
(AVSUP) are > 4.75 Volt and the MSP-Clock is running
(Delay: 2 ms max, 0.5 ms typ.).
This means, if the reset low-high edge starts with a delay
of 2 ms after DVSUP> 4.75 Volt and AVSUP>4.75 Volt,
even under worst case conditions, the reset is ok.
DVSUP/V
AVSUP/V
4.75
Oscillator
RESETQ
time / ms
max. 2
time / ms
min. 2
0.45 * DVSUP
time / ms
Fig. 5–3: Power-up sequence
MICRONAS INTERMETALL
Note: The reset should
not reach high level before the oscillator has
started. This requires a
reset delay of >2 ms
19
MSP 3400C
PRELIMINARY DATA SHEET
6. Programming the Demodulator Part
6.1. Registers: Table and Addresses
In Table 6–1, all Write Registers are listed.
All transmissions on the control bus are 16 bits wide.
Data for the demodulator part has 8 or 12 significant bits.
These data have to be inserted LSB bound and filled
with zero bits into the 16 bit transmission word. If channel 1 or channel 2 is selected in the channel matrix while
any of the parameters are changed, the corresponding
output must be muted. Click and crack noise may occur
during coefficient changes. Table 4–1 explains how to
assign FM carriers to the MSPC-Sound IF channels and
the corresponding matrix modes in the audio processing
part.
Table 6–1: MSP 3400C demodulator write registers
Register
Protocol
Write
Address
(hex)
Function
AD_CV
long
00BB
input selection, configuration of AGC and Mute Function,
and selection of A/D-converter
MODE_REG
long
0083
mode register
FIR_REG_1
FIR_REG_2
long
long
0001
0005
serial shift register for 6 ⋅ 8 bit, filter coefficient channel 1 (48 bit)
serial shift register for 6 ⋅ 8 bit, + 2 ⋅ 12 bit off set (total 72 bit)
DCO1_LO
DCO1_HI
DCO2_LO
DCO2_HI
long
long
long
long
0093
009B
00A3
00AB
increment channel 1 Low Part
increment channel 1 High Part
increment channel 2 Low Part
increment channel 2 High Part
PLL_CAP1)
short
1F
switchable PLL capacities
Table 6–2: MSP 3400C demodulator read registers
Register
Protocol
Read
Address
(hex)
Function
PLL_CAP1)
short
1F
switchable PLL capacities
AGC_RMS1)
short
1E
RMS value, comparable with reference value
C_AD_BITS
long
0023
A read from this address always responds with 0. This ensures
software compatibility with the MSP 3410 readout. Reading 0 from
this register signals “No NICAM”.
1) The registers PLL_CAP and AGC_RMS are only available in MSP 3400C. In MSP 3410 and MSP 34x0D, this register
cannot be accessed.
20
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
6.2. Registers: Functions and Values
In the following, the functions of several registers are explained and their (default) values are defined.
6.2.1. Setting of Parameter AD_CV
Table 6–3: AD_CV Register
AD_CV Bit Range
Meaning
Settings
AD_CV [0]
not used
must be set to 0
AD_CV [6:1]
Reference level in case of Automatic Gain
Control = on.
Constant gain factor when Automatic Gain
Control = off .
see Table 6–5
AD_CV [7]
Determination of Automatic Gain or Constant
Gain
0 = constant gain
1 = automatic gain
AD_CV [8]
Selection of analog input
0 = ANALOG IN1
1 = ANALOG IN2
AD_CV [9]
MSPC-Carrier-Mute Function
0 = off: no mute
1 = on: mute (see section 4.1.8.)
AD_CV [11–10]
Programmable Carrier-Mute Level
see Table 6–4
AD_CV [15–12]
not used
must be set to 0
see Table 6–6
Table 6–4: Carrier Mute Level
Step
AD_CV [11:10]
binary
AD_CV [11:10]
decimal
0
1
2
3
00
01
10
11
0
1
2
3
Internal reference level for mute active
(dBr: relative to MSP 3410 )
0 dBr
–3 dBr
–6 dBr
–12 dBr
Table 6–5: Reference values AD_CV [6:1] for active AGC (AD_CV[7] = 1)
Application
Input Signal Contains
Ref. Value
binary
Ref. Value
decimal
Range of Input Signal
at pin ANA_IN_1+ and
ANA_IN_2+
Terrestrial TV
2 FM Carriers
101000
40
0.14 – 3 Vpp1)
SAT
1 or more FM Carriers
100011
35
0.14 – 3 Vpp1)
ADR
1 or more FM Carriers and
1 or more ADR Carriers
010100
20
0.14 – 3 Vpp1)
1)
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the AD converter may result. Due
to the robustness of the internal processing in FM mode, the IC works properly up to and even more than 3 Vpp. In AM
mode, of course, no AD converter overflow is allowed. As a consequence, in the AM-mode, the maximum input at pins
41 or 43 must not exceed 1.4 Vpp.
MICRONAS INTERMETALL
21
MSP 3400C
PRELIMINARY DATA SHEET
Table 6–6: AD_CV parameters for constant input gain (AD_CV[7]=0)
Step
AD_CV [6:1]
Constant Gain
Gain
Input Level at pin ANA_IN1+ and ANA_IN2+
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
3.00 dB
3.85 dB
4.70 dB
5.55 dB
6.40 dB
7.25 dB
8.10 dB
8.95 dB
9.80 dB
10.65 dB
11.50 dB
12.35 dB
13.20 dB
14.05 dB
14.90 dB
15.75 dB
16.60 dB
17.45 dB
18.30 dB
19.15 dB
20.00 dB
maximum input level1): 3 Vpp (FM) or 1.4 Vpp (AM)
maximum input level: 0.14 Vpp1)
1)
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the AD converter may result. Due
to the robustness of the internal processing in FM mode, the IC works properly up to and even more than 3 Vpp. In AM
mode, of course, no AD converter overflow is allowed. As a consequence, in the AM-mode, the maximum input at pins
41 or 43 must not exceed 1.4 Vpp.
22
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
6.2.2. Control Register ‘MODE_REG’
The register ‘MODE_REG’ contains the control bits determining the operation mode of the MSP 3400C; Table
6–7 explains all bit positions.
Table 6–7: Control word ‘MODE_REG’: All bits are “0” after power-on-reset
Bit
Function
Comment
Definition
Recommendation
[0]
DMA_SYNC1)
Synchronization to DMA
0 : off
1 : on
X
[1]
DCTR_TRI
Digital control out 0/1 tristate
0 : active
1 : tristate
0
[2]
I2S_TRI
I2S outputs tristate (I2S_CL,
I2S_WS, I2S_DA_OUT)
0 : active
1 : tristate
0
[3]
I2S Mode1)
Master/Slave mode of the
I2S bus
0 : Master
1 : Slave
X
[4]
I2S_WS Mode
WS due to the Sony or
Philips-Format
0 : Sony
1 : Philips
X
[5]
Audio_CL_OUT
switch Audio_Clock_Output
to tristate
0 : on
1 : tristate
X
[6]
not used
must be 0
0
[7]
FM1 FM2
MSPC-channel 1 mode
[8]
AM
MSPC-channel 1/2 mode
0 : FM
1 : AM
s.Table 6–8
[9]
HDEV
High Deviation Mode
(channel matrix must be
sound A )
0 : normal mode
1 : high deviation mode
s.Table 6–8
[10]
not used
must be 1
1
[11]
S-Bus Mode2)
mode of Pins S_CL and S_ID
0 : Tristate
1 : Active
0
[12]
FM2 FIR Filter Gain
(FM2 = Ch1)
see table 6–10
0 : Gain = 6 dB
1 : Gain = 0 dB
0
[13]
FM2 FIR Filter Coeff. Set
(FM2 = Ch1)
see table 6–10
0 : use FIR_REG_1
1 : use FIR_REG_2
0
[14]
ADR
Mode of ADR Interface
0 : normal mode
1 : ADR mode
X
[15]
AM-Gain
additional gain in AM-mode
0 : 0 dB
1 : +12 dB
0
1)
2)
s.Table 6–8
In case of synchronization to DMA, no I2S-slave mode possible.
In case of I2S-slave mode, no synchronization to DMA allowed. I2S-Slave mode dominates.
The normal operation mode is ‘Tristate’; SBUS is only used in conjunction with DMA.
MICRONAS INTERMETALL
X: Depending on mode
23
MSP 3400C
PRELIMINARY DATA SHEET
Table 6–8: Channel modes ‘MODE_REG [7–9]‘
FM1 FM2
bit[7]
AM
bit[8]
HDEV
bit[9]
channel 1
channel 2
0
0
0
mute
FM-Mono (FM1)
1
0
0
FM2
FM1
X
1
0
AM
AM
X
X
1
FM-Mono (high deviation)
FM-Mono (high deviation)
6.2.3. FIR-Filter Switches
To simplify programming of the MSP 3400C, two additional switches have been implemented.
The FIR filter for channel1/FM2 can use either
FIR_REG_1 coefficients or FIR_REG_2 coefficients by
means of MODE_REG[13]. Herewith, it is no longer necessary to transmit both coefficient sets in FM-terrestrial
mode. The loading sequence for FIR_REG_2 is sufficient.
The additional gain of +6 dB in channel1/FM2 can be
switched to 0 dB by means of MODE_REG[12]. Together with MODE_REG[13] set to 1, in satellite mode, it is
no longer necessary to transmit both FIR filter coefficient
sets. The loading sequence for FIR_REG_2 is sufficient.
6.2.4. FIR-Parameter
The following data values (see Table 6–9) are to be
transferred 8 bits at a time embedded LSB-bound in
a 16 bit word. These sequences must be obeyed. To
change a coefficient set, the complete block
FIR_REG_1 or FIR_REG_2 must be transmitted. The
new coefficient set will be active without a load_reg routine.
Table 6–9: Loading sequence for FIR-coefficients
WRITE_ADR = FIR_REG_1(Channel 1: FM2)
No.
Symbol Name
Bits
Value
1
FM2_Coeff. (5)
8
see Table 6–10.
2
FM2_Coeff. (4)
8
3
FM2_Coeff. (3)
8
4
FM2_Coeff. (2)
8
5
FM2_Coeff. (1)
8
6
FM2_Coeff. (0)
8
WRITE_ADR = FIR_REG_2 (Channel 2: FM1/FM
mono)
No.
Symbol Name
Bits
Value
1
* IMREG1 (8 LSBS)
8
04 HEX
2
* IMREG1 / IMREG2
(4 MSBs / 4 LSBs)
8
40 HEX
3
* IMREG2 (8 MSBs)
8
00 HEX
see Table 6–10.
4
FM_Coef (5)
8
5
FM_Coef (4)
8
6
FM_Coef (3)
8
7
FM_Coef (2)
8
8
FM_Coef (1)
8
9
FM_Coef (0)
8
* IMREG_1/2: Two 12-bit off-set constants
24
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Table 6–10: 8-bit FIR-coefficients (decimal integer) for MSP 3410D; reset status: all coefficients are “0”
Coefficients for FIR1 0001hex and FIR2 0005hex
Terrestrial TV-Standards
FM - Satellite
FIR filter corresponds to a
bandpass with a bandwidth of B = 130 to 500 kHz
B
fc
B/G-,D/K-,M-Dual FM
frequency
130 kHz
180 kHz
200 kHz
280 kHz
380 kHz
500 kHz
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
0
3
73
9
3
–8
–1
–1
75
1
18
53
18
18
–8
–9
–1
19
2
27
64
28
27
4
–16
–8
36
3
48
119
47
48
6
5
2
35
4
66
101
55
66
78
65
59
39
5
72
127
64
72
107
123
126
40
MODE-REG[12]
0
1
1
1
1
1
1
0
MODE-REG[13]
1
1
1
1
1
1
1
0
Coef(i)
Autosearch
MODE_REG[12] should be set to 0 (= 6 dB gain) if the level of the FM2-carrier processed in MSP-Ch1 is appr. 7 dB below the FM1-carrier of
MSP-Ch2. If both carriers have the same level, MODE_REG[12] must be set to 1 (=0 dB gain).
MODE_REG[13]: If in MSP-Channel 1 and 2 the same bandwidth is required, it is sufficient to transmit FIR_REG2 only and to set
MODE_REG[13] to 1.
For compatibility (besides the above programming), the FIR-filter programming as used for the MSP 3410B is also possible.
ADR coefficients are listed in the DRP-data sheet.
The 130 kHz coefficients are based on subcarriers, which are 7 dB below an existent main carrier.
MICRONAS INTERMETALL
25
MSP 3400C
PRELIMINARY DATA SHEET
6.2.5. DCO-Increments
For a chosen TV standard, a corresponding set of 24-bit
increments determining the mixing frequencies of the
quadrature mixers, has to be written into the IC. In Table
6–11, several examples of DCO increments are listed.
It is necessary to divide them into low part and high part.
The formula for the calculation of the increments for any
chosen IF-Frequency is as follows:
INCRdez = int(f/fs ⋅ 224)
with: int = integer function
f = IF-frequency in MHz
fS = sampling frequency (18.432 MHz)
Conversion of INCR into hex-format and separation of
the 12-bit low and high parts lead to the required increments. (DCO1_HI or _LO for channel 1, DCO2_HI or LO
for channel 2).
Table 6–11: DCO increments for the MSP 3400C; frequency in MHz, increments in Hex
Frq. MHz
DCO_HI
DCO_LO
Frq. MHz
DCO_HI
DCO_LO
4.5
03E8
0000
5.04
5.5
5.58
5.7421875
0460
04C6
04D8
04FC
0000
038E
0000
00AA
5.76
5.85
5.94
0500
0514
0528
0000
0000
0000
6.0
6.2
6.5
6.552
0535
0561
05A4
05B0
0555
0C71
071C
0000
6.6
6.65
6.8
05BA
05C5
05E7
0AAA
0C71
01C7
7.02
0618
0000
7.2
0640
0000
7.38
0668
0000
7.56
0690
0000
26
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
6.3. Sequences to Transmit Parameters and to Start
Processing
After having been switched on, the MSPC must be initialized by transmitting the parameters according to the
LOAD_SEQ_1/2 of Table 6–12. In the MSPC, the initialization sequence must no longer be terminated by transmitting LOAD_REG_1/2. The transmitted data are active as soon as the corresponding I2C telegram has
finished. Therefore, while changing parameters of the
demodulator section, a mute is recommended for the affected channel (LOAD_SEQ_1/2: mute all FM,
LOAD_SEQ_1: switch audio processing to channel2/FM1 or mute channel1/FM2). Otherwise, distorted
sound may occur while switching.
For FM-stereo operation, the evaluation of the identification signal must be performed. For positive identification
check, the MSP 3400C sound channels have to be
switched corresponding to the detected operation
mode.
6.4. Software Proposals for Multistandard TV-Sets
To familiarize the reader with the programming scheme
of the MSP 3400C, two examples in the shape of flow
diagrams are shown in the following sections.
6.4.1. Multistandard System B/G German DUAL FM
Fig. 6–1 shows a flow diagram for the CCU software,
applied for the MSP 3400C in a TV set, which facilitates
all standards according to System B/G. For the instructions used in the diagram, please refer to Table 6–12.
After having switched on the TV-set and having initialized the MSP 3400C (LOAD_SEQ_1/2), FM-mono
sound is available.
Fig. 6–1 shows how to check for any stereo or bilingual
audio information in channel 1. If successful, the
MSP 3400C must be switched to the desired audio
mode.
Table 6–12: Sequences to initialize and start the MSP 3400C
LOAD_SEQ_1/2: General Initialization
1. AD_CV
2. FIR_REG_1
3. FIR_REG_2
4. MODE_REG
5. DCO1_LO
6. DCO1_HI
7. DCO2_LO
8. DCO2_HI
FM_IDENT_CHECK: Decoding of the identification signal
1. Evaluation of the stereo detection register (DFP register 0018hex, high part)
2. If necessary, switch the corresponding sound channels within the audio processing part
LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2
1. FIR_REG_1
2. MODE_REG
3. DCO1_LO
4. DCO1_HI
MICRONAS INTERMETALL
(6 ⋅ 8 bit)
(12 bit)
(12 bit)
27
MSP 3400C
PRELIMINARY DATA SHEET
START
6.4.3. Automatic Search Function for FM-Carrier Detection
LOAD_SEQ_1/2
Channel 1:
FM2 Parameter
Channel 2:
FM1 Parameter
The AM demodulation ability of the MSP 3400C offers
the possibility to calculate the “field strength” of the momentarily selected FM carrier, which can be read out by
the CCU. In SAT receivers, this feature can be used to
make automatic FM carrier search possible.
Therefore, the MSPC has to be switched to AM-mode
(MODE_REG[8]), FM-Prescale must be set to
7Fhex=+127dez, and the FM DC Notch must be switched
off. The sound-IF frequency range must now be
“scanned” in the MSPC-channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz).
Audio Processing Init
Pause
Bilingual
Set FM Matrix:
To NO_MATRIX
Set Channel Matrix:
To SOUND A or B
< –t
FM_
IDENT_CHECK
0x0018
Mono
Set FM Matrix:
To NO_MATRIX > –t & < t
Set Channel Matrix:
To SOUNDA
Stereo
Set FM Matrix:
To G/KMATRIX
Set Channel Matrix:
To STEREO
>t
Fig. 6–1: CCU software flow diagram: Standard B/G,
t = threshold value for stereo/bilingual detection
START
LOAD_SEQ_1/2
MSP-Channel 1:
FM2-Parameter
MSP-Channel 2:
FM1-Parameter
Audio Processing Init
After each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to FM), which must be examined for relative maxima by the CCU. This results in
either continuing search or switching the MSP 3400C
back to FM demodulation mode.
During the search process, the FIR_REG_2 must be
loaded with the coefficient set “AUTOSEARCH”, which
enables small bandwidth, resulting in appropriate field
strength characteristics. The absolute field strength value (can be read out of “quasi peak detector output FM1”)
also gives information on whether a main FM carrier or
a subcarrier was detected, and as a practical consequence, the FM bandwidth (FIR_REG_1/2) and the
deemphasis (50 µs or adaptive) can be switched automatically.
Due to the fact that a constant demodulation frequency
offset of a few kHz, leads to a DC-level in the demodulated signal, a further fine tuning of the found carrier can
be achieved by evaluating the “DC Level Readout FM1”.
Therefore, the FM DC Notch must be switched on, and
the demodulator part must be switched back to FM-demodulation mode.
For a detailed description of the automatic search function, please refer to the corresponding MSP 3400C Windows software.
Note: The automatic search is still possible by evaluating only the DC Level Readout FM1 (DC Notch On) as
it is described with the MSP 3410, but the above mentioned method is faster.
STOP
Fig. 6–2: CCU software flow diagram: SAT-mode
6.4.2. Satellite Mode
Fig. 6–2 shows the simple flow diagram to be used for
the MSP 3400C in a satellite receiver. For FM-mono
operation, the corresponding FM carrier should preferably be processed at the MSPC-channel 2 or at the
MSPC-channel 1 with FIR gain = 0 dB.
28
6.4.4. Automatic Standard Detection
The AM demodulation ability of the MSP 3400 C enables a simple method of deciding between standard
B/G (FM-carrier at 5.5 MHz) and standard I (FM-carrier
at 6.0 MHz). It is achieved by tuning the MSP 3400C in
the AM-mode to the two discrete frequencies and evaluating the field strength via the DC level register or the
quasi-peak detector output (Mode_Reg, DC Notch, FM
Prescale as described in section 6.4.3.).
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
7. Programming the Audio Processing Part
7.1. Summary of the DSP Control Registers
Control registers are 16 bit wide. Transmissions via I2C
bus have to take place in 16 bit words. Single data entries are 8 bit. Some of the defined 16 bit words are divided into low and high byte, thus holding two different
control entities. All control registers are readable.
Note: Unused parts of the 16 bit registers must be zero.
Table 7–1: DSP Control Registers
Name
I2C Bus
Address
High/
Low
Adjustable Range, Operational Modes
Reset Mode
Volume loudspeaker channel
0000hex
H
[+12 dB ... –114 dB, MUTE]
MUTE
L
1/8 dB Steps, Reduce Volume / Tone Control
00hex
H
[0..100 / 100 % and vv][–127..0 / 0 dB and vv]
100%/100%
L
[Linear mode / logarithmic mode]
linear mode
Volume / Mode loudspeaker channel
Balance loudspeaker channel [L/R]
0001hex
Balance Mode loudspeaker
Bass loudspeaker channel
0002hex
H
[+20 dB ... –12 dB]
0 dB
Treble loudspeaker channel
0003hex
H
[+15 dB ... –12 dB]
0 dB
Loudness loudspeaker channel
0004hex
H
[0 dB ... +17 dB]
0 dB
L
[NORMAL, SUPER_BASS]
NORMAL
H
[–100%...OFF...+100%]
OFF
L
[SBE, SBE+PSE]
SBE+PSE
H
[+12 dB ... –114 dB, MUTE]
MUTE
L
1/8 dB Steps, Reduce Volume / Tone Control
00hex
H
[00hex ... 7Fhex],[+12 dB ... –114 dB, MUTE]
00hex
L
[Linear mode / logarithmic mode]
linear mode
H
[FM, NICAM, SCART, I2S1, I2S2]
FM
L
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
H
[FM, NICAM, SCART, I2S1, I2S2]
FM
L
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
H
[FM, NICAM, SCART, I2S1, I2S2]
FM
L
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
H
[FM, NICAM, SCART, I2S1, I2S2]
FM
Loudness Filter Characteristic
Spatial effect strength loudspeaker ch.
0005hex
Spatial effect mode/customize
Volume headphone channel
0006hex
Volume / Mode headphone channel
Volume SCART channel
0007hex
Volume / Mode SCART channel
Loudspeaker channel source
0008hex
Loudspeaker channel matrix
Headphone channel source
0009hex
Headphone channel matrix
SCART1 channel source
000ahex
SCART1 channel matrix
I2S channel source
000bhex
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
I2S channel matrix
Quasi-peak detector source
000chex
Quasi-peak detector matrix
L
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
H
[FM, NICAM, SCART, I2S1, I2S2]
FM
L
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
Prescale SCART
000dhex
H
[00hex ... 7Fhex]
00hex
Prescale FM
000ehex
H
[00hex ... 7Fhex]
00hex
L
[NO_MAT, GSTEREO, KSTEREO]
NO_MAT
FM matrix
MICRONAS INTERMETALL
29
MSP 3400C
PRELIMINARY DATA SHEET
Name
I2C Bus
Address
High/
Low
Adjustable Range, Operational Modes
Reset Mode
Deemphasis FM
000fhex
H
[OFF, 50 µs, 75 µs, J17]
50 µs
L
[OFF, WP1]
OFF
Adaptive Deemphasis FM
Prescale I2S2
0012hex
H
[00hex ... 7Fhex]
10hex
ACB Register (SCART Switches and
DIG_OUT Pins)
0013hex
H/L
Bits [15..0]
00hex
Beeper
0014hex
H/L
[00hex ... 7Fhex]/[00hex ... 7Fhex]
0/0
Identification Mode
0015hex
L
[B/G, M]
B/G
Prescale I2S1
0016hex
H
[00hex ... 7Fhex]
10hex
FM DC Notch
0017hex
L
[ON, OFF]
ON
Mode Tone Control
0020hex
H
[BASS/TREBLE, EQUALIZER]
BASS/TREB
Equalizer loudspeaker ch. band 1
0021hex
H
[+12 dB ... –12 dB]
0 dB
Equalizer loudspeaker ch. band 2
0022hex
H
[+12 dB ... –12 dB]
0 dB
Equalizer loudspeaker ch. band 3
0023hex
H
[+12 dB ... –12 dB]
0 dB
Equalizer loudspeaker ch. band 4
0024hex
H
[+12 dB ... –12 dB]
0 dB
Equalizer loudspeaker ch. band 5
0025hex
H
[+12 dB ... –12 dB]
0 dB
Automatic Volume Correction
0029hex
H
[off, on, decay time]
off
Volume Subwoofer channel
002Chex
H
[0dB ... –30 dB, mute]
0 dB
Subwoofer Channel Corner Frequency
002Dhex
H
[50 Hz ... 400 Hz]
L
[off, on]
off
H
[0...100 / 100% and vv][–127...0 / 0 dB and vv]
100%/100%
L
[Linear mode / logarithmic mode]
linear mode
Subwoofer: Complementary Highpass
Balance headphone channel [L/R]
0030hex
Balance Mode headphone
Bass headphone channel
0031hex
H
[+20 dB ... –12 dB]
0 dB
Treble headphone channel
0032hex
H
[+15 dB ... –12 dB]
0 dB
Loudness headphone channel
0033hex
H
[0 dB ... +17 dB]
0 dB
L
[NORMAL, SUPER_BASS]
NORMAL
Loudness filter characteristic
Note: For compatibility to new technical codes of the MSP 3400C, please consider the following compatibility restrictions:
If adaptive deemphasis is switched on, 75 µs deemphasis must be activated.
30
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
7.1.1. Volume Loudspeaker Channel and Headphone Channel
Clipping Mode
loudspeaker
0000hex
3 LSBs
Volume
loudspeaker
0000hex
11 MSBs
Clipping Mode
headphone
0006hex
3 LSBs
Volume
headphone
0006hex
11 MSBs
Reduce Volume
x000
RESET
0hex
+12 dB
0111 1111 000x
7F0hex
Reduce Tone Control
x001
1hex
+11.875 dB
0111 1110 111x
7EEhex
Compromise Mode
x010
2hex
+0.125 dB
0111 0011 001x
732hex
0 dB
0111 0011 000x
730hex
–0.125 dB
0111 0010 111x
72Ehex
–113.875dB
0000 0001 001x 012hex
–114 dB
0000 0001 000x 010hex
Mute
0000 0000 xxxx 00xhex
RESET
Fast Mute
1111 1111 111x
FFEhex
The highest given positive 11-bit number (7F0hex) yields
in a maximum possible gain of 12 dB. Decreasing the
volume register by 1 LSB decreases the volume by
0.125 dB. Volume settings lower than the given minimum mute the output. With large scale input signals,
positive volume settings may lead to signal clipping.
With Fast Mute, volume is reduced to mute position by
digital volume only. Analog volume is not changed. This
reduces any audible DC plops. Going back from Fast
Mute should be done to the volume step before Fast
Mute was activated.
MICRONAS INTERMETALL
If the clipping mode is set to “Reduce Volume”, the following clipping procedure is used: To prevent severe
clipping effects with bass, treble, or equalizer boosts, the
internal volume is automatically limited to a level where,
in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB.
If the clipping mode is “Reduce Tone Control”, the bass
or treble value is reduced if amplification exceeds 12 dB.
If the equalizer is switched on, the gain of those bands
is reduced, where amplification together with volume exceeds 12 dB.
If the clipping mode is “Compromise Mode”, the bass or
treble value and volume are reduced half and half if amplification exceeds 12 dB (see example below). If the
equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with
volume exceeds 12 dB.
Example:
Vol.:
+6 dB
Bass:
+9 dB
Treble:
+5 dB
Red. Volume
3
9
5
Red. Tone Con.
6
6
5
Compromise
4.5
7.5
5
31
MSP 3400C
7.1.2. Balance
Channel
PRELIMINARY DATA SHEET
Loudspeaker
and
Headphone
Positive balance settings reduce the left channel without
affecting the right channel; negative settings reduce the
right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the
balance by about 0.8% (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases
the balance by 1 dB.
Balance Mode
loudspeaker
0001hex
LSB
Balance Mode
headphone
0030hex
linear
xxx0
RESET
0hex
logarithmic
xxx1
1hex
Balance loudspeaker
channel [L/R]
0001hex
H
Balance headphone
channel [L/R]
0030hex
H
Left muted, Right 100%
0111 1111
7Fhex
Left 0.8%, Right 100%
0111 1110
7Ehex
Left 99.2%, Right 100%
0000 0001
01hex
Left 100%, Right 100%
0000 0000
RESET
00hex
Left 100%, Right 99.2%
1111 1111
FFhex
Left 100%, Right 0.8%
1000 0010
82hex
Left 100%, Right muted
1000 0001
81hex
Logarithmic Mode
Balance loudspeaker
channel [L/R]
0001hex
H
Balance headphone
channel [L/R]
0030hex
H
Left –127 dB, Right 0 dB
0111 1111
7Fhex
Left –126 dB, Right 0 dB
0111 1110
7Ehex
Left –1 dB, Right 0 dB
0000 0001
01hex
Left 0 dB, Right 0 dB
0000 0000
RESET
00hex
Left 0 dB, Right –1 dB
1111 1111
FFhex
Left 0 dB, Right –127 dB
1000 0001
81hex
Left 0 dB, Right –128 dB
1000 0000
80hex
LSB
Linear Mode
32
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
7.1.3. Bass Loudspeaker and Headphone Channel
7.1.4. Treble Loudspeaker and Headphone Channel
Bass loudspeaker
0002hex
H
Treble loudspeaker
0003hex
H
Bass headphone
0031hex
H
Treble headphone
0032hex
H
+20 dB
0111 1111
7Fhex
+15 dB
0111 1000
78hex
+18 dB
0111 1000
78hex
+14 dB
0111 0000
70hex
+16 dB
0111 0000
70hex
+1 dB
0000 1000
08hex
+14 dB
0110 1000
68hex
+1/8 dB
0000 0001
01hex
+12 dB
0110 0000
60hex
0 dB
00hex
+11 dB
0101 1000
58hex
0000 0000
RESET
+1 dB
0000 1000
08hex
–1/8 dB
1111 1111
FFhex
+1/8 dB
0000 0001
01hex
–1 dB
1111 1000
F8hex
0 dB
0000 0000
RESET
00hex
–11 dB
1010 1000
A8hex
–12 dB
1010 0000
A0hex
–1/8 dB
1111 1111
FFhex
–1 dB
1111 1000
F8hex
–11 dB
1010 1000
A8hex
–12 dB
1010 0000
A0hex
With positive bass settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with
volume, would result in an overall positive gain.
With positive treble settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with
volume, would result in an overall positive gain.
Loudspeaker channel: Treble and Equalizer cannot
work simultaneously (see Table: Mode Tone Control). If
Equalizer is used, Bass and Treble coefficients must be
set to zero and vice versa.
Loudspeaker channel: Bass and Equalizer cannot work
simultaneously (see Table: Mode Tone Control). If
Equalizer is used, Bass and Treble coefficients must be
set to zero and vice versa.
MICRONAS INTERMETALL
33
MSP 3400C
7.1.5. Loudness
Channel
PRELIMINARY DATA SHEET
Loudspeaker
and
Headphone
7.1.6. Spatial Effects Loudspeaker Channel
Spatial effect strength
loudspeaker channel
0005hex
H
Enlargement 100%
0111 1111
7Fhex
Enlargement 50%
0011 1111
3Fhex
44hex
Enlargement 1.5%
0000 0001
01hex
0100 0000
40hex
Effect off
0000 0000
RESET
00hex
+1 dB
0000 0100
04hex
Reduction 1.5%
1111 1111
FFhex
0 dB
0000 0000
RESET
00hex
Reduction 50%
1100 0000
C0hex
Reduction 100%
1000 0000
80hex
L
Spatial Effect Mode
0005hex
[7:4]
Stereo Basewidth Enlargement (SBE) and
Pseudo Stereo Effect
(PSE). (Mode A)
0000
RESET
0000
0hex
Stereo Basewidth Enlargement (SBE) only.
(Mode B)
0010
2hex
Spatial Effect Customize Coefficient
0005hex
[3:0]
Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has
to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended
to set loudness to a value that ,in conjunction with volume, would result in an overall positive gain.
max high pass gain
0000
RESET
0hex
2/3 high pass gain
0010
2hex
1/3 high pass gain
0100
4hex
min high pass gain
0110
6hex
By means of ‘Mode Loudness’, the corner frequency for
bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up.
The point of constant volume is shifted from 1 kHz to
2 kHz.
automatic
1000
8hex
Loudness
loudspeaker
0004hex
H
Loudness
headphone
0033hex
H
+17 dB
0100 0100
+16 dB
Mode Loudness
loudspeaker
0004hex
Mode Loudness
headphone
0033hex
L
Normal (constant
volume at 1 kHz)
0000 0000
RESET
00hex
Super Bass (constant
volume at 2 kHz)
0000 0100
04hex
0hex
There are several spatial effect modes available:
Mode A (low byte = 00hex) is compatible to the formerly
used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in
mono mode, Pseudo Stereo Effect is active; for stereo
signals, Pseudo Stereo Effect and Stereo Basewidth
Enlargement is effective. The strength of the effect is
controllable by the upper byte. A negative value reduces
the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is
rather close. For large screen TV sets, a more moderate
spatial effect is recommended. In mode A, even in case
of stereo input signals, Pseudo Stereo Effect is active,
which reduces the center image.
In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect
has to be switched on.
34
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin
yields a flat response for center signals (L = R) but a high
pass function of L or R only signals. A value of 0110bin
has a flat response for L or R only signals but a lowpass
function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound
material by choosing an optimal high pass gain.
7.1.7. Volume SCART
7.1.8. Channel Source Modes
Loudspeaker channel
source
0008hex
H
Headphone channel
source
0009hex
H
SCART channel
source
000ahex
H
I2S channel source
000bhex
H
Volume Mode SCART
0007hex
LSB
Quasi-peak detector
source
000chex
H
linear
xxx0
RESET
0hex
FM
0000 0000
RESET
00hex
logarithmic
xxx1
1hex
NONE (MSP3410: NICAM)
0000 0001
01hex
SCART
0000 0010
02hex
SBUS12
0000 0011
03hex
Linear Mode
Volume SCART
0007hex
H
SBUS34
0000 0100
04hex
OFF
0000 0000
RESET
00hex
I2S1
0000 0101
05hex
I2S2
0000 0110
06hex
0 dB gain
(digital full scale (FS)
to 2 VRMS output)
0100 0000
40hex
+6 dB gain (–6 dBFS
to 2 VRMS output)
0111 1111
7Fhex
Note: For Headphone output it is also possible to select
a subwoofer signal derived from the Loudspeaker channel. For more details see section 7.1.23.
Logarithmic Mode
Volume SCART
0007hex
+12 dB
0111 1111 000x
7F0hex
+11.875 dB
0111 1110 111x
7EEhex
+0.125 dB
0111 0011 001x
732hex
0 dB
0111 0011 000x
730hex
–0.125 dB
0111 0010 111x
72Ehex
–113.875 dB
0000 0001 001x 012hex
–114 dB
0000 0001 000x 010hex
Mute
0000 0000 0000 000hex
RESET
MICRONAS INTERMETALL
11 MSBs
35
MSP 3400C
PRELIMINARY DATA SHEET
7.1.9. Channel Matrix Modes (see also Table 4–1)
Loudspeaker channel
matrix
0008hex
L
Volume Prescale FM
(normal FM mode)
000ehex
H
Headphone channel
matrix
0009hex
L
OFF
0000 0000
RESET
00hex
SCART channel
matrix
000ahex
L
0111 1111
7Fhex
I2S channel matrix
000bhex
L
Maximum Volume
(28 kHz deviation 1)
recommended FIRbandwidth: 130 kHz)
Quasi-peak detectormatrix
000chex
L
0100 1000
48hex
SOUNDA / LEFT /
MSP-IF-CHANNEL2
0000 0000
RESET
00hex
Deviation 50 kHz1)
recommended FIRbandwidth: 200 kHz
0011 0000
30hex
SOUNDB / RIGHT /
MSP-IF-CHANNEL1
0001 0000
10hex
Deviation 75 kHz1)
recommended FIRbandwidth: 200 or
280 kHz
STEREO
0010 0000
20hex
0001 1000
18hex
MONO
0011 0000
30hex
Deviation 150 kHz1)
recommended FIRbandwidth: 380 kHz
SUM/DIFF
0100 0000
40hex
0001 0011
13hex
AB_XCHANGE
0101 0000
50hex
INVERT_B
0110 0000
60hex
Maximum deviation
192 kHz1)
recommended FIRbandwidth: 380 kHz
Prescale for adaptive
deemphasis WP1
recommended FIRbandwidth: 130 kHz
0001 0000
10hex
Volume Prescale FM
(High Deviation
Mode)
000ehex
H
Deviation 150 kHz1)
recommended FIRbandwidth: 380 kHz
0011 0000
30hex
Maximum deviation
384 kHz1)
recommended FIRbandwidth: 500 kHz
0001 0011
13hex
The sum/difference mode can be used together with the
quasi-peak detector to determine the sound material
mode. If the difference signal on channel B (right) is near
to zero, and the sum signal on channel A (left) is high,
the incoming audio signal is mono. If there is a significant
level on the difference signal, the incoming audio is stereo.
7.1.10. SCART Prescale
36
7.1.11. FM Prescale
Volume Prescale
SCART
000dhex
H
OFF
0000 0000
RESET
00hex
0 dB gain (2 VRMS input to digital full scale)
0001 1001
19hex
+14 dB gain
(400 mVRMS input to
digital full scale)
0111 1111
7Fhex
For the High Deviation Mode, the FM prescaling values
can be used in the range between 13hex to 30hex. Please
consider the internal reduction of 6 dB for this mode. The
FIR-bandwidth should be selected to 500 kHz.
1) Given
deviations will result in internal digital full scale
signals. Appropriate clipping headroom has to be set by
the customer. This can be done by decreasing the listed
values by a specific factor.
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
7.1.12. FM Matrix Modes (see also Table 4–1)
7.1.15. I2S1 and I2S2 Prescale
FM matrix
000ehex
L
Prescale I2S1
0016hex
H
NO MATRIX
0000 0000
RESET
00hex
Prescale I2S2
0012hex
H
OFF
GSTEREO
0000 0001
01hex
00hex
0 dB gain
KSTEREO
0000 0010
02hex
10hex
RESET
+18 dB gain
7Fhex
NO_MATRIX is used for terrestrial mono or satellite stereo sound. GSTEREO dematrixes (L+R, 2R) to (2L, 2R)
and is used for German dual carrier stereo system
(Standard B/G). KSTEREO dematrixes (L+R, L–R) to
(2L, 2R) and is used for the Korean dual carrier stereo
system (Standard M).
7.1.13. FM Fixed Deemphasis
Deemphasis FM
000fhex
H
50 µs
0000 0000
RESET
00hex
75 µs
0000 0001
01hex
J17
0000 0100
04hex
OFF
0011 1111
3Fhex
7.1.14. FM Adaptive Deemphasis
FM Adaptive
Deemphasis WP1
000fhex
L
OFF
0000 0000
RESET
00hex
WP1
0011 1111
3Fhex
Must be set to ‘OFF’ in case of dual carrier stereo (German or Korean). If ‘ON’, FM fixed deemphasis must be
set to 75 µs.
MICRONAS INTERMETALL
7.1.16. ACB Register, Definition of the SCARTSwitches and DIG_CTR_OUT Pins
ACB Register
0013hex
H
DSP In
Selection of Source:
SC_1_IN
MONO_IN
SC_2_IN
SC_3_IN
xxxx
xxxx
xxxx
xxxx
xx00
xx01
xx10
xx11
RESET
SC_1_OUT_L/R
Selection of Source:
SC_3_IN
SC_2_IN
MONO_IN
DA_SCART
xxxx
xxxx
xxxx
xxxx
00xx
01xx
10xx
11xx
RESET
SC_2_OUT_L/R
Selection of Source:
DA_SCART
SC_1_IN
MONO_IN
xx00 xxxx
xx01 xxxx
xx10 xxxx
RESET
DIG_CTR_OUT1
low
high
x0xx xxxx
x1xx xxxx
RESET
DIG_CTR_OUT2
low
high
0xxx xxxx
1xxx xxxx
RESET
RESET: The RESET state is taken at the time of
the first write transmission on the control bus to
the audio processing part (DSP). By writing to the
ACB register first, the RESET state can be redefined.
37
MSP 3400C
PRELIMINARY DATA SHEET
7.1.17. Beeper
7.1.19. FM DC Notch
Beeper Volume
0014hex
H
FM DC Notch
0017hex
L
OFF
0000 0000
RESET
00hex
ON
0000 0000
Reset
00hex
Maximum Volume (full
digital scale FDS)
0111 1111
7Fhex
OFF
0011 1111
3Fhex
Beeper Frequency
0014hex
L
16 Hz (lowest)
0000 0001
01hex
1 kHz
0100 0000
40hex
4 kHz (highest)
1111 1111
FFhex
A squarewave beeper can be added to the loudspeaker
channel and the headphone channel. The addition point
is just before loudness and volume adjustment.
7.1.18. Identification Mode
Identification Mode
0015hex
L
Standard B/G (German
Stereo)
0000 0000
RESET
00hex
Standard M (Korean
Stereo)
0000 0001
01hex
Reset of Ident-Filter
0011 1111
3Fhex
The DC compensation filter (FM DC Notch) for FM input
can be switched off. This is used to speed up the automatic search function (see sector 6.4.3.). In normal FMmode, the FM DC Notch should be switched on.
7.1.20. Mode Tone Control
Mode Tone Control
00020hex
H
Bass and Treble
0000 0000
RESET
00hex
Equalizer
1111 1111
FFhex
By means of ‘Mode Tone Control’, Bass/Treble or Equalizer may be activated.
To shorten the response time of the identification algorithm after a program change between two FM-stereo
capable programs, the reset of ident-filter can be applied.
Sequence:
1. Program change
2. Reset ident-filter
3. Wait at least 1 msec.
4. Set identification mode back to standard B/G or M
5. Wait approx. 1 sec.
6. Read stereo detection register
38
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
7.1.21. Equalizer Loudspeaker Channel
Band 1 (below 120 Hz)
0021hex
H
Band 2 (Center: 500 Hz)
0022hex
H
Band 3 (Center: 1.5 kHz)
0023hex
H
Band 4 (Center: 5 kHz)
0024hex
H
Band 5 (above 10kHz)
0025hex
H
+12 dB
0110 0000
60hex
+11 dB
0101 1000
58hex
+1 dB
0000 1000
08hex
+1/8 dB
0000 0001
01hex
0 dB
0000 0000
RESET
00hex
–1/8 dB
1111 1111
FFhex
–1 dB
1111 1000
F8hex
–11dB
1010 1000
A8hex
–12 dB
1010 0000
A0hex
With positive equalizer settings, internal overflow may
occur even with overall volume less than 0 dB. This will
lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive
gain.
Equalizer must not be used simultaneously with Bass
and Treble (Mode Tone Control must be set to FF to use
the Equalizer).
The absolute value of the incoming signal is fed into a
filter with 16ms attack time and selectable decay time.
The decay time must be adjusted as shown in the table
above. This attack/decay filter block works similar to a
peak hold function. The volume correction value with it’s
quasi continuous step width is calculated using the attack/decay filter output.
The Automatic Volume Correction works with an internal
reference level of –18 dBFS. This means, input signals
with a volume level of –18 dBFS will not be affected by
the AVC. If the input signals vary in a range of –24 dB to
0 dB the AVC compensates this.
Example: A static input signal of 1 kHz on Scart has an
output level as shown in the table below.
Scart Input
0dbr = 2 Vrms
Volume
Correction
Main Output
0dBr = 1.4 Vrms
0 dBr
–18 dB
–18 dBr
–6 dBr
–12 dB
–18 dBr
–12 dBr
–6 dB
–18 dBr
–18 dBr
–0 dB
–18 dBr
–24 dBr
+ 6 dB
–18 dBr
–30 dBr
+ 6 dB
–24 dBr
Loudspeaker Volume = 73h = 0 dBFS
Scart Prescale = 20h i.e. 2.0 Vrms = 0dBFS
7.1.22. Automatic Volume Correction (AVC)
AVC
on/off
0029hex
[15:12]
AVC
off and Reset
of int. variables
0000
RESET
0hex
AVC
on
1000
8hex
AVC
Decay Time
0029hex
[11:8]
8 sec
4 sec
2 sec
20 ms
(long)
(middle)
(short)
(very short)
1000
0100
0010
0001
8hex
4hex
2hex
1hex
MICRONAS INTERMETALL
Different sound sources (e.g. Terrestrial channels, SAT
channels or SCART) fairly often don’t have the same
volume level. Advertisement during movies as well has
mostly a different (higher) volume level, than the movie
itself. The Automatic Volume Correction (AVC) solves
this problem and equalizes the volume levels.
To reset the internal variables, the AVC should be
switched off and on during any channel or source
change. For standard applications, the recommended
decay time is 4sec.
Note: AVC should not be used in any Dolby Prologic
modes, except PANORAMA, where no other than the
loudspeaker output is active.
39
MSP 3400C
PRELIMINARY DATA SHEET
7.1.23. Subwoofer on Headphone Output
7.2. Exclusions
The subwoofer channel is created by combining the left
and right loudspeaker channels ( (L+R)/2 ) directly behind the tone control filter block. A third order lowpass filter with programmable corner frequency and volume adjustment respectively to the loudspeaker channel output
is performed to the bass-signal. Additionally, at the loudspeaker channels, a complementary high pass filter can
be switched on. The subwoofer channel output can be
switched to the headphone D/A converter alternatively
with the headphone output.
In general, all functions can be switched independently
of the others. One exception exists:
Subwoofer Channel
Volume Adjust
002Chex
H
0 dB
0000 0000
RESET
00hex
–1 dB
1111 1111
FFhex
–29 dB
1110 0011
E3hex
–30 dB
1110 0010
E2hex
Mute
1000 0000
80hex
Subwoofer Channel
Corner Frequency
002Dhex
H
50 Hz .... 400 Hz
e.g. 50 Hz
= 5 int
400 Hz = 40int
0000 0101
0010 1000
05hex
28hex
Headphone Output
002Dhex
[7:4]
Headphone
0000
0hex
Subwoofer
1000
8hex
Subwoofer: Complementary Highpass
002Dhex
[3:0]
HP off
0000
0hex
HP on
0001
1hex
1. If the adaptive deemphasis is activated (Reg. 000fhex
L), the FM fixed deemphasis (Reg. 000fhex H) must be
set to 75 µs.
Note: If subwoofer is chosen for headphone output, the
corner frequency must be set to the desired value, before the loudspeaker volume is set. This is to avoid plop
noise.
40
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
7.3. Summary of Readable Registers
All readable registers are 16 bit wide. Transmissions via
I2C bus have to take place in 16 bit words. Single data
entries are 8 bit. Some of the defined 16 bit words are
divided into low and high byte, thus holding two different
control entities.
These registers are not writeable.
Name
Address
High/Low
Output Range
Stereo detection register
0018hex
H
[80hex ... 7Fhex]
8 bit two’s complement
Quasi peak readout left
0019hex
H&L
[00hex ... 7FFFhex]
16 bit binary
Quasi peak readout right
001ahex
H&L
[00hex ... 7FFFhex]
16 bit binary
DC level readout FM1/Ch2–L
001bhex
H&L
[00hex ... 7FFFhex]
16 bit binary
DC level readout FM2/Ch1–R
001chex
H&L
[00hex ... 7FFFhex]
16 bit binary
MSP hardware version code
001ehex
H
[00hex ... FFhex]
L
[00hex ... FFhex]
H
[00hex ... 0Ahex]
L
[00hex ... FFhex]
MSP major revision code
MSP product code
001fhex
MSP ROM version code
7.3.1. Stereo Detection Register
Stereo Detection
Register
0018hex
Stereo Mode
7.3.2. Quasi Peak Detector
Quasi peak readout
left
0019hex
H+L
Reading
(two’s complement)
Quasi peak readout
right
001ahex
H+L
MONO
near zero
Quasi peak readout
[0hex ... 7FFFhex]
values are 16 bit binary
STEREO
positive value (ideal
reception: 7Fhex)
BILINGUAL
H
negative value (ideal
reception: 80hex)
The quasi peak readout register can be used to read out
the quasi peak level of any input source, in order to adjust all inputs to the same normalized listening level. The
refresh rate is 32 kHz. The feature is based on a filter
time constant:
attack-time: 1.3 ms
decay-time: 37 ms
MICRONAS INTERMETALL
41
MSP 3400C
PRELIMINARY DATA SHEET
7.3.3. DC Level Register
7.3.6. MSP Product Code
DC level readout FM1
001bhex
H+L
Product
001fhex
H
DC level readout FM2
001chex
H+L
MSP 3400C
0000 0000
00hex
DC Level
[0hex ... 7FFFhex]
values are 16 bit binary
MSP 3400
0000 1010
0Ahex1)
MSP 3410
0000 1010
0Ahex
The DC level register measures the DC component of
the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
FM frequencies fine tuning. For further processing, the
DC content of the demodulated FM signals is suppressed. The time constant τ, defining the transition time
of the DC Level Register, is approximately 28 ms.
7.3.4. MSP Hardware Version Code
Hardware Version
001ehex
Hardware Version
[00hex ... FFhex]
MSP 3400C – C8
03hex
H
A change in the hardware version code defines hardware optimizations that may have influence on the chip’s
behavior. The readout of this register is identical to the
hardware version code in the chip’s imprint.
7.3.5. MSP Major Revision Code
Major Revision
001ehex
MSP 3400C
03hex
L
1)
Note: The MSP 3400 hardware is identical to the
MSP 3410. Therefore, the family code readout will show
‘MSP 3410’ instead of its label ‘MSP 3400’.
7.3.7. MSP ROM Version Code
ROM Version
001fhex
L
Major software revision
[00hex ... FFhex]
MSP 3400C – B5
0000 0101
05hex
MSP 3400C – C6
0000 0110
06hex
MSP 3400C – C8
0000 1000
08hex
A change in the ROM version code defines internal software optimizations, that may have influence on the
chip’s behavior, e.g. new features may have been included. While a software change is intended to create no
compatibility problems, customers that want to use the
new functions can identify new MSP 3400C versions according to this number. The readout of this register is
identical to the ROM version code in the chip’s imprint.
The MSP 3400C is the third generation of ICs in the MSP
family.
42
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
8. Specifications
8.1. Outline Dimensions
60
2
2
24.2 ±0.1
23.4
25 +0.25
0.711
9
15
26
0.2
9
44
27
1.9 1.5
43
4.05
25 +0.25
4.75 ±0.15
24.2 ±0.1
0.1
SPGS7004-3/4E
Fig. 8–1:
68-Pin Plastic Leaded Chip Carrier Package
(PLCC68)
Weight approximately 4.8 g
Dimensions in mm
SPGS0015-1/2E
SPGS0016-4/2E
33
1
32
27
1
26
15.6 ±0.1
14 ±0.1
0.3
47 ±0.1
0.4 ±0.2
4 ±0.1
0.3
3.8 ±0.1
19.3 ±0.1
18 ±0.1
4.8 ±0.4
3.2 ±0.4
1.9
(1)
57.7 ±0.1
31 x 1.778 = 55.118 ±0.1
Fig. 8–2:
64-Pin Plastic Shrink Dual Inline Package
(PSDIP64)
Weight approximately 9.0 g
Dimensions in mm
MICRONAS INTERMETALL
1 ±0.1
0.457
1.778 ±0.05
25 x 1.778 = 44.47 ±0.1
0.24
20.1 ±0.6
3.2 ±0.2
0.457
0.3
0.27 ±0.06
1 ±0.1
1.778 ±0.05
1.29
52
3
2.5
64
16 x 1.27 ± 0.1 = 20.32 ± 0.1
10
2.4
61
1.27 ± 0.1
1
16 x 1.27 ± 0.1 = 20.32 ± 0.1
1.27 ± 0.1
1.2 x 45°
0.457
9
2.4
0.9
1+0.2 x 45 °
0.27 ±0.06
0°...15°
Fig. 8–3:
52-Pin Plastic Shrink Dual In Line Package
(PSDIP52)
Weight approximately 5.5 g
Dimensions in mm
43
MSP 3400C
PRELIMINARY DATA SHEET
23 x 0.8 = 18.4
0.8
0.17 ±0.03
64
41
14
17.2
8
1.8
10.3
9.8
5
16
80
0.8
8
1.8
15 x 0.8 = 12.0
40
65
25
1
1.28
24
2.70
23.2
3 ±0.2
20
0.1
Fig. 8–4:
80-Pin Plastic Quad Flat Pack Package
(PQFP80)
Weight approximately 1.61 g
Dimensions in mm
SPGS0025-1/1E
8.2. Pin Connections and Short Descriptions
AHVSS = connect to AHVSS
DVSS = if not used, connect to DVSS
–
= pin does not exist in this package
NC = not connected; leave vacant
LV = if not used, leave vacant
X = obligatory; connect as described
in circuit diagram
Pin No.
PLCC
68-pin
PSDIP
52-pin
Pin Name
PQFP
80-pin
Type
3410D in ( )
1
16
14
9
S_ID
(ADR_WS)
2
–
–
–
NC
3
15
13
8
S_DA_IN
(ADR_DA)
4
14
12
7
5
13
11
6
12
7
Connection
Short Description
(if not used)
LV
SBUS Ident or ADR
wordstrobe1)
LV
Not connected
OUT
LV
SBUS Data input or ADR
data output1)
I2S_DA_IN1
IN
LV
I2S1 data input
6
I2S_DA_OUT
OUT
LV
I2S data output
10
5
I2S_WS
IN/OUT
LV
I2S wordstrobe
11
9
4
I2S_CL
IN/OUT
LV
I2S clock
8
10
8
3
I2C_DA
IN/OUT
X
I2C data
9
9
7
2
I2C_CL
IN/OUT
X
I2C clock
10
8
–
1
NC
LV
Not connected
11
7
6
80
STANDBYQ
IN
X
Standby (low-active)
12
6
5
79
ADR_SEL
IN
X
I2C Bus address select
1)
2)
44
PSDIP
64-pin
OUT
Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).
Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Pin No.
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
Pin Name
PQFP
80-pin
Type
3410D in ( )
Connection
Short Description
(if not used)
13
5
4
78
D_CTR_OUT0
OUT
LV
Digital control output 0
14
4
3
77
D_CTR_OUT1
OUT
LV
Digital control output 1
15
3
–
76
NC
LV
Not connected
16
2
–
–
NC
LV
Not connected
17
–
–
75
NC
LV
Not connected
18
1
2
74
AUD_CL_OUT
OUT
LV
Audio clock output
19
64
1
73
DMA_SYNC
IN
LV
DMA-Sync. Input
20
63
52
72
XTAL_OUT
OUT
X
Crystal oscillator
21
62
51
71
XTAL_IN
IN
X
Crystal oscillator
22
61
50
70
TESTEN
IN
X
Test pin
23
60
49
69
ANA_IN2+
IN
LV
IF input 2 (if ANA_IN1+ is
used only, connect to
AVSS with 50 pF capacitor)
24
59
48
68
ANA_IN–
IN
LV
IF common
25
58
47
67
ANA_IN1+
IN
LV
IF input 1
26
57
46
66
AVSUP
X
Analog power supply +5 V
–
–
–
65
AVSUP
X
Analog power supply +5 V
–
–
–
64
NC
LV
Not connected
–
–
–
63
NC
LV
Not connected
27
56
45
62
AVSS
X
Analog ground
–
–
–
61
AVSS
X
Analog ground
28
55
44
60
MONO_IN
LV
Mono input
–
–
–
59
NC
LV
Not connected
29
54
43
58
VREFTOP
X
Reference voltage IF A/D
converter
30
53
42
57
SC1_IN_R
IN
LV
Scart input 1 in, right
31
52
41
56
SC1_IN_L
IN
LV
Scart input 1 in, left
32
51
–
55
ASG1
AHVSS
Analog Shield Ground 1
33
50
40
54
SC2_IN_R
IN
LV
Scart input 2 in, right
34
49
39
53
SC2_IN_L
IN
LV
Scart input 2 in, left
1)
2)
IN
Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).
Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.
MICRONAS INTERMETALL
45
MSP 3400C
PRELIMINARY DATA SHEET
Pin No.
PLCC
68-pin
PSDIP
52-pin
Pin Name
PQFP
80-pin
Type
3410D in ( )
35
48
–
52
ASG2
36
47
38
51
SC3_IN_R
37
46
37
50
SC3_IN_L
38
45
–
49
39
44
–
40
43
41
Connection
Short Description
(if not used)
AHVSS
Analog Shield Ground 2
IN
LV
Scart input 3 in, right
IN
LV
Scart input 3 in, left
NC (ASG4)
LV
Not connected
48
NC
(SC4_IN_R)
LV
Not connected
–
47
NC
(SC4_IN_L)
LV
Not connected
–
–
46
NC
LV or
AHVSS
Not connected
42
42
36
45
AGNDC
X
Analog reference voltage
high voltage part
43
41
35
44
AHVSS
X
Analog ground
–
–
–
43
AHVSS
X
Analog ground
–
–
–
42
NC
LV
Not connected
–
–
–
41
NC
LV
Not connected
44
40
34
40
CAPL_M
X
Volume capacitor MAIN
45
39
33
39
AHVSUP
X
Analog power supply
8.0 V
46
38
32
38
CAPL_A
X
Volume capacitor AUX
47
37
31
37
SC1_OUT_L
OUT
LV
Scart output 1, left
48
36
30
36
SC1_OUT_R
OUT
LV
Scart output 1, right
49
35
29
35
VREF1
X
Reference ground 1 high
voltage part
50
34
28
34
SC2_OUT_L
OUT
LV
Scart output 2, left
51
33
27
33
SC2_OUT_R
OUT
LV
Scart output 2, right
52
–
–
32
ASG3
AHVSS2)
Analog Shield Ground 3
53
32
–
31
NC
LV
Not connected
54
31
26
30
NC
(DACM_SUB)
LV
Not connected
55
30
–
29
NC
LV
Not connected
56
29
25
28
DACM_L
LV
Analog output MAIN, left
1)
2)
46
PSDIP
64-pin
OUT
Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).
Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Pin No.
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
Pin Name
PQFP
80-pin
Type
3410D in ( )
57
28
24
27
DACM_R
58
27
23
26
VREF2
59
26
22
25
DACA_L
60
25
21
24
DACA_R
–
–
–
23
–
–
–
61
24
62
Connection
Short Description
(if not used)
LV
Analog output MAIN,
right
X
Reference ground 2 high
voltage part
OUT
LV
Analog output AUX, left
OUT
LV
Analog output AUX, right
NC
LV
Not connected
22
NC
LV
Not connected
20
21
RESETQ
X
Power-on-reset
23
–
20
NC
LV
Not connected
63
22
–
19
NC
LV
Not connected
64
21
19
18
NC
LV
Not connected
65
20
18
17
I2S_DA_IN2
LV
I2S2-data input
66
19
17
16
DVSS
X
Digital ground
–
–
–
15
DVSS
X
Digital ground
–
–
–
14
DVSS
X
Digital ground
67
18
16
13
DVSUP
X
Digital power supply +5 V
–
–
–
12
DVSUP
X
Digital power supply +5 V
–
–
–
11
DVSUP
X
Digital power supply +5 V
68
17
15
10
S_CL
(ADR_CL)
LV
SBUS clock or ADR
clock1)
1)
2)
OUT
IN
IN
OUT
Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).
Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.
MICRONAS INTERMETALL
47
MSP 3400C
PRELIMINARY DATA SHEET
8.3. Pin Configurations
S_ID
NC
S_CL
S_DA_IN
DVSUP
I2S_DA_IN1
DVSS
I2S_DA_OUT
I2S_DA_IN2
I2S_WS
NC
I2S_CL
NC
I2C_DA
NC
I2C_CL
RESETQ
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
NC
10
60
DACA_R
STANDBYQ
11
59
DACA_L
ADR_SEL
12
58
VREF2
D_CTR_OUT0
13
57
DACM_R
D_CTR_OUT1
14
56
DACM_L
NC
15
55
NC
NC
16
54
NC
NC
17
53
NC
AUD_CL_OUT
18
52
ASG3
DMA_SYNC
19
51
SC2_OUT_R
XTAL_OUT
20
50
SC2_OUT_L
XTAL_IN
21
49
VREF1
TESTEN
22
48
SC1_OUT_R
ANA_IN2+
23
47
SC1_OUT_L
ANA_IN–
24
46
CAPL_A
ANA_IN1+
25
45
AHVSUP
AVSUP
26
44
CAPL_M
MSP 3400C
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AHVSS
AVSS
AGNDC
MONO_IN
NC
VREFTOP
NC
SC1_IN_R
NC
SC1_IN_L
ASG1
NC
SC2_IN_R
SC3_IN_L
SC2_IN_L
SC3_IN_R
ASG2
Fig. 8–5: 68-pin PLCC package
48
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
64
DMA_SYNC
NC
1
52
XTAL_OUT
2
63
XTAL_OUT
AUD_CL_OUT
2
51
XTAL_IN
NC
3
62
XTAL_IN
D_CTR_OUT1
3
50
TESTEN
D_CTR_OUT1
4
61
TESTEN
D_CTR_OUT0
4
49
ANA_IN2+
D_CTR_OUT0
5
60
ANA_IN2+
ADR_SEL
5
48
ANA_IN–
ADR_SEL
6
59
ANA_IN–
STANDBYQ
6
47
ANA_IN1+
STANDBYQ
7
58
ANA_IN1+
I2C_CL
7
46
AVSUP
NC
8
57
AVSUP
I2C_DA
8
45
AVSS
I2C_CL
9
56
AVSS
I2S_CL
9
44
MONO_IN
I2C_DA
10
55
MONO_IN
I2S_WS
10
43
VREFTOP
I2S_CL
11
54
VREFTOP
I2S_DA_OUT
11
42
SC1_IN_R
I2S_WS
12
53
SC1_IN_R
I2S_DA_IN1
12
41
SC1_IN_L
I2S_DA_OUT
13
52
SC1_IN_L
S_DA_IN
13
40
SC2_IN_R
I2S_DA_IN1
14
51
ASG1
S_ID
14
39
SC2_IN_L
S_DA_IN
15
50
SC2_IN_R
S_CL
15
38
SC3_IN_R
S_ID
16
49
SC2_IN_L
DVSUP
16
37
SC3_IN_L
S_CL
17
48
ASG2
DVSS
17
36
AGNDC
DVSUP
18
47
SC3_IN_R
I2S_DA_IN2
18
35
AHVSS
DVSS
19
46
SC3_IN_L
NC
19
34
CAPL_M
I2S_DA_IN2
20
45
NC
RESETQ
20
33
AHVSUP
NC
21
44
NC
DACA_R
21
32
CAPL_A
NC
22
43
NC
DACA_L
22
31
SC1_OUT_L
NC
23
42
AGNDC
VREF2
23
30
SC1_OUT_R
RESETQ
24
41
AHVSS
DACM_R
24
29
VREF1
DACA_R
25
40
CAPL_M
DACM_L
25
28
SC2_OUT_L
DACA_L
26
39
AHVSUP
NC
26
27
SC2_OUT_R
VREF2
27
38
CAPL_A
DACM_R
28
37
SC1_OUT_L
DACM_L
29
36
SC1_OUT_R
ASG3
30
35
VREF1
NC
31
34
SC2_OUT_L
NC
32
33
SC2_OUT_R
Fig. 8–6: 64-pin shrink PSDIP package
MICRONAS INTERMETALL
MSP 3400C
1
NC
MSP 3400C
AUD_CL_OUT
Fig. 8–7: 52-pin shrink PSDIP package
49
MSP 3400C
PRELIMINARY DATA SHEET
SC2_IN_L
SC2_IN_R
ASG2
SC3_IN_R
SC3_IN_L
ASG1
NC
SC1_IN_L
SC1_IN_R
NC
VREFTOP
NC
NC
NC
MONO_IN
AGNDC
AVSS
AHVSS
AVSS
AHVSS
NC
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVSUP
65
40
CAPL_M
AVSUP
66
39
AHVSUP
ANA_IN1+
67
38
CAPL_A
ANA_IN–
68
37
SC1_OUT_L
ANA_IN2+
69
36
SC1_OUT_R
TESTEN
70
35
VREF1
XTAL_IN
71
34
SC2_OUT_L
XTAL_OUT
72
33
SC2_OUT_R
DMA_SYNC
73
32
ASG3
AUD_CL_OUT
74
31
NC
NC
75
30
NC
NC
76
29
NC
D_CTR_OUT1
77
28
DACM_L
D_CTR_OUT0
78
27
DACM_R
ADR_SEL
79
26
VREF2
STANDBY_Q
80
25
DACA_L
MSP 3400C
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC
DACA_R
I2C_CL
NC
I2C_DA
NC
I2S_CL
RESETQ
I2S_WS
NC
I2S_DA_OUT
NC
I2S_DA_IN1
NC
S_DA_IN
I2S_DA_IN2
DVSS
S_ID
S_CL
DVSS
DVSUP
DVSUP
DVSS
DVSUP
Fig. 8–8: 80-pin PQFP package
50
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
8.4. Pin Circuits
DVSUP
P
2.5 V
N
GND
Fig. 8–14: Input Pin 19 (DMA_SYNC)
Fig. 8–9: Output Pins 1, 5, 13, 14, and 68
(S_ID, I2S_DA_OUT, D_CTR_OUT0/1, S_CL)
DVSUP
P
DVSUP
P
N
GND
N
GND
Fig. 8–10: Input Pins 4 and 65
(I2S_DA_IN1/2)
Fig. 8–15: Input Pin 3
(S_DA_IN)
P
N
GND
3–30 pF
Fig. 8–11: Input/Output Pins 8 and 9
(I2C_DA, I2C_CL)
500 k
N
2.5 V
3–30 pF
Fig. 8–16: Output/Input Pins 18, 20, and 21
(AUD_CL_OUT, XTALIN/OUT)
Fig. 8–12: Input Pins 11, 12, 61, and 62
(STANDBYQ, ADR_SEL, RESETQ, TESTEN)
ANAIN1+
ANAIN2+
A
D
DVSUP
P
ANAIN–
VREFTOP
N
GND
Fig. 8–13: Input/Output Pins 6 and 7
(I2S_WS, I2S_CL)
MICRONAS INTERMETALL
Fig. 8–17: Input Pins 23–25 and 29
(ANA_IN2+, ANA_IN–, ANA_IN1+, VREFTOP)
51
MSP 3400C
PRELIMINARY DATA SHEET
AHVSUP
16 K
≈ 3.75 V
0...1.2 mA
Fig. 8–18: Input Pin 28 (MONO_IN)
3.3 K
Fig. 8–21: Output Pins 56, 57, 59, and 60
(DACA_L/R, DACM_L/R)
125 K
≈ 3.75 V
0...2 V
Fig. 8–19: Capacitor Pins 44 and 46
(CAPL_M, CAPL_A)
Fig. 8–22: Pin 42 (AGNDC)
40 pF
80 K
300
40 K
≈ 3.75 V
Fig. 8–20: Input Pins 30, 31, 33, 34, 36, and 37
(SC1–3_IN_L/R)
52
≈ 3.75 V
Fig. 8–23: Output Pins 47, 48, 50 and 51
(SC_1/2_OUT_L/R)
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
8.5. Electrical Characteristics
8.5.1. Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Min.
Max.
Unit
TA
Ambient Operating Temperature
–
0
70
°C
TS
Storage Temperature
–
–40
125
°C
VSUP1
First Supply Voltage
AHVSUP
–0.3
9.0
V
VSUP2
Second Supply Voltage
DVSUP
–0.3
6.0
V
VSUP3
Third Supply Voltage
AVSUP
–0.3
6.0
V
dVSUP23
Voltage between AVSUP
and DVSUP
AVSUP,
DVSUP
–0.5
0.5
V
PTOT
Chip Power Dissipation
PLCC68 without Heat Spreader
AHVSUP,
DVSUP, AVSUP
1100
mW
–0.3
VSUP2+0.3
V
VIdig
Input Voltage, all Digital Inputs
IIdig
Input Current, all Digital Pins
–
–20
+20
mA1)
VIana
Input Voltage, all Analog Inputs
SCn_IN_s,2)
MONO_IN
–0.3
VSUP1+0.3
V
IIana
Input Current, all Analog Inputs
SCn_IN_s,2)
MONO_IN
–5
+5
mA1)
IOana
Output Current, all SCART Outputs
SCn_OUT_s2)
3), 4)
3), 4)
IOana
Output Current, all Analog Outputs
except SCART Outputs
DACp_s2)
3)
3)
ICana
Output Current, other pins
connected to capacitors
CAPL_p,2)
AGNDC
3)
3)
1)
2)
3)
4)
positive value means current flowing into the circuit
“n” means “1”, “2” or “3”,
“s” means “L” or “R”, “p” means “M” or “A”
The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.
Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
MICRONAS INTERMETALL
53
MSP 3400C
PRELIMINARY DATA SHEET
8.5.2. Recommended Operating Conditions
(at TA = 0 to 70 °C)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VSUP1
First Supply Voltage
AHVSUP
7.6
8.0
8.4
V
VSUP2
Second Supply Voltage
DVSUP
4.75
5.0
5.25
V
VSUP3
Third Supply Voltage
AVSUP
4.75
5.0
5.25
V
VREIL
RESET Input Low Voltage
RESETQ
0.45
VSUP2
VREIH
RESET Input High Voltage
0.8
VSUP2
tREIL
RESET Low Time after DVSUP
Stable and Oscillator Startup
5
µs
VDMAIL
Sync Input Low Voltage
VDMAIH
Sync Input High Voltage
tDMA
Sync Input Frequency
RDMA
Sync Input Clock High-Level Time
VDIGIL
Digital Input Low Voltage
VDIGIH
Digital Input High Voltage
STANDBYQ,
ADR SEL
ADR_SEL,
TESTEN
tSTBYQ1
STANDBYQ Setup Time before
Turn-off of Second Supply Voltage
STANDBYQ,
DVSUP
DMA_SYNC
0.44
0.56
VSUP1
VSUP1
18.0
kHz
500
ns
0.25
VSUP2
0.75
VSUP2
1
µs
I2C-Bus Recommendations
54
VIMIL
I2C-BUS Input Low Voltage
I2C_CL,
I2C_DA
C DA
VIMIH
I2C-BUS Input High Voltage
fIM
I2C-BUS Frequency
I2C_CL
tI2C1
I2C START Condition Setup Time
tI2C2
I2C STOP Condition Setup Time
I2C_CL,
I2C_DA
C DA
tI2C3
I2C-Clock Low Pulse Time
tI2C4
I2C-Clock High Pulse Time
tI2C5
I2C-Data Setup Time Before
Rising Edge of Clock
tI2C6
I2C-Data Hold Time after Falling
Edge of Clock
VI2SIL
I2S-Data Input Low Voltage
VI2SIH
I2S-Data Input High Voltage
0.3
0.6
I2C_CL
I2C_CL,
I2C_DA
VSUP2
VSUP2
1.0
MHz
120
ns
120
ns
500
ns
500
ns
55
ns
55
ns
I2S_DA_IN1/2
0.25
0.75
VSUP2
VSUP2
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
tI2S1
I2S-Data Input Setup Time
before Rising Edge of Clock
I2S_DA_IN1/2,
I2S_CL
20
ns
tI2S2
I2S-Data Input Hold Time
after Falling Edge of Clock
0
ns
VI2SIDL
I2S-Input Low Voltage when
MSP 3400C in I2S-Slave-Mode
VI2SIDH
I2S-Input High Voltage when
MSP 3400C in I2S-Slave-Mode
fI2SCL
I2S-Clock Input Frequency when
MSP 3400C in I2S-Slave-Mode
RI2SCL
I2S-Clock Input Ratio when
MSP 3400C in I2S-Slave-Mode
fI2SWS
I2S-Wordstrobe Input Frequency
when MSP 3400C in I2S-SlaveMode
I2S_WS
tI2SWS1
I2S-Wordstrobe Input Setup Time
before Rising Edge of Clock when
MSP 3400C in I2S-Slave-Mode
I2S_WS,
I2S_CL
tI2SWS2
I2S-Wordstrobe Input Hold Time
after Falling Edge of Clock when
MSP 3400C in I2S-Slave-Mode
VSBUSIL
SBUS-Data Input Low Voltage
ISBUSIL
SBUS-Data Input Low Current
0.9
VSBUSTRIG
SBUS-Data Input Trigger Voltage
0.8
tSBUS1
SBUS-Data Input Setup Time
before Rising Edge of Clock
tSBUS2
SBUS-Data Input Hold Time
after Falling Edge of Clock
I2S_CL,
I2S_WS
Max.
0.25
0.75
I2S_CL
VSUP2
VSUP2
1.024
0.9
MHz
1.1
32.0
kHz
60
ns
0
ns
S_DA_IN
S_DA_IN,
S_CL
Unit
1.7
0.6
V
3.2
mA
1.2
V
10
ns
0
ns
Crystal Recommendations for Master-Slave Application
fP
Parallel Resonance Frequency at
12 pF Load Capacitance
fTOL
Accuracy of Adjustment
–20
+20
ppm
DTEM
Frequency Variation versus
Temperature
–20
+20
ppm
RR
Series Resistance
8
25
Ω
C0
Shunt (Parallel) Capacitance
6.2
7.0
pF
C1
Motional (Dynamic) Capacitance
MICRONAS INTERMETALL
18.432
19
24
MHz
fF
55
MSP 3400C
Symbol
Parameter
PRELIMINARY DATA SHEET
Pin Name
Min.
Typ.
Max.
Unit
Load Capacitance Recommendations for Master-Slave Applications
CL
External Load Capacitance2)
fCL
Required Open Loop Clock
Frequency (Tamb = 25°C)
XTAL_IN,
XTAL_OUT
PSDIP
PLCC
1.5
3.3
18.431
pF
pF
18.433
MHz
Crystal Recommendations for FM Application (No Master-Slave Mode possible)
fP
Parallel Resonance Frequency at
12 pF Load Capacitance
18.432
MHz
fTOL
Accuracy of Adjustment
–100
+100
ppm
DTEM
Frequency Variation versus
Temperature
–50
+50
ppm
RR
Series Resistance
8
25
Ω
C0
Shunt (Parallel) Capacitance
6.2
7.0
pF
Load Capacitance Recommendations for FM Application (No Master-Slave Mode possible)
External Load Capacitance2)
CL
XTAL_IN,
XTAL_OUT
PSDIP
PLCC
1.5
3.3
pF
pF
Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF)
VXCA
External Clock Amplitude
XTAL_IN
0.7
Vpp
AGNDC
–20%
3.3
µF
–20%
100
nF
–20%
330
Analog Input and Output Recommendations
CAGNDC
AGNDC-Filter-Capacitor
Ceramic Capacitor in Parallel
DC-Decoupling Capacitor in front
of SCART Inputs
VinSC
SCART Input Level
VinMONO
Input Level, Mono Input
MONO_IN
RLSC
SCART Load Resistance
SCn_OUT_s1)
CLSC
SCART Load Capacitance
CVMA
Main/AUX Volume Capacitor
CAPL_M,
CAPL_A
CFMA
Main/AUX Filter Capacitor
DACM_s,
DACA_s1)
1)
2)
56
SCn_IN_s1)
CinSC
+20%
nF
2.0
VRMS
2.0
VRMS
10
kΩ
6.0
µF
10
–10%
1
nF
+10%
nF
“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. The higher the capacitors,
the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely
as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the
application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VREFTOP
–20%
10
µF
–20%
100
nF
0.14
0.8
Recommendations for Analog Sound IF Input Signal
CVREFTOP
VREFTOP-Filter-Capacitor
Ceramic Capacitor in Parallel
VIF
Analog Input Range
(Complete Sound IF, 0 – 9 MHz)
RFM
Ratio: FM-Main/FM-Sub
Satellite
7
dB
RFM1/FM2
Ratio: FM1/FM2
German FM-System
7
dB
RFC
Ratio: Main FM Carrier/Color
Carrier
15
–
–
dB
RFV
Ratio: Main FM Carrier/Luma
Components
15
–
–
dB
PRIF
Passband Ripple
–
–
±2 dB
dB
SUPHF
Suppression of Spectrum
Above 9.0 MHz
15
–
dB
FMMAX
Maximum FM-Deviation (apprx.)
normal mode
high deviation mode
±192
±360
kHz
MICRONAS INTERMETALL
ANA_IN1+,
ANA_IN2+,
ANA IN
ANA_IN–
3
Vpp
57
MSP 3400C
PRELIMINARY DATA SHEET
8.5.3. Characteristics at TA = 0 to 70 °C, fCLOCK = 18.432 MHz
(Typical values are measured at TA = 25 °C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.)
Symbol
Parameter
Pin Name
fCLOCK
Clock Input Frequency
XTAL_IN
DCLOCK
Clock High to Low Ratio
tJITTER
Clock Jitter (verification not
provided in production test)
VxtalDC
DC-Voltage Oscillator
tStartup
Oscillator Startup Time at
VDD Slew-rate of 1 V / 1 µs
XTAL_IN,
XTAL_OUT
First Supply Current (active)
AHVSUP
Min.
Typ.
Max.
Unit
Test Conditions
DCO
18.432
45
MHz
55
%
50
ps
2.5
V
0.4
2.0
ms
8.2
5.6
14.8
10.0
22.0
15.0
mA
mA
60
65
70
mA
f = 18.432 MHz
DVSUP = 5 V
mA
f = 18.432 MHz
AVSUP = 5 V
mA
STANDBYQ = low
VSUP = 8 V
Vpp
40 pF load
Power Supply
ISUP1A
Analog Volume for Main and Aux at 0dB
Analog Volume for Main and Aux at –30dB
at Tj = 27 °C
ISUP2A
Second Supply Current (active)
DVSUP
ISUP3A
Third Supply Current (active)
AVSUP
ISUP1S
First Supply Current
(standby mode) at Tj = 27 °C
AHVSUP
2.8
AUD_CL_OUT
1.2
25
5.0
7.2
f = 18.432 MHz
AHVSUP = 8 V
DVSUP = 5 V
AVSUP = 5 V
Audio Clock Output
VAPUAC
Audio Clock Output AC Voltage
VAPUDC
Audio Clock Output DC Voltage
0.4
0.6
VSUP1
0.4
V
IDDCTR = 1 mA
4.0
V
IDDCTR = –1 mA
0.4
V
IiMOL = 3 mA
µA
VIMOH = 5 V
Digital Output
VDCTROL
Digital Output Low Voltage
VDCTROH
Digital Output High Voltage
D_CTR_OUT0
D_CTR_OUT1
D CTR OUT1
I2C Bus
VIMOL
I2C-Data Output Low Voltage
IIMOH
I2C-Data Output High Current
tIMOL1
I2C-Data Output Hold Time after
Falling Edge of Clock
tIMOL2
I2C-Data Output Setup Time
before Rising Edge of Clock
I2C_DA
1
I2C_DA,
I2C_CL
15
ns
100
ns
fIM = 1 MHz
DVSUP = 5 V
kHz
DVSUP = 5 V
SBus
fSB
SBUS-Clock Frequency
tS1/S2
SBUS-Clock High/Low-Ratio
tS3
SBUS Setup Time before
Ident End Pulse
S_CL,
S_ID
fSIO
SBUS Ident frequency
S_ID
tS6
SBUS-Ident End Pulse Time
58
S_CL
4608
0.9
1.0
210
ns
ns
32
210
1.1
DVSUP = 5.25 V
kHz
ns
DVSUP = 5.25 V
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
VI2SOL
I2S Output Low Voltage
VI2SOH
I2S Output High Voltage
I2S_WS,
I2S_CL,
I2S CL
I2S_DA_OUT
fI2SCL
I2S-Clock Output Frequency
I2S_CL
fI2SWS
I2S-Wordstrobe Output Frequency
I2S_WS
tI2S1/I2S2
I2S-Clock High/Low-Ratio
I2S_CL
0.9
tI2S3
I2S-Data Setup Time
before Rising Edge of Clock
I2S_CL,
I2S_DA_OUT
tI2S4
I2S-Data Hold Time after Falling
Edge of Clock
tI2S5
I2S-Wordstrobe Setup Time
before Rising Edge of Clock
tI2S6
I2S-Wordstrobe Hold Time after
Falling Edge of Clock
Typ.
Max.
Unit
Test Conditions
0.4
V
II2SOL = 1 mA
V
II2SOH = –1 mA
1204
kHz
DVSUP = 5 V
32.0
kHz
DVSUP = 5 V
200
ns
DVSUP = 4.75 V
12
ns
DVSUP = 5.25 V
100
ns
DVSUP = 4.75 V
50
ns
DVSUP = 5.25 V
Rload ≥ 10 MΩ
I2S Bus
I2S_CL,
I2S_WS
4.0
1.0
1.1
Analog Ground
VAGNDC0
AGNDC Open Circuit Voltage
RoutAGN
AGNDC Output Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
AGNDC
3.64
3.73
3.84
V
70
70
125
180
180
kΩ
kΩ
25
25
40
58
58
kΩ
kΩ
10
10
16
23
23
kΩ
kΩ
2.02
2.12
2.22
VRMS
0.20
0.20
0.33
0.46
0.5
kΩ
kΩ
+70
mV
3 V ≤ VAGNDC ≤ 4 V
Analog Input Resistance
RinSC
RinMONO
SCART Input Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
SCn_IN_s1)
MONO Input Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
MONO_IN
fsignal = 1 kHz,
I ≤ 0.05 mA
fsignal = 1 kHz,
I ≤ 0.1 mA
Audio Analog-to-Digital-Converter
VAICL
Analog Input Clipping Level for
Analog-to-Digital-Conversion
SCn_IN_s,1)
MONO_IN
fsignal = 1 kHz
SCART Outputs
RoutSC
SCART Output Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
dVOUTSC
Deviation of DC-Level at SCART
Output from AGNDC Voltage
ASCtoSC
Gain from Analog Input to SCART
Output
frSCtoSC
VoutSC
1)
Frequency Response from Analog
Input to SCART Output
bandwidth: 0 to 20000 Hz
Signal Level at SCART-Output
during full-scale digital input signal
from DSP
“n” means “1”, “2” or “3”,
“s” means “L” or “R”,
MICRONAS INTERMETALL
SCn_OUT_s1)
fsignal = 1 kHz, I = 0.1 mA
–70
SCn_IN_s1)
MONO_IN
→
SCn_OUT_s1)
SCn_OUT_s1)
fsignal = 1kHz
–1.0
0
+0.5
dB
–0.5
0
+0.5
dB
1.8
1.9
2.0
VRMS
with respect to 1 kHz
fsignal = 1 kHz
“p” means “M” or “A”
59
MSP 3400C
Symbol
Parameter
PRELIMINARY DATA SHEET
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
2.1
2.1
3.3
4.6
5.0
kΩ
kΩ
DC-Level at Main/AUX-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB
1.74
–
1.94
61
2.14
–
V
mV
Signal Level at Main/AUX-Output
during full-scale digital input signal
from DSP for Analog Volume at
0 dB
1.23
1.37
1.51
VRMS
fsignal = 1 kHz
Main and AUX Outputs
RoutMA
VoutDCMA
VoutMA
Main/AUX Output Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
DACp_s1)
fsignal = 1 kHz, I = 0.1 mA
Analog Performance
SNR
THD
1)
2)
3)
60
Signal-to-Noise Ratio
from Analog Input to DSP
MONO_IN,
SCn_IN_s1)
85
88
dB
Input Level = –20 dB with
resp. to VAICL, fsig = 1
kHz, equally weighted
20 Hz ... 16 kHz2)
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s1)
→
SCn_OUT_s1)
93
96
dB
Input Level = –20 dB,
fsig = 1 kHz,
equally weighted
20 Hz ... 20 kHz
from DSP to SCART Output
SCn_OUT_s1)
85
88
dB
Input Level = –20 dB,
fsig = 1 kHz,
equally weighted
20 Hz ... 15 kHz3)
from DSP to Main/AUX-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB
DACp_s1)
85
78
88
83
dB
dB
Input Level = –20 dB,
fsig = 1 kHz,
equally weighted
20 Hz ... 15 kHz3)
Total Harmonic Distortion
from Analog Input to DSP
MONO_IN,
SCn_IN_s1)
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s
→
SCn_OUT_s1)
from DSP to SCART Output
from DSP to Main or AUX Output
“n” means “1”, “2” or “3”,
“s” means “L” or “R”,
DSP measured at I2S-Output
DSP Input at I2S-Input
0.05
%
Input Level = –3 dBr with
resp. to VAICL, fsig =1kHz,
equally weighted
20 Hz ...16 kHz,
RLoad = 30 kΩ2)
0.01
0.03
%
Input Level = –3 dBr,
fsig = 1 kHz, equally
weighted 20 Hz ... 20 kHz,
RLoad = 30 kΩ
SCn_OUT_s1)
0.01
0.03
%
Input Level = –3 dBr,
fsig = 1 kHz, equally
weighted 20 Hz ... 16 kHz,
RLoad = 30 kΩ3)
DACA_s,
DACM_s1)
0.01
0.03
%
Input Level = –3 dBr,
fsig = 1 kHz, equally
weighted 20 Hz ... 16 kHz,
RLoad = 30 kΩ3)
“p” means “M” or “A”
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
XTALK
Crosstalk attenuation
– PLCC68
– PSDIP64
Input Level = –3 dB,
fsig = 1 kHz, unused analog inputs connected to
ground by Z<1 kΩ
between left and right channel within SCART Input/Output pair (L→R, R→L)
equally weighted
20 Hz ... 20 kHz
SCn_IN → SCn_OUT1)
PLCC68
PSDIP64
80
80
dB
dB
SCn_IN → DSP1)
PLCC68
PSDIP64
80
80
dB
dB
DSP → SCn_OUT1)
PLCC68
PSDIP64
80
80
dB
dB
between left and right channel within Main or AUX
Output pair
DSP → DACp1)
PLCC68
PSDIP64
2)
3)
equally weighted
20 Hz ... 16 kHz
80
75
dB
dB
between SCART Input/Output pairs1)
D = disturbing program
O = observed program
3)
(equally weighted
20 Hz ... 20 kHz)
same signal source on
left and right disturbing
channel effect on each
channel,
observed output channel
D: MONO/SCn_IN → SCn_OUT
O: MONO/SCn_IN → SCn_OUT1)
PLCC68
PSDIP64
100
100
dB
dB
D: MONO/SCn_IN → SCn_OUT
O: or unsel. MONO/SCn_IN → DSP1)
PLCC68
PSDIP64
95
95
dB
dB
2)
D: MONO/SCn_IN → SC1_OUT
O: DSP → SCn_OUT1)
PLCC68
PSDIP64
100
100
dB
dB
3)
D: MONO/SCn_IN → unselected
O: DSP → SC1_OUT1)
PLCC68
PSDIP64
100
100
dB
dB
3)
95
90
dB
dB
Crosstalk between Main and AUX Output pairs
DSP → DACp1)
PLCC68
PSDIP64
Crosstalk from Main or AUX Output to SCART Output
and vice versa
(equally weighted
20 Hz ... 16 kHz)3)
same signal source on
left and right disturbing
channel, effect on each
observed output channel
(equally weighted
20 Hz ... 20 kHz)
same signal
source on
g
left and right disturbing
channel, effect on each
observed output channel
D = disturbing program
O = observed program
1)
2)
3)
Test Conditions
D: MONO/SCn_IN/DSP → SCn_OUT
O: DSP → DACp1)
PLCC68
PSDIP64
90
85
dB
dB
SCART output load resistance 10 kΩ
D: MONO/SCn_IN/DSP → SCn_OUT
O: DSP → DACp1)
PLCC68
PSDIP64
95
85
dB
dB
SCART output load resistance 30 kΩ
D: DSP → DACp
O: MONO/SCn_IN → SCn_OUT1)
PLCC68
PSDIP64
100
95
dB
dB
3)
D: DSP → DACp
O: DSP → SCn_OUT1)
PLCC68
PSDIP64
100
95
dB
dB
“n” means “1”, “2” or “3”,
“s” means “L” or “R”,
DSP measured at I2S-Output
DSP Input at I2S-Input
MICRONAS INTERMETALL
“p” means “M” or “A”
61
MSP 3400C
Symbol
PRELIMINARY DATA SHEET
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
PSRR: rejection of noise on AHVSUP at 1 kHz
PSRR
AGNDC
AGNDC
80
dB
From analog Input to DSP
MONO_IN
SCn_IN_s1)
69
dB
From analog Input to
SCART Output
MONO_IN
SCn_IN_s,1)
SCn_OUT_s1)
74
dB
From DSP to SCART Output
SCn_OUT_s1)
70
dB
From DSP to MAIN/AUX Output
DACp_s1)
80
dB
Sound IF Input Section
DCVREFTOP
DC voltage at VREFTOP
VREFTOP
2.4
2.6
2.7
V
VSUPANALOG = 5 V
RLoad ≥ 10 MΩ
RIFIN
Input Impedance
ANA_IN1+,
ANA_IN2+,
ANA_IN–
1.5
10.5
2
14.1
2.5
17.6
kOhm
AGC = +20 dB
AGC = +3 dB
RLoad ≥ 10 MΩ
DCANA_IN
DC voltage on IF inputs
1.3
1.5
1.7
V
AVSUP = 5 V
RLoad ≥ 10 MΩ
XTALKIF
Crosstalk attenuation
40
t.b.d.
–
dB
fsig = 1 MHz,
Input Level = –2 dBr
BWIF
3 dB Bandwidth
10
–
–
MHz
Input Level = –2 dBr
AGC
AGC step width
t.b.d.
0.85
t.b.d.
dB
fsig = 1 MHz,
Input Level = –2 dBr
1)
62
“n” means “1”, “2” or “3”,
“s” means “L” or “R”,
“p” means “M” or “A”
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
DACp_s,
SCn_OUT_s1)
Typ.
Max.
Unit
Test Conditions
70
–
dB
1 FM-carrier 5.5 MHz,
50 µs, 1 kHz, 40 kHz deviation; RMS, unweighted
0 to 15 kHz; full input
range
Overall Performance
S/NFM
FM input to Main/AUX/SCART
Output
S/ND2MAC
Signal to Noise ratio of D2MAC
baseband signal on Main/AUX/
SCART outputs
TBD
–
dB
THDFM
Total Harmonic Distortion + Noise
of FM demodulated signal on
Main/AUX/SCART output
–
0.3
%
1 FM-carrier 5.5 MHz,
1kHz, 50 µs; 40 kHz deviation; full input range
THDD2MAC
Total Harmonic Distortion + Noise
of D2MAC baseband signal for
Main/AUX/SCART output
–
0.1
%
2.12 kHz, Modulator input
level = 0 dBref
dVFMOUT
Tolerance of output voltage of FM
demodulated signal
–1.5
+1.5
dB
1 FM-carrier, 50 µs,
1 kHz
40 kHz deviation; RMS
dV-
Tolerance of output voltage of
D2MAC baseband signal
–1.5
+1.5
dB
2.12 kHz, Modulator input
level = 0 dBref
fRFM
FM frequency response on Main/
AUX/SCART outputs, bandwidth
20 to 15000 Hz
–1.0
+1.0
dB
1 FM-carrier 5.5 MHz,
50 µs, Modulator input
level = –14.6 dBref; RMS
fRD2MAC
D2MAC frequency response on
Main/AUX/SCART outputs, bandwidth 20 to 15000 Hz
–1.0
+1.0
dB
Modulator input level =
–12 dB dBref; RMS
SEPFM
FM channel separation (Stereo)
50
dB
2 FM-carriers 5.5/5.74
MHz, 50 µs, 1 kHz, 40
kHz deviation; RMS
SEPD2MAC
D2MAC channel separation
(Stereo)
80
dB
XTALKFM
FM crosstalk attenuation (Dual)
80
dB
XTALK-
D2MAC crosstalk attenuation
(Dual)
80
dB
D2MACOUT
D2MAC
1)
“n” means “1”, “2” or “3”,
“s” means “L” or “R”,
MICRONAS INTERMETALL
0.01
2 FM-carriers 5.5/5.74
MHz, 50 µs, 1 kHz, 40
kHz deviation; RMS
“p” means “M” or “A”
63
MSP 3400C
PRELIMINARY DATA SHEET
9. Application of the MSP 3400C
IF 2 IN
Signal GND
100
nF
+
18.432
3.3 100 MHz
µF nF
+
10 µF 10 µF
XTAL_OUT (63) 20
AGNDC (42) 42
VREFTOP (54) 29
Ana_IN2+ (60) 23
Ana_IN– (59) 24
+
+
50pF 50pF 50pF
Ana_IN1+ (58) 25
+8.0 V
CAPL_A (46) 38
10
µF -
IF 1 IN
XTAL_IN (62) 21
Tuner 1
0.1 pF
CAPL_M (40) 44
Tuner 2
28 (55) MONO_IN
1µF
330 nF
52 (30) ASG3
AHVSS
DACM_L (29) 56
30 (53) SC1_IN_R
330 nF
31 (52) SC1_IN_L
330 nF
AHVSS
1 nF
1µF
1 nF
1µF
1 nF
1µF
MAIN
DACM_R (28) 57
32 (51) ASG1
33 (50) SC2_IN_R
330 nF
DACA_L (26) 59
34 (49) SC2_IN_L
330 nF
35 (48) ASG2
AHVSS
HEADPHONE
DACA_R (25) 60
36 (47) SC3_IN_R
330 nF
1 nF
37 (46) SC3_IN_L
330 nF
MSP 3400C
5V
SC1_OUT_L (37) 47
11 (7) STANDBY Q
SC1_OUT_R (36) 48
5V
DVSS
DVSS
12 (6) ADR_SEL
SC2_OUT_L (34) 50
9 (9) I2C-CL
8 (10) I2C-DA
SC2_OUT_R (33) 51
100Ω 22 µF
+
100Ω 22 µF
+
100Ω 22 µF
+
100Ω 22 µF
+
1 (16) S_ID
68 (17) S_CL
3 (15) S_DA_IN
D_CTR_OUT0 (5) 13
6 (12) I2S_WS
7 (11) I2S_CL
4 (14) I2S_DA_IN1
AUD_CL_OUT (1) 18
D_CTR_OUT1 (4) 14
DMA_SYNC (64) 19
58 (27) VREF2
49 (35) VREF1
43 (41) AHVSS
45 (39) AHVSUP
27 (56) AVSS
26 (57) AVSUP
66 (19) DVSS
TESTEN (61) 22
67 (18) DVSUP
61 (24) RESETQ
65 (20) I2S_DA_IN2
5 (13) I2S_DA_OUT
DVSS
100
nF
5V
100
nF
5V
100
nF
AVSS
+
10 µF
8.0 V
Note: Pin numbers refer to PLCC packages, pin numbers for PSDIP packages in brackets.
not connected pins are 2,10,15,16,17,38,39,40,41,53,54,55,62,63,64 (2,3,8,21,22,23,31,32,43,44,45)
64
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
AMU, DMA 2386, and DMA 2381, it is recommended to
use a clock inverter circuit, as shown below right, a minimum gain of 1.0 at 18.432 MHz and an output phase as
specified in Fig. 10–2.
10. DMA Application
Fig. 10–1 shows an example for the D2MAC application
with the MSP 3400 or MSP 3400C. To obtain the optimal
amplitude and phase conditions for the clock input of
+ 5 Volt
5K
S_DATA 66
9 S_DATA_IN
S_IDENT 64
15 S_IDENT
S_CLOCK 67
8 S_CLOCK
open
AMU 2481
DMA 2381
S_Bus
Slave_mode
Software:
S_DATA_OUT 6
SBS = 1
ACS = 1
ACF = 0
DCOF= 1
(addr. 204, 214)
ACLK
65
17
13 AUDIO_CLOCK
16
18.432 MHz
3
S_DA_IN
68 S_CL
1 nF
1 S_ID
MSP 3400C C6...
MSP 3410/00
TC15/F7
MODE_REG[0] = 1
Clock
Inverter
+2...3 V
18 AUD_CL_OUT
(see below)
4.7 nF
19 DMA_SYNC
Clock Inverter
65
ACLK
66
S_DATA
+5 V
64
S_IDENT
100 nF
DMA 2386
120
To
DMA 2381/86
and AMU 2481
6k8
10 nF
BC 848C
82
3k8
Fig. 10–1: DMA application with MSP 3410 TC15 or F7
Note: Pin numbers refer to PLCC packages for DMA 2381 and MSP 3400C and to PSDIP package for AMU 2481
MICRONAS INTERMETALL
65
MSP 3400C
PRELIMINARY DATA SHEET
MSP Clock Output
typ. 20 ns
at inverter output
Clock Inverter Output
Timing window
for the low to high edge at
pin 17 of DMA 2381 (XTAL2)
> 10 ns
< 42 ns
Fig. 10–2: Timing requirements for the clock signal at the DMA 2381 clock input
In the following table, the input/output clock-specification of the D2MAC circuit is shown.
Table 10–1: Clock input and output specification for MSPs
MSP 3400C >C6
new Version
MSP 3410/00 TC27
new Version
MSP 3410/00 TC15
actual Version
XTAL_IN min
(minimum amplitude)
> 0.7 Vpp
> 0.7 Vpp
> 0.7 Vpp
C input
(after Reset)
22 pF
22 pF
31 pF
AUD_CL_OUT min
with C load
> 1.2 Vpp
40 pF
> 1.2 Vpp
40 pF
> 1.0 Vpp
43 pF
Rout (HF) typ.
150 Ω
120 Ω
120 Ω
Table 10–2: Clock input and output specification for ICs connected to MSP
XTAL_IN min
Clock-in min
(minimal amplitude)
DMA 2381
DMA 2386
AMU2481
> 0.7 Vpp
> 0.7 Vpp
> 0.7 Vpp
24 pF
10 pF with: Adr.
204,14=1
7pF
7pF
C input
For the DMA_SYNC input specification of the MSP, please refer to page 54 “VDMAIL, VDMAIH.”
66
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
11. MSP Application with External Clock
If for some reason, e.g. to spare the cost of an additional
crystal, the MSP receives the 18.432 MHz clock from an
external source, for example from an other MSP, the following circuit can be used. For input/output specification
see also Table 10–1.
18.432 MHz
62
63
MSP 3400C or
MSP 3410B
MSP 3400C
10 nF
AUD_CL_OUT 18
62 XTAL_IN
LV
63 XTAL_OUT
Fig. 11–1: MSP 3400C with external clock
12. ADR Application
18.432 MHz
18.432 MHz
S_CL
S_ID
S_DA_IN
Tuner
(Sat)
MSP 3400C
(in I2S Slave Mode)
I2S_CL
I2S_WS
I2S_DA_IN
2
I S_DA_OUT
MICRONAS INTERMETALL
ADR-Interface
I2S-Interface
SI1C
SI1I
SI1D
PI16
PI15
SO1C
SO1I
SO1D
PI14
DRP 3510A
67
MSP 3400C
PRELIMINARY DATA SHEET
13. I2S Bus in Master/Slave Configuration with
Standby Mode
In a master/slave application, both MSP, after power up
and reset, will start as master by default. This means that
before the slave MSP is set to slave-mode, relatively
large current-pulses (~20 mA) in the I2S_CL and
I2S_WS lines can cause some crackling noise during
startup time, if the the MSP is demuted before the slave
MSP is set to slave mode.
These high current pulses are also possible, if the active
I2S_CL and I2S_WS outputs of the master MSP are
clipped by the correspondent inputs of the slave MSP,
which is switched to standby mode.
To avoid this, it is recommended, that the I2S-bus lines
I2S_CL and I2S_WS are current-limited to about 5 mA
with series resistors of about 390 Ω (330...470 Ω).
Fig. 13–1 depicts the recommended application circuit
for two MSP 3410/00 or MSP 3400C, which are connected via I2S Bus in a master/slave configuration, and
where the slave MSP can be switched in standby mode
(+5 Volt power is switched off).
Standby control
+5 V
18.432 MHz
62
18.432 MHz
63
18
DVSUP
I2S_DA_IN 14
MSP 3410/00
MSP 3400C
(master)
7
STANDBYQ
62
63
13 I2S_DA_OUT
I2S_DA_OUT 13
14 I2S_DA_IN
I2S_WS 12
12 I2S_WS
R
I2S_CL 11
MSP 3410/00
MSP 3400C
(slave)
C
11 I2S_CL
minimal corner frequency = 4 MHz
with R = 390 Ω (330–470 Ω)
Fig. 13–1: I2S master/slave application
68
MICRONAS INTERMETALL
MSP 3400C
PRELIMINARY DATA SHEET
14. APPENDIX A: Technical Code History
TC01
First Release, compatible with MSP3410 and
MSP 3400. Date: June 1994.
TC04
Emulator version for software development.
Version B5
New Features:
1. Equalizer
2. Improved identification
3. Improved adaptive deemphasis
Version C6
New Features:
1. Adjustable Stereo Basewidth Enlargement (SBE) and
switchable Pseudo Stereo Effect (SBE)
2. New Channel Matrix Modes (Mono, Sum/Dif, etc)
3. New Audio Clock Output Driver
4. Fast mute (Volume)
5. Clipping mode (Volume)
6. Sub dB steps for Volume, Bass, Treble, Equalizer
15. APPENDIX B: Documentation History
1. Advance Information: “MSP 3400C Multistandard
Sound Processor”, Apr. 14, 1994, 6251-377-1AI.
First release of the advance information.
2. MSP 3400C Data Sheet: “MSP 3400C Multistandard
Sound Processor”, Dec. 14, 1994, 6251-377-1PD.
First release of the preliminary data sheet.
3. MSP 3400C Data Sheet: “MSP 3400C Multistandard
Sound Processor”, Oct. 6, 1996, 6251-377-2PD.
Second release of the preliminary data sheet.
Major changes: see Appendix A: Version C6
4. MSP 3400C Data Sheet: “MSP 3400C Multistandard
Sound Processor”, Dec. 8, 1997, 6251-377-3PD.
Third release of the preliminary data sheet.
Major changes: see Appendix A: Version C7 and C8
– new PQFP80 package
Version C7
New Features:
1. Balance, Bass, Treble and Loudness for Headphone
output
2. Prescale for I2S1 and I2S2 inputs
3. Balance in dB units and linear mode
4. SCART volume in dB units and linear mode
5. Increased range for Bass/Treble
Version C8
New Features:
1. Automatic Volume Control A.V.C.
2. Subwoofer Output alternatively with Headphone Output.
MICRONAS INTERMETALL
69
MSP 3400C
70
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
MSP 3400C
71
MSP 3400C
MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: http://www.intermetall.de
Printed in Germany
Order No. 6251-377-3PD
72
PRELIMINARY DATA SHEET
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability. Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the
same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases.
MICRONAS INTERMETALL
End of Data Sheet
Multimedia ICs
MICRONAS
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