Revised March 2000 DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS85ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q L H X X H Q L H L X X L H L L X X H H ↑ H H (Note 1) H (Note 1) H L H H ↑ L L H H H L X Q0 Q0 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level ↑ = Positive-going Transition Q0 = The output logic level of Q before the indicated input conditions were established. Note 1: This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (HIGH) level. © 2000 Fairchild Semiconductor Corporation DS006373 www.fairchildsemi.com DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 DM74LS74A Absolute Maximum Ratings(Note 2) Supply Voltage Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 3) fCLK Clock Frequency (Note 4) tW Pulse Width (Note 3) tW 2 V 8 mA 0 25 MHz 0 20 MHz Clock HIGH 18 Preset LOW 15 Clear LOW 15 Pulse Width Clock HIGH 25 (Note 4) Preset LOW 20 Clear LOW 20 ns ns tSU Setup Time (Note 3)(Note 5) 20↑ ns tSU Setup Time (Note 4)(Note 5) 25↑ ns tH Hold Time (Note 5)(Note 6) 0↑ TA Free Air Operating Temperature 0 Note 3: CL = 15 pF, R L = 2 kΩ, TA = 25°C, and VCC = 5V. Note 4: CL = 50 pF, R L = 2 kΩ, TA = 25°C, and VCC = 5V. Note 5: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 6: TA = 25°C and V CC = 5V. www.fairchildsemi.com 2 ns 70 °C over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.7 IIH Units −1.5 V V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max Data 0.1 Input Voltage VI = 7V Clock 0.1 Preset 0.2 Clear 0.2 HIGH Level VCC = Max Data 20 Input Current VI = 2.7V Clock 20 Clear 40 Preset IIL Max 3.4 IOL = 4 mA, VCC = Min II Typ (Note 7) VCC = Max Data −0.4 Input Current VI = 0.4V Clock −0.4 Preset −0.8 VCC = Max (Note 8) ICC Supply Current VCC = Max (Note 9) µA mA −0.8 Clear Short Circuit Output Current mA 40 LOW Level IOS V −20 −100 mA 8 mA 4 Note 7: All typicals are at VCC = 5V, TA = 25°C. Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 9: With all outputs OPEN, ICC is measured with CLOCK grounded after setting the Q and Q outputs HIGH in turn. Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output Max 25 CL = 50 pF Min Units Max 20 MHz Clock to Q or Q 25 35 ns Clock to Q or Q 30 35 ns Preset to Q 25 35 ns Preset to Q 30 35 ns Clear to Q 25 35 ns Clear to Q 30 35 ns 3 www.fairchildsemi.com DM74LS74A Electrical Characteristics DM74LS74A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 DM74LS74A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6