DM54L72 AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs General Description This device contains a positive pulse triggered master-slave J-K flip-flop with complementary outputs. Multiple J and K inputs are ANDed together to produce the internal J and K function for the flip-flop. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is low the slave is isolated from the master. On the positive transition of the clock, the data from the AND gates is transferred to the master. While the clock is high the AND gate inputs are disabled. On the negative transition of the clock the data from the master is transferred to the slave. The logic state of the J and K inputs must not be allowed to change while the clock is in the high state. Data is transferred to the outputs on the falling edge of the clock pulse. A low logic level on the preset or clear inputs sets or resets the outputs regardless of the logic levels of the other inputs. Connection Diagram Function Table Inputs Dual-In-Line Package Outputs PR CLR CLK J (Note 1) L H L H H H H H L L H H H H X X X É É É É X X X L H L H K (Note 1) X X X L L H H Q Q H L L H H* H* Qo Qo H L L H Toggle Note 1: J e (J1)(J2)(J3), K e (K1)(K2)(K3) TL/F/6629 – 1 Order Number DM54L72J or DM54L72W See NS Package Number J14A or W14B C1995 National Semiconductor Corporation TL/F/6629 H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level É e Positive pulse. The J and K inputs must be held constant while the clock is high. Data is transferred to the outputs on the falling edge of the clock pulse. Qo e The output logic level before the indicated input conditions were established. * e This configuration is nonstable; that is, it will not persist when the preset and/or clear inputs return to their inactive (high) level. Toggle e Each output changes to the complement of its previous level on each complete high level clock pulse. RRD-B30M105/Printed in U. S. A. DM54L72 AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guarateed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 8V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54L b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol DM54L72 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage Units Min Nom Max 4.5 5 5.5 2 V V Clock 0.6 Others 0.7 V IOH High Level Output Current b 0.2 IOL Low Level Output Current 2 mA fCLK Clock Frequency (Note 2) 6 MHz tW Pulse Width (Note 2) 0 Clock High 100 Clock Low 100 Preset Low 100 Clear Low 100 tSU Input Setup Time (Notes 1 & 2) 0u tH Input Hold Time (Notes 1 & 2) 0v TA Free Air Operating Temperature b 55 Note 1: The symbols ( u, v) indicate the edge of the clock pulse used for reference: u for rising edge, v for falling edge. Note 2: TA e 25§ C and VCC e 5V. 2 mA ns ns ns 125 §C Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) 2.4 3.3 VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min II Input Current @ Max Input Voltage VCC e Max VI e 5.5V IIH IIL High Level Input Current Low Level Input Current VCC e Max VI e 2.4V VCC e Max VI e 0.3V IOS Short Circuit Output Current VCC e Max ICC Supply Current VCC e Max (Note 2) Max Units V 0.15 0.3 J, K 100 Clear 200 Preset 200 Clock 200 J, K 10 Clear 20 Preset 20 Clock b 200 J, K b 0.18 Clear b 0.36 Preset b 0.36 Clock b 0.36 b3 0.76 V mA mA mA b 15 mA 1.44 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement the clock input is grounded. Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 4 kX, CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Preset to Q 6 75 ns tPHL Propagation Delay Time High to Low Level Output Preset to Q 150 ns tPLH Propagation Delay Level Output Low to High Level Output Clear to Q 75 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 150 ns tPLH Propagation Delay Time Low to High Level Output Clock to Q or Q 10 75 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q or Q 10 150 ns 3 MHz DM54L72 AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54L72J NS Package Number J14A 14-Lead Ceramic Flat Package (W) Order Number DM54L72W NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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