LP3961/LP3964 800mA Fast Ultra Low Dropout Linear Regulators General Description Features The LP3961/LP3964 series of fast ultra low-dropout linear regulators operate from a +2.5V to +7.0V input supply. Wide range of preset output voltage options are available. These ultra low dropout linear regulators respond very fast to step changes in load which makes them suitable for low voltage microprocessor applications. The LP3961/LP3964 are developed on a CMOS process which allows low quiescent current operation independent of output load current. This CMOS process also allows the LP3961/LP3964 to operate under extremely low dropout conditions. Dropout Voltage: Ultra low dropout voltage; typically 24mV at 80mA load current and 240mV at 800mA load current. Ground Pin Current: Typically 4mA at 800mA load current. Shutdown Mode: Typically 15µA quiescent current when the shutdown pin is pulled low. Error Flag: Error flag goes low when the output voltage drops 10% below nominal value (for LP3961). SENSE: Sense pin improves regulation at remote loads. (For LP3964) Precision Output Voltage: Multiple output voltage options are available ranging from 1.2V to 5.0V and adjustable, with a guaranteed accuracy of ± 1.5% at room temperature, and ± 3.0% over all conditions ( varying line, load, and temperature). n n n n n n n n n n n n Ultra low dropout voltage Low ground pin current Load regulation of 0.02% 15µA quiescent current in shutdown mode Guaranteed output current of 0.8A DC Available in SOT-223,TO-263 and TO-220 packages Output voltage accuracy ± 1.5% Error flag indicates output status (LP3961) Sense option improves better load regulation (LP3964) Extremely low output capacitor requirements Overtemperature/overcurrent protection −40˚C to +125˚C junction temperature range Applications n n n n n n n n Microprocessor power supplies GTL, GTL+, BTL, and SSTL bus terminators Power supplies for DSPs SCSI terminator Post regulators High efficiency linear regulators Battery chargers Other battery powered applications Typical Application Circuits DS101129-1 # Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin. *SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section for more information. © 2000 National Semiconductor Corporation DS101129 www.national.com LP3961/LP3964 800mA Fast Ultra Low Dropout Linear Regulators May 2000 LP3961/LP3964 Typical Application Circuits (Continued) DS101129-2 # Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin. *SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section for more information. Block Diagram LP3961 DS101129-3 www.national.com 2 LP3961/LP3964 Block Diagram LP3964 DS101129-29 Block Diagram LP3964-ADJ DS101129-30 Connection Diagrams DS101129-4 Top View SOT 223-5 Package 3 www.national.com LP3961/LP3964 Connection Diagrams (Continued) DS101129-5 Top View TO220-5 Package Bent, Staggered Leads DS101129-6 Top View TO263-5 Package Pin Description for SOT223-5 Package Pin # LP3961 Name LP3964 Function Name Function 1 SD Shutdown SD Shutdown 2 VIN Input Supply VIN Input Supply 3 VOUT 4 ERROR 5 GND Output Voltage ERROR Flag Ground VOUT SENSE/ADJ GND Output Voltage Remote Sense Pin or output Adjust Pin Ground Pin Description for TO220-5 and TO263-5 Packages Pin # 1 LP3961 Name LP3964 Function SD Shutdown 2 VIN Input Supply 3 GND Ground 4 VOUT Output Voltage 5 ERROR www.national.com Name SD VIN GND ERROR Flag 4 VOUT SENSE/ADJ Function Shutdown Input Supply Ground Output Voltage Remote Sense Pin or output Adjust Pin LP3961/LP3964 Ordering Information DS101129-31 Package Type Designator is ″MP″ for SOT223 package, ″T″ for TO220 package, and ″S″ for TO263 package. TABLE 1. Package Marking and Ordering Information Output Voltage Order Number Description (Current, Option) Package Type Package Marking Supplied As: 5.0 LP3961EMP-5.0 800mA, Error Flag SOT223-5 LBSB 1000 units on Tape and Reel 5.0 LP3961EMPX-5.0 800mA, Error Flag SOT223-5 LBSB 2000 units on Tape and Reel 3.3 LP3961EMP-3.3 800mA, Error Flag SOT223-5 LAZB 1000 units on Tape and Reel 3.3 LP3961EMPX-3.3 800mA, Error Flag SOT223-5 LAZB 2000 units on Tape and Reel 2.5 LP3961EMP-2.5 800mA, Error Flag SOT223-5 LBBB 1000 units on Tape and Reel 2.5 LP3961EMPX-2.5 800mA, Error Flag SOT223-5 LBBB 2000 units on Tape and Reel 1.8 LP3961EMP-1.8 800mA, Error Flag SOT223-5 LBAB 1000 units on Tape and Reel 1.8 LP3961EMPX-1.8 800mA, Error Flag SOT223-5 LBAB 2000 units on Tape and Reel 5.0 LP3964EMP-5.0 800mA, SENSE SOT223-5 LBUB 1000 units on Tape and Reel 5.0 LP3964EMPX-5.0 800mA, SENSE SOT223-5 LBUB 2000 units on Tape and Reel 3.3 LP3964EMP-3.3 800mA, SENSE SOT223-5 LBJB 1000 units on Tape and Reel 3.3 LP3964EMPX-3.3 800mA, SENSE SOT223-5 LBJB 2000 units on Tape and Reel 2.5 LP3964EMP-2.5 800mA, SENSE SOT223-5 LBHB 1000 units on Tape and Reel 2.5 LP3964EMPX-2.5 800mA, SENSE SOT223-5 LBHB 2000 units on Tape and Reel 1.8 LP3964EMP-1.8 800mA, SENSE SOT223-5 LBFB 1000 units on Tape and Reel 1.8 LP3964EMPX-1.8 800mA, SENSE SOT223-5 LBFB 2000 units on Tape and Reel ADJ LP3964EMP-ADJ 800mA, ADJ SOT223-5 LBPB 1000 units on Tape and Reel 5 www.national.com LP3961/LP3964 Ordering Information (Continued) TABLE 1. Package Marking and Ordering Information (Continued) Output Voltage Order Number Description (Current, Option) Package Type Package Marking Supplied As: ADJ LP3964EMPX-ADJ 800mA, ADJ SOT223-5 LBPB 2000 units on Tape and Reel 5.0 LP3961ES-5.0 800mA, Error Flag TO263-5 LP3961ES-5.0 Rail 5.0 LP3961ESX-5.0 800mA, Error Flag TO263-5 LP3961ESX-5.0 Tape and Reel 3.3 LP3961ES-3.3 800mA, Error Flag TO263-5 LP3961ES-3.3 Rail 3.3 LP3961ESX-3.3 800mA, Error Flag TO263-5 LP3961ES-3.3 Tape and Reel 2.5 LP3961ES-2.5 800mA, Error Flag TO263-5 LP3961ES-2.5 Rail 2.5 LP3961ESX-2.5 800mA, Error Flag TO263-5 LP3961ES-2.5 Tape and Reel 1.8 LP3961ES-1.8 800mA, Error Flag TO263-5 LP3961ES-1.8 Rail 1.8 LP3961ESX-1.8 800mA, Error Flag TO263-5 LP3961ES-1.8 Tape and Reel 5.0 LP3964ES-5.0 800mA, SENSE TO263-5 LP3964ES-5.0 Rail 5.0 LP3964ESX-5.0 800mA, SENSE TO263-5 LP3964ES-5.0 Tape and Reel 3.3 LP3964ES-3.3 800mA, SENSE TO263-5 LP3964ES-3.3 Rail 3.3 LP3964ESX-3.3 800mA, SENSE TO263-5 LP3964ES-3.3 Tape and Reel 2.5 LP3964ES-2.5 800mA, SENSE TO263-5 LP3964ES-2.5 Rail 2.5 LP3964ESX-2.5 800mA, SENSE TO263-5 LP3964ES-2.5 Tape and Reel 1.8 LP3964ES-1.8 800mA, SENSE TO263-5 LP3964ES-1.8 Rail 1.8 LP3964ESX-1.8 800mA, SENSE TO263-5 LP3964ES-1.8 Tape and Reel ADJ LP3964ES-ADJ 800mA, ADJ TO263-5 LP3964ES-ADJ Rail ADJ LP3964ESX-ADJ 800mA, ADJ TO263-5 LP3964ES-ADJ Tape and Reel 5.0 LP3961ET-5.0 800mA, Error Flag TO220-5 LP3961ET-5.0 Rail 3.3 LP3961ET-3.3 800mA, Error Flag TO220-5 LP3961ET-3.3 Rail 2.5 LP3961ET-2.5 800mA, Error Flag TO220-5 LP3961ET-2.5 Rail 1.8 LP3961ET-1.8 800mA, Error Flag TO220-5 LP3961ET-1.8 Rail 5.0 LP3964ET-5.0 800mA, SENSE TO220-5 LP3964ET-5.0 Rail 3.3 LP3964ET-3.3 800mA, SENSE TO220-5 LP3964ET-3.3 Rail 2.5 LP3964ET-2.5 800mA, SENSE TO220-5 LP3964ET-2.5 Rail 1.8 LP3964ET-1.8 800mA, SENSE TO220-5 LP3964ET-1.8 Rail ADJ LP3964ET-ADJ 800mA, ADJ TO220-5 LP3964ET-ADJ Rail www.national.com 6 IOUT (Survival) Maximum Voltage for ERROR Pin Maximum Voltage for SENSE Pin If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Lead Temperature (Soldering, 5 sec.) ESD Rating (Note 3) Power Dissipation (Note 2) Input Supply Voltage (Survival) Shutdown Input Voltage (Survival) Output Voltage (Survival), (Note 6), (Note 7) Short Circuit Protected VIN+0.3V VOUT+0.3V Operating Ratings −65˚C to +150˚C Input Supply Voltage (Operating) 260˚C 2 kV Internally Limited −0.3V to +7.5V −0.3V to VIN+0.3V Shutdown Input Voltage (Operating) 2.5V to 7.0V −0.3V to VIN+0.3V Maximum Operating Current (DC) Operating Junction Temp. Range 0.8A −40˚C to +125˚C −0.3V to +7.5V Electrical Characteristics LP3961/LP3964 Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT =10µF, VSD = VIN-0.3V. Symbol VO Parameter Output Voltage Tolerance (Note 8) Conditions VOUT+1V < VIN < 7.0V 10 mA < IL < 800 mA 3.135 ≤ VIN ≤ 7.0 for VOUT = 2.5V Typ(Note 4) 0 LP3961/4 (Note 5) Min Max -1.5 -3.0 +1.5 +3.0 Units % ∆V OL Output Voltage Line Regulation (Note 8) VOUT+1V < VIN < 7.0V, 0.02 0.06 % ∆VO/ ∆IOUT Output Voltage Load Regulation (Note 8) 10 mA < IL < 800 mA 0.02 0.08 % VIN VOUT IGND Dropout Voltage (Note 10) Ground Pin Current In Normal Operation Mode IL = 80 mA 24 30 35 IL = 800 mA 240 300 350 IL = 80 mA 3 9 10 IL = 800 mA 4 14 15 25 75 IGND Ground Pin Current In Shutdown Mode (Note 11) VSD ≤ 0.2V 15 IO(PK) Peak Output Current (Note 2) 1.5 1.2 1.1 mV mA µA A SHORT CIRCUIT PROTECTION ISC Short Circuit Current 2.8 A OVER TEMPERATURE PROTECTION Tsh(t) Shutdown Threshold 165 ˚C Tsh(h) Thermal Shutdown Hysteresis 10 ˚C SHUTDOWN INPUT Output = High VIN Output = Low 0 Turn-off delay IL = 800 mA 20 µs Turn-on delay IL = 800 mA 25 µs SD Input Current VSD = VIN 1 nA VSDT Shutdown Threshold TdOFF TdON ISD 7 VIN–0.3 0.2 V www.national.com LP3961/LP3964 Absolute Maximum Ratings (Note 1) LP3961/LP3964 Electrical Characteristics LP3961/LP3964 (Continued) Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT =10µF, VSD = VIN-0.3V. Symbol Parameter Conditions Typ(Note 4) LP3961/4 (Note 5) Units Min Max 10 5 16 % 5 2 8 % ERROR FLAG COMPARATOR VT Threshold VTH Threshold Hysteresis (Note 9) VEF(Sat) Error Flag Saturation Isink = 100µA (Note 9) 0.02 0.1 V Td Flag Reset Delay 1 µs Ilk Error Flag Pin Leakage Current 1 nA VError = 0.5V (over temp.) 1 mA VIN = VOUT + 1.5V COUT = 100uF VOUT = 3.3V 60 VIN = VOUT + 0.3V COUT = 100uF VOUT = 3.3V 40 Imax Error Flag Pin Sink Current AC PARAMETERS PSRR Ripple Rejection dB ρn(l/f Output Noise Density f = 120Hz 0.8 µV en Output Noise Voltage (rms) BW = 10Hz – 100kHz 150 BW = 300Hz – 300kHz 100 µV (rms) Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Charateristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θjA = 50˚C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θjA = 60˚C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. The devices in SOT223 package must be derated at θjA = 90˚C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm. Note 5: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground. Note 7: The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp of peak current. Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Note 9: Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. Note 10: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since the minimum input voltage is 2.5V. Note 11: This specification has been tested for −40˚C ≤ TJ ≤ 85˚C since the temperature rise of the device is negligible under shutdown conditions. www.national.com 8 Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 2.5V, COUT =10µF, IOUT = 10mA, CIN =10µF, VSD = VIN, and TA = 25˚C. Drop-Out Voltage Vs Temperature for Different Load Currents Drop-Out Voltage Vs Temperature for Different Output Voltages (IOUT = 800mA) DS101129-9 Ground Pin Current Vs Input Voltage (VSD=VIN) DS101129-10 Ground Pin Current Vs Input Voltage (VSD=100mV) DS101129-11 Ground Current Vs Temperature (VSD=VIN) DS101129-15 Ground Current Vs Temperature (VSD=0V DS101129-18 DS101129-12 9 www.national.com LP3961/LP3964 Typical Performance Characteristics LP3961/LP3964 Typical Performance Characteristics Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 2.5V, COUT =10µF, IOUT = 10mA, CIN =10µF, VSD = VIN, and TA = 25˚C. (Continued) Ground Pin Current Vs Shutdown Pin Voltage Input Voltage Vs Output Voltage DS101129-17 DS101129-16 Output Noise Density, VOUT= 2.5V Output Noise Density, VOUT= 5V DS101129-13 www.national.com DS101129-14 10 Input Capacitor Selection The LP3961 and LP3964 require a minimum input capacitance of 10µF between the input and ground pins to prevent any impedance interactions with the supply. This capacitor should be located very close to the VIN pin. This capacitor can be of any type such as ceramic, tantalum, or aluminium. Any good quality capacitor which has good tolerance over temperature and frequency is recommended. Output Capacitor Selection The LP3961 and LP3964 require a minimum of 10µF capacitance between the output and ground pins for proper operation. LP3961 and LP3964 work best with Tantalum or Electrolytic capacitor. The output capacitor should have a good tolerance over temperature, voltage, and frequency. Larger capacitance provides better improved load dynamics and noise performance. The output capacitor should be connected very close to the Vout pin. Short-Circuit Protection The LP3961and LP3964 is short circuit protected and in the event of a peak over-current condition, the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on thermal information for power dissipation calculations. Output Adjustment An adjustable output device has output voltage range of 1.215V to 5.1V. To obtain a desired output voltage, the following equation can be used with R1 always a 10kΩ resistor. Error Flag Operation The LP3961/LP3964 produces a logic low signal at the Error Flag pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing diagram in Figure 1 shows the relationship between the ERROR and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the Error Flag. The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high through a pull up resistor. Although the ERROR pin can sink current of 1mA, this current is energy drain from the input supply. Hence, the value of the pull up resistor should be in the range of 100kΩ to 1MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode. For output stability, CF must be between 68pF and 100pF. Output Noise Noise is specified in two waysSpot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and total output noise is measured in µV(rms). The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low fre- 11 www.national.com LP3961/LP3964 quency component and a high frequency component, which depend strongly on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). Using an optimized trade-off of ground pin current and die size, LP3961/LP3964 achieves low noise performance and low quiescent current operation. The total output noise specification for LP3961/LP3964 is presented in the Electrical Characteristics table. The Output noise density at different frequencies is represented by a curve under typical performance characteristics. Applications Information LP3961/LP3964 Applications Information (Continued) DS101129-7 FIGURE 1. Error Flag Operation Sense Pin In applications where the regulator output is not very close to the load, LP3964 can provide better remote load regulation using the SENSE pin. Figure 2 depicts the advantage of the SENSE option. LP3961 regulates the voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resis- tance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the voltage at the remote load will be 3.22V with 800mAmps of load current, ILOAD. The LP3964 regulates the voltage at the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in Figure 2. If the sense option pin is not required, the sense pin must be connected to the VOUT pin. DS101129-8 FIGURE 2. Improving remote load regulation using LP3964 Shutdown Operation A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively terminated through a 10kΩ pull-up resistor for a proper operation. If this www.national.com pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. 12 pends on method of attachment, insulator, etc. θCH varies between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown, 2˚C/W can be assumed. (Continued) Dropout Voltage The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the output voltage. The LP3961/LP3964 use an internal MOSFET with an Rds(on) of 240mΩ (typically). For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET. Heatsinking TO-263 and SOT-223 Packages The TO-263 and SOT223 packages use the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. Figure 3 shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Reverse Current Path The internal MOSFET in LP3961and LP3964 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200mA continuous and 1A peak. Maximum Output Current Capability LP3961 and LP3964 can deliver a continuous current of 800mA over the full operating temperature range. A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND DS101129-32 FIGURE 3. θJA vs Copper(1 Ounce) Area for TO-263 package where IGND is the operating ground current of the device (specified under Electrical Characteristics). The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature(TJmax): TRmax = TJmax− TAmax As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 packag mounted to a PCB is 32˚C/W. Figure 4 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming θJA is 35˚C/W and the maximum junction temperature is 125˚C. The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = TRmax / PD LP3961 and LP3964 are available in TO-220, TO-263, and SOT-223 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 ˚C/W for TO-220 package, ≥60 ˚C/W for TO-263 package, and ≥ 140 ˚C/W for SOT-223 package, no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. Heatsinking TO-220 Packages The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. DS101129-33 FIGURE 4. Maximum power dissipation vs ambient temperature for TO-263 package Figure 5 shows a curve for the θJA of SOT-223 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. In this equation, θCH is the thermal resistance from the junction to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3˚C/W for a TO220 package. The value for θCH de- 13 www.national.com LP3961/LP3964 Applications Information LP3961/LP3964 Applications Information (Continued) DS101129-19 FIGURE 5. θJA vs Copper(1 Ounce) Area for SOT-223 package The following figures show different layout scenarios for SOT-223 package. DS101129-22 FIGURE 8. SCENARIO C, θJA = 92˚C/W DS101129-20 FIGURE 6. SCENARIO A, θJA = 148˚C/W DS101129-21 FIGURE 7. SCENARIO B, θJA = 125˚C/W DS101129-23 FIGURE 9. SCENARIO D, θJA = 83˚C/W www.national.com 14 LP3961/LP3964 Applications Information (Continued) DS101129-25 DS101129-24 FIGURE 11. SCENARIO F, θJA = 75˚C/W FIGURE 10. SCENARIO E, θJA = 77˚C/W DS101129-26 FIGURE 12. SCENARIO G, θJA = 113˚C/W 15 www.national.com LP3961/LP3964 Applications Information (Continued) DS101129-27 FIGURE 13. SCENARIO H, θJA = 79˚C/W www.national.com 16 LP3961/LP3964 Applications Information (Continued) DS101129-28 FIGURE 14. SCENARIO I, θJA = 78.5˚C/W 17 www.national.com LP3961/LP3964 Physical Dimensions inches (millimeters) unless otherwise noted TO220 5-lead, Molded, Stagger Bend Package (TO220-5) NS Package Number T05D For Order Numbers, refer to the “Ordering Information” section of this document. www.national.com 18 LP3961/LP3964 Physical Dimensions inches (millimeters) unless otherwise noted TO263 5-Lead, Molded, Surface Mount Package (TO263-5) NS Package Number TS5B For Order Numbers, refer to the “Ordering Information” section of this document. 19 www.national.com LP3961/LP3964 800mA Fast Ultra Low Dropout Linear Regulators Physical Dimensions inches (millimeters) unless otherwise noted SOT223, 5-Lead, Molded, Surface Mount Package (SOT223-5) NS Package Number MA05C For Order Numbers, refer to the “Ordering Information” section of this document. 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