LP38513 3A Fast Response Ultra Low Dropout Linear Regulator General Description Features The LP38513 fast response ultra low dropout linear regulator operates from a +2.25V to +5.50V input supply. This ultra low dropout linear regulator responds very quickly to step changes in line or load conditions, which makes it suitable for low voltage microprocessor applications. Developed on a CMOS process, with a PMOS pass transistor, the LP38513 has low quiescent current operation that is independent of the output load current. Ground Pin Current: Typically 12 mA at 3A load current. Disable Mode: Typically 60 µA quiescent current when the Enable pin is pulled low. ERROR Flag: The ERROR Flag goes low if VOUT falls more than typically 15% below the nominal value. Precision Output Voltage: A guaranteed VOUT accuracy of ±2.6% with TJ from 0°C to 125°C. ■ ■ ■ ■ ■ ■ ■ ■ Conversions from 2.5V rail to 1.8V Stable with ceramic capacitors Low ground pin current Load regulation of 0.1% for 10 mA to 3A load current 60 μA typical quiescent current in shutdown mode Guaranteed output current of 3A Available in TO220-5 and TO263-5 packages Guaranteed VOUT accuracy of ±2.6% with TJ from 0°C to +125°C ■ ERROR flag indicates VOUT status ■ Over-Temperature and Over-Current protection ■ −40°C to +125°C operating TJ range Applications ■ ■ ■ ■ ■ ■ ■ Microprocessor power supplies GTL, GTL+, BTL, and SSTL bus terminators Power supplies for DSPs SCSI terminator Post regulators Battery chargers Other battery powered applications Typical Application Circuit 20146801 © 2007 National Semiconductor Corporation 201468 www.national.com LP38513 3A Fast Response Ultra Low Dropout Linear Regulator July 2007 LP38513 Ordering Information TABLE 1. Package Marking and Ordering Information Output Voltage Order Number 1.8 LP38513T-1.8 Package Type Package Marking Supplied As: LP38513S-1.8 TO263-5 LP38513S-1.8 Rail LP38513SX-1.8 TO263-5 LP38513S-1.8 Tape and Reel TO220-5 LP38513T-1.8 Rail Connection Diagrams 20146803 20146804 Top View TO-220 5 Pin Package Top View TO-263 5 Pin Package Pin Descriptions for TO-220 and TO-263 5 Pin Packages Pin # TO220-5 and TO263-5 Function EN Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and must be tied to the input voltage, or actively driven. 2 IN Input Supply Pin 3 GND Ground 4 OUT Regulated Output Voltage Pin 5 ERROR TAB TAB 1 www.national.com ERROR Flag. A high level indicates that VOUT is within (tbd)% of the nominal regulated voltage. The TO220 and TO263 TAB is used as a thermal connection to remove heat from the device to an external heatsink. The TAB is internally connected to device pin 3. 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Soldering Temperature (Note 3) TO-220, Wave TO-263 ESD Rating (Note 2) Power Dissipation (Note 4) Input Pin Voltage (Survival) Enable Pin Voltage (Survival) Output Pin Voltage (Survival) ERROR Pin Voltage (Survival) IOUT (Survival) (Note 1) Input Supply Voltage, VIN Enable Input Voltage, VEN ERROR Pin Voltage Output Current (DC) Junction Temperature (Note 4) −65°C to +150°C 260°C, 10s 235°C, 30s ±2 kV Internally Limited −0.3V to +6.0V −0.3V to +6.0V −0.3V to +6.0V 0.3V to +6.0V Internally Limited 2.25V to 5.5V 0.0V to 5.5V 0.0V to VIN 0 mA to 3A −40°C to +125°C Electrical Characteristics Unless otherwise specified: VIN = 2.5V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = 2.0V. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions 2.25V ≤ VIN ≤ 5.5V VOUT Output Voltage Tolerance (Note 7) 10 mA ≤ IOUT ≤ 3A Min Typ Max -1.6 −4.1 0 +1.6 +2.6 2.25V ≤ VIN ≤ 5.5V Units % 10 mA ≤ IOUT ≤ 3A -2.6 0 +2.6 0°C ≤ TJ ≤ 125°C ΔVOUT/ΔVIN Output Voltage Line Regulation (Notes 5, 7) 2.25V ≤ VIN ≤ 5.5V - 0.03 0.06 - %/V ΔVOUT/ΔIOUT Output Voltage Load Regulation (Notes 6, 7) 10 mA ≤ IOUT ≤ 3A - 0.10 0.20 - %/A Dropout Voltage (Note 8) IOUT = 3A - - 425. mV IOUT = 10 mA ERROR pin = GND - 10 12 15 IOUT = 3A ERROR pin = GND - 12 15 20 Ground Pin Current, Output Disabled VEN = 0.50V ERROR pin = GND - 60 100 110 µA Short Circuit Current VOUT = 0V - 5.6 - A 0.74 0.56 0.85 0.92 1.00 V VDO IGND ISC Ground Pin Current, Output Enabled mA Enable Input VEN rising from 0.0V until the output turns On, or VEN falling from ≥ 2.0V until the output turns Off VEN(TH) Enable On/Off Threshold td(OFF) Turn-off delay Time from VEN < VEN(TH) to VOUT = OFF, ILOAD = 3A - 5 - td(ON) Turn-on delay Time from VEN >VEN(TH) to VOUT = ON, ILOAD = 3A - 5 - VEN = VIN - 1 - VEN = 0V - -1 - IEN Enable Pin Current 3 µs nA www.national.com LP38513 Operating Ratings Absolute Maximum Ratings (Note 1) LP38513 Symbol Parameter Conditions Min Typ Max 77 85 94 Units ERROR Flag VTH ERROR Flag Threshold (Note 9) VOUT falling from VOUT(NOM) until ERROR Flag goes low ΔVTH ERROR Flag Threshold Hysteresis (Note 9) VOUT rising from VTH until ERROR Flag goes high VERROR(SAT) ERROR Flag Saturation Voltage Ilk ERROR Flag Pin Leakage Current td ERROR Flag Delay time % 2.2 4 5.8 ISINK = 1 mA - 20 100 mV VERROR = 5.5V - 100 - nA - 1 - µs VIN = 2.5V f = 120Hz - 73 - VIN = 2.5V f = 1 kHz - 70 - Output Noise Density f = 120Hz - 0.8 - µV/√Hz Output Noise Voltage BW = 100Hz – 100kHz VOUT = 1.8V - 45 - µVRMS TJ rising - 165 - - 10 - AC Parameters PSRR ρn(l/f) en Ripple Rejection dB Thermal Characteristics TSD ΔTSD Thermal Shutdown Thermal Shutdown Hysteresis TJ falling from TSD θJ-A Thermal Resistance Junction to Ambient TO-220 (Note 4) - 60 - TO-263 (Note 4) - 60 - θJ-C Thermal Resistance Junction to Case TO-220 - 3 - TO-263 - 3 - °C °C/W °C/W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method is per JESD22-A114. Note 3: Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the temperatures and times are for Sn-Pb (STD) only. Note 4: Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). Note 5: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the voltage at the input. Note 6: Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current at the output. Note 7: The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Note 8: Dropout voltage (VDO) is typically defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. For the LP38513, the minimum operating voltage of 2.25V is the limiting factor and the maximum dropout voltage is defined as: VDO(MAX) = VIN(MIN) - VOUT(MIN) = (i.e. 2.25V - (1.80V x 95.9%) = 524 mV) Note 9: The ERROR Flag thresholds are specified as percentage of the nominal regulated output voltage. See Application Information. www.national.com 4 Unless otherwise specified: TJ = 25°C, VIN = 2.5V, VEN = 2.0V, VOUT vs Temperature VOUT vs VIN 20146811 20146837 Ground Pin Current (IGND) vs VIN Ground Pin Current (IGND) vs Temperature 20146812 20146813 Ground Pin Current(IGND) vs Temperature Enable Threshold vs Temperature 20146816 20146814 5 www.national.com LP38513 Typical Performance Characteristics CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. LP38513 VOUT vs VEN VOUT ERROR Flag Threshold vs Temperature 20146832 20146817 ERROR Flag Low vs Temperature ERROR Flag Leakage vs Temperature 20146818 20146819 Load regulation vs Temperature Line Regulation vs Temperature 20146820 www.national.com 20146821 6 LP38513 Current Limit vs Temperature Load Transient 10mA to 3A, COUT = 10 μF Ceramic 20146822 20146823 Load Transient 10 mA to 3A, COUT = 10 μF Ceramic + 100 μF Aluminum Load Transient 1A to 3A, COUT = 10 μF Ceramic 20146824 20146825 Load Transient 1A to 3A, COUT = 10 μF Ceramic + 100 μF Aluminum Line Transient 20146827 20146826 7 www.national.com LP38513 PSRR Noise 20146829 www.national.com 20146831 8 LP38513 Block Diagram 20146807 Application Information voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output. There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition. While VIN is high enough to keep the control circuity alive, and the Enable pin is above the VEN(ON) threshold, the control circuitry will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full on condition when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. The internal PFET pass element in the LP38513 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output voltage to input voltage differential is more than 500 mV (typical) the parasitic diode becomes forward biased and current flows from the output pin to the input through the diode. The current in the parasitic diode should be limited to less than 1A continuous and 5A peak. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this protective clamp. EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating conditions, a 10 µF ceramic input capacitor will provide satisfactory performance. OUTPUT CAPACITOR: A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be located less than 1 cm from the device and connected directly to the output and ground pin using traces which have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no limitation on any additional capacitance. X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drop severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. SHORT-CIRCUIT PROTECTION The LP38513 is short circuit protected, and in the event of a peak over-current condition the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output 9 www.national.com LP38513 on/off cycling to a lower frequency. Please refer to the POWER DISSIPATION/HEAT-SINKING section for power dissipation calculations. ERROR FLAG OPERATION When the LP38513 Enable pin is high, the ERROR Flag pin will produce a logic low signal when the output drops by more than 15% (VTH, typical) from the nominal output voltage. The drop in output voltage may be due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The output voltage will need to rise to greater than typically 89% of the nominal output voltage for the ERROR Flag to return to a logic high state. It should also be noted that when the Enable pin is pulled low, the ERROR Flag pin is forced to be low as well. The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin requires an external pull-up resistor. The value of the pull-up resistor should be in the range of 2 kΩ to 20 kΩ, and should be connected to the LP38513 output voltage pin. The ERROR Flag pin should not be pulled-up to any voltage source higher than VIN as current flow through an internal parasitic diode may cause unexpected behavior. When the input voltage is less than typically 1.25V the status of the ERROR flag output will not be reliable. The ERROR Flag pin must be connected to ground if this function is not used. The timing diagram in Figure 1 shows the relationship between the ERROR flag and the output voltage when the pullup resistor is connected to the output voltage pin. The timing diagram in Figure 2 shows the relationship between the ERROR flag and the output voltage when the pullup resistor is connected to the input voltage. ENABLE OPERATION The Enable On/Off threshold is typically 850 mV, and has no hysteresis. The voltage signal must rise and fall cleanly, and promptly, through this threshold. The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a single ended device (such as the collector of a discrete transistor) a pull-up resistor to VIN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩ to 100 kΩ resistor can be used as the pull-up or pull-down resistor to establish default condition for the EN pin. The resistor value selected should be appropriate to swamp out any leakage in the external single ended device, as well as any stray capacitance. If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator output), the pull-up, or pull-down, resistor is not required. If the application does not require the Enable function, the pin should be connected directly to the adjacent VIN pin. The status of the Enable pin also affects the behavior of the ERROR Flag. While the Enable pin is high the regulator control loop will be active and the ERROR Flag will report the status of the output voltage. When the Enable pin is taken low the regulator control loop is shutdown, the output is turned off, and the internal logic will immediately force the ERROR Flag pin low. 20146808 FIGURE 1. ERROR Flag Operation, see Typical Application www.national.com 10 LP38513 20146834 FIGURE 2. ERROR Flag Operation, biased from VIN If a copper plane is to be used, the values of θJA will be the same as shown in the next section for the TO263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, POWER DISSIPATION/HEAT-SINKING A heat-sink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient temperature (TA(MAX))of the application, and the thermal resistance (θJA) of the package. Under all possible conditions, the junction temperature (TJ) must be within the range specified in the Operating Ratings. The total power dissipation of the device is given by: PD = ( (VIN−VOUT) x IOUT) + ((VIN) x IGND) θHA ≤ θJA − θCH − θJC In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. The rated θJC is about 3°C/W for a TO220–5 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed. (1) where IGND is the operating ground current of the device (specified under Electrical Characteristics). The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient temperature (TA (MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)): ΔTJ = TJ(MAX)− TA(MAX) HEAT-SINKING THE TO-263 PACKAGE The TO-263 package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the copper plane for heat sinking. Figure 3 shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. (2) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = ΔTJ / PD(MAX) (4) (3) LP38513 is available in TO-220 and TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W for TO-220 package and ≥ 60 °C/W for TO-263 package no heat-sink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. HEAT-SINKING THE TO-220 PACKAGE The thermal resistance of a TO-220 package can be reduced by attaching it to a heat-sink or a copper plane on a PC board. 11 www.national.com LP38513 Figure 4 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. 20146835 FIGURE 3. θJA vs Copper (1 Ounce) Area for the TO-263 package As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 package mounted to a PCB is 32°C/W. www.national.com 20146836 FIGURE 4. Maximum Power Dissipation vs Ambient Temperature for the TO-263 Package 12 LP38513 Physical Dimensions inches (millimeters) unless otherwise noted TO220 5-lead, Molded, Stagger Bend Package NS Package Number T05D TO263 5-Lead, Molded, Surface Mount Package NS Package Number TS5B 13 www.national.com LP38513 3A Fast Response Ultra Low Dropout Linear Regulator Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. 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