LM4950
7.5W Mono-BTL or 3.1W Stereo Audio Power Amplifier
General Description
Key Specifications
The LM4950 is a dual audio power amplifier primarily designed for demanding applications in flat panel monitors and
TV’s. It is capable of delivering 3.1 watts per channel to a 4Ω
single-ended load with less than 1% THD+N or 7.5 watts
mono BTL to an 8Ω load, with less than 10% THD+N from a
12VDC power supply.
Boomer audio power amplifiers were designed specifically to
provide high quality output power with a minimal amount of
external components. The LM4950 does not require bootstrap capacitors or snubber circuits. Therefore, it is ideally
suited for display applications requiring high power and minimal size.
The LM4950 features a low-power consumption active-low
shutdown mode. Additionally, the LM4950 features an internal thermal shutdown protection mechanism along with short
circuit protection.
The LM4950 contains advanced pop & click circuitry that
eliminates noises which would otherwise occur during
turn-on and turn-off transitions.
The LM4950 is a unity-gain stable and can be configured by
external gain-setting resistors.
j Quiscent Power Supply Current
16mA (typ)
j POUT (SE)
VDD = 12V, RL = 4Ω, 1% THD+N
3.1W (typ)
j POUT (BTL)
VDD = 12V, RL = 8Ω, 10% THD+N
j Shutdown current
7.5W (typ)
40µA (typ)
Features
n Pop & click circuitry eliminates noise during turn-on and
turn-off transitions
n Low current, active-low shutdown mode
n Low quiescent current
n Stereo 3.1W output, RL = 4Ω
n Mono 7.5W BTL output, RL = 8Ω
n Short circuit protection
n Unity-gain stable
n External gain configuration capability
Applications
n Flat Panel Monitors
n Flat panel TV’s
n Computer Sound Cards
Typical Application
20047078
FIGURE 1. Typical Bridge-Tied-Load (BTL) Audio Amplifier Application Circuit
Boomer ® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS200470
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LM4950 7.5W Mono-BTL or 3.1W Stereo Audio Power Amplifier
August 2004
LM4950
Connection Diagrams
Plastic Package, TO-263
20047070
Top View
U = Wafer Fab Code
Z = Assembly Plant Code
XY = Date Code
TT = Die Traceability
Order Number LM4950TS
See NS Package Number TS9A
Plastic Package, TO-220
20047071
Top View
U = Wafer Fab Code
Z = Assembly Plant Code
XY = Date Code
TT = Die Traceability
Order Number LM4950TA
See NS Package Number TA09A
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2
Junction Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Thermal Resistance
Supply Voltage (pin 6, referenced
to GND, pins 4 and 5)
150˚C
θJC (TS)
4˚C/W
θJA (TS) (Note 3)
20˚C/W
θJC (TA)
18.0V
Storage Temperature
4˚C/W
θJA (TA) (Note 3)
20˚C/W
−65˚C to +150˚C
Input Voltage
Operating Ratings
−0.3V to VDD + 0.3V
pins 3 and 7
pins 1, 2, 8, and 9
Temperature Range
−0.3V to 9.5V
Power Dissipation (Note 3)
TMIN ≤ TA ≤ TMAX
Internally limited
ESD Susceptibility (Note 4)
2000V
ESD Susceptibility (Note 5)
200V
−40˚C ≤ T
A
≤ 85˚C
9.6V ≤ VDD ≤ 16V
Supply Voltage
Electrical Characteristics VDD = 12V (Notes 1, 2)
The following specifications apply for VDD = 12V, AV = 0dB (SE) or 6dB (BTL) unless otherwise specified. Limits apply for TA =
25˚C.
Symbol
Parameter
Conditions
LM4950
Typical
(Note 6)
Limit
(Notes 7, 8)
IDD
Quiescent Power Supply Current
VIN = 0V, IO = 0A, No Load
16
30
Units
(Limits)
mA (max)
ISD
Shutdown Current
VSHUTDOWN = GND (Note 9)
40
80
µA (max)
VOS
Offset Voltage
VIN = 0V, RL = 8Ω
5
30
mV (max)
VSDIH
Shutdown Voltage Input High
2.0
VDD/2
V (min)
V (max)
VSDIL
Shutdown Voltage Input Low
0.4
V (max)
TWU
Wake-up Time
150
190
˚C (min)
˚C (max)
3.0
W (min)
TSD
Thermal Shutdown Temperature
PO
Output Power
THD+N
Total Harmomic Distortion + Noise
CB = 10µF
440
170
f = 1kHz
RL = 4Ω SE, Single Channel,
THD+N = 1%
RL = 8Ω BTL, THD+N = 10%
3.1
7.5
PO = 2.5Wrms; f = 1kHz;
RL = 4Ω SE
0.05
PO = 2.5Wrms; AV = 10; f = 1kHz;
RL = 4Ω, SE
0.14
eOS
Output Noise
A-Weighted Filter, VIN = 0V,
Input Referred
XTALK
Channel Separation
fIN = 1kHz, PO = 1W, SE Mode
RL = 8Ω
RL = 4Ω
ms
%
10
µV
76
70
dB
PSRR
Power Supply Rejection Ratio
VRIPPLE = 200mVp-p, f = 1kHz,
RL = 8Ω, BTL
70
IOL
Output Current Limit
VIN = 0V, RL = 500mΩ
5
56
dB (min)
A
Note 1: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is P DMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is lower. For the LM4950 typical application (shown
in Figure 1) with VDD = 12V, RL = 4Ω stereo operation the total power dissipation is 3.65W. θJA = 20˚C/W for both TO263 and TO220 packages mounted to 16in2
heatsink surface area.
Note 4: Human body model, 100pF discharged through a 1.5 kΩ resistor.
Note 5: Machine Model, 220pF–240pF discharged through all pins.
3
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LM4950
Absolute Maximum Ratings (Notes 1, 2)
LM4950
Electrical Characteristics VDD = 12V (Notes 1, 2)
(Continued)
Note 6: Typicals are measured at 25˚C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Shutdown current is measured in a normal room environment. The Shutdown pin should be driven as close as possible to GND for minimum shutdown
current.
20047072
FIGURE 2. Typical Stereo Single-Ended (SE) Audio Amplifier Application Circuit
External Components Description
Components
Refer to (Figure 1.)
Functional Description
1. RIN
This is the inverting input resistance that, along with RF, sets the closed-loop gain. Input resistance RIN
and input capacitance CIN form a high pass filter. The filter’s cutoff frequency is fc = 1/(2πRINCIN).
2. CIN
This is the input coupling capacitor. It blocks DC voltage at the amplifier’s inverting input. CIN and RIN
create a highpass filter. The filter’s cutoff frequency is fC = 1/(2πRINCIN). Refer to the SELECTING
EXTERNAL COMPONENTS, for an explanation of determining CIN’s value.
3. RF
This is the feedback resistance that, along with Ri, sets closed-loop gain.
4. CS
The supply bypass capacitor. Refer to the POWER SUPPLY BYPASSING section for information about
properly placing, and selecting the value of, this capacitor.
5. CBYPASS
This capacitor filters the half-supply voltage present on the BYPASS pin. Refer to the Application section,
SELECTING EXTERNAL COMPONENTS, for information about properly placing, and selecting the
value of, this capacitor.
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4
LM4950
Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
200470B2
200470B3
VDD = 12V, RL = 8Ω,
BTL operation, POUT = 1W
VDD = 12V, RL = 8Ω,
BTL operation, POUT = 3W
THD+N vs Frequency
THD+N vs Frequency
200470B4
200470D5
VDD = 12V, RL = 8Ω,
BTL operation, POUT = 5W
VDD = 12V, RL = 8Ω,
BTL operation, BTLAV = 20, POUT = 1W
THD+N vs Frequency
THD+N vs Frequency
200470D4
200470D6
VDD = 12V, RL = 8Ω,
BTL operation, BTLAV = 20, POUT = 3W
VDD = 12V, RL = 8Ω,
BTL operation, BTLAV = 20, POUT = 5W
5
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LM4950
Typical Performance Characteristics
(Continued)
THD+N vs Frequency
THD+N vs Frequency
20047099
200470A0
VDD = 12V, RL = 4Ω, SE operation,
both channels driven and loaded (average shown),
POUT = 1W, AV = 1
VDD = 12V, RL = 4Ω, SE operation,
both channels driven and loaded (average shown),
POUT = 2.5W, AV = 1
THD+N vs Frequency
THD+N vs Output Power
200470A1
200470A9
VDD = 12V, RL = 8Ω, SE operation,
both channels driven and loaded (average shown),
POUT = 1W, AV = 1
VDD = 12V, RL = 8Ω,
BTL operation, fIN = 1kHz
THD+N vs Output Power
THD+N vs Output Power
200470D0
200470D1
VDD = 12V, RL = 8Ω,
BTL operation, BTLAV = 20, fIN = 1kHz
VDD = 12V, RL = 16Ω,
BTL operation, BTLAV = 20, fIN = 1kHz
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6
LM4950
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
THD+N vs Output Power
200470D9
200470E0
VDD = 12V, RL = 4Ω, SE operation,
both channels driven and loaded (average shown),
fIN = 1kHz
VDD = 12V, RL = 8Ω, SE operation,
both channels driven and loaded (average shown),
fIN = 1kHz
THD+N vs Output Power
THD+N vs Output Power
200470E1
200470C7
VDD = 12V, RL = 16Ω, SE operation,
both channels driven and loaded (average shown),
fIN = 1kHz
VDD = 12V, RL = 4Ω, SE operation, AV = 10
both channels driven and loaded (average shown),
fIN = 1kHz
THD+N vs Output Power
Output Power vs Power Supply Voltage
200470C3
200470C6
RL = 8Ω, BTL, fIN = 1kHz,
at (from top to bottom at 12V): THD+N = 10%
THD+N = 1%, THD+N = 0.2%
VDD = 12V, RL = 8Ω, SE operation, AV = 10
both channels driven and loaded (average shown),
fIN = 1kHz
7
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LM4950
Typical Performance Characteristics
(Continued)
Output Power vs Power Supply Voltage
Output Power vs Power Supply Voltage
200470C5
200470C4
RL = 4Ω, SE operation,
both channels driven and loaded (average shown),
at (from top to bottom at 12V): THD+N = 10%,
THD+N = 1%
RL = 8Ω, SE operation, fIN = 1kHz,
both channels driven and loaded (average shown),
at (from top to bottom at 12V): THD+N = 10%,
THD+N = 1%
Power Supply Rejection vs Frequency
Power Supply Rejection vs Frequency
200470B9
200470B8
VDD = 12V, RL = 8Ω, BTL operation,
VRIPPLE = 200mVp-p, at (from top to bottom at 60Hz):
CBYPASS = 1µF, CBYPASS = 4.7µF, CBYPASS = 10µF,
VDD = 12V, RL = 8Ω, SE operation,
VRIPPLE = 200mVp-p, at (from top to bottom at 60Hz):
CBYPASS = 1µF, CBYPASS = 4.7µF, CBYPASS = 10µF,
Power Supply Rejection vs Frequency
Power Supply Rejection vs Frequency
200470D7
200470D8
VDD = 12V, RL = 8Ω, BTL operation, VRIPPLE = 200mVp-p,
AV = 20, at (from top to bottom at 60Hz):
CBYPASS = 1µF, CBYPASS = 4.7µF, CBYPASS = 10µF
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VDD = 12V, RL = 8Ω, SE operation, VRIPPLE = 200mVp-p,
AV = 10, at (from top to bottom at 60Hz):
CBYPASS = 1µF, CBYPASS = 4.7µF, CBYPASS = 10µF
8
(Continued)
Total Power Dissipation vs Load Dissipation
Total Power Dissipation vs Load Dissipation
20047084
20047081
VDD = 12V, BTL operation, fIN = 1kHz,
at (from top to bottom at 3W):
RL = 8Ω, RL = 16Ω
VDD = 12V, SE operation, fIN = 1kHz,
at (from top to bottom at 1W):
RL = 4Ω, RL = 8Ω
Output Power vs Load Resistance
Output Power vs Load Resistance
20047094
20047091
VDD = 12V, BTL operation, fIN = 1kHz,
at (from top to bottom at 15Ω):
THD+N = 10%, THD+N = 1%
VDD = 12V, SE operation, fIN = 1kHz,
both channels driven and loaded, at (from top to bottom
at 15Ω):
THD+N = 10%, THD+N = 1%
Channel-to-Channel Crosstalk vs Frequency
Channel-to-Channel Crosstalk vs Frequency
20047098
200470A3
VDD = 12V, RL = 4Ω, POUT = 1W, SE operation,
at (from top to bottom at 1kHz): VINB driven,
VOUTA measured; VINA driven, VOUTB measured
VDD = 12V, RL = 8Ω, POUT = 1W, SE operation,
at (from top to bottom at 1kHz): VINB driven,
VOUTA measured; VINA driven, VOUTB measured
9
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LM4950
Typical Performance Characteristics
LM4950
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
THD+N vs Output Power
200470B5
200470E2
VDD = 9.6V, RL = 8Ω,
BTL operation, fIN = 1kHz
VDD = 9.6V, RL = 4Ω,
SE operation, fIN = 1kHz
both channels driven and loaded (average shown)
THD+N vs Output Power
THD+N vs Output Power
200470D2
200470C8
VDD = 9.6V, RL = 8Ω, BTL operation,
BTLAV = 20, fIN = 1kHz
VDD = 9.6V, RL = 4Ω, SE operation,
AV = 10, fIN = 1kHz
both channels driven and loaded (average shown)
Total Power Dissipation vs Load Dissipation per
Channel
Total Power Dissipation vs Load Dissipation
20047085
20047082
VDD = 9.6V, BTL operation, fIN = 1kHz
at (from top to bottom at 2W):
RL = 8Ω, RL = 16Ω
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VDD = 9.6V, SE operation, fIN = 1kHz,
at (from top to bottom at 1W):
RL = 4Ω, RL = 8Ω
10
LM4950
Typical Performance Characteristics
(Continued)
Output Power vs Load Resistance
Output Power vs Load Resistance
20047095
20047092
VDD = 9.6V, BTL operation, fIN = 1kHz,
at (from top to bottom at 15Ω):
THD+N = 10%, THD+N = 1%
VDD = 9.6V, SE operation, fIN = 1kHz,
both channels driven and loaded, at (from top to bottom
at 15Ω):
THD+N = 10%, THD+N = 1%
Channel-to Channel Crosstalk vs Frequency
Channel-to Channel Crosstalk vs Frequency
20047096
200470A4
VDD = 9.6V, RL = 4Ω, POUT = 1W, SE operation,
at (from top to bottom at 1kHz): VINB driven, VOUTA
measured; VINA driven, VOUTB measured
VDD = 9.6V, RL = 8Ω, POUT = 1W, SE operation,
at (from top to bottom at 1kHz): VINB driven, VOUTA
measured; VINA driven, VOUTB measured
THD+N vs Output Power
THD+N vs Output Power
200470C0
200470C2
VDD = 15V, RL = 8Ω,
BTL operation, fIN = 1kHz
VDD = 15V, RL = 4Ω,
SE operation, fIN = 1kHz
both channels driven and loaded (average shown)
11
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LM4950
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
Total Power Dissipation vs Load Dissipation
20047083
VDD = 15V, BTL operation, fIN = 1kHz,
at (from top to bottom at 4W): RL = 8Ω, RL = 16Ω
200470E3
VDD = 15V, RL = 8Ω,
SE operation, fIN = 1kHz
both channels driven and loaded (average shown)
Total Power Dissipation vs Load Dissipation per
Channel
Output Power vs Load Resistance
20047093
20047080
VDD = 15V, SE operation, fIN = 1kHz,
at (from top to bottom at 2W): RL = 4Ω, RL = 8Ω
VDD = 15V, BTL operation, fIN = 1kHz,
at (from top to bottom at 15Ω):
THD+N = 10%, THD+N = 1%
Output Power vs Load Resistance
THD+N vs Output Power
20047090
200470B6
VDD = 15V, SE operation, fIN = 1kHz,
both channels driven and loaded,
at (from top to bottom at 15Ω): THD+N = 10%, THD+N =
1%
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VDD = 16V, RL = 8Ω,
BTL operation, fIN = 1kHz
12
LM4950
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
THD+N vs Output Power
200470D3
200470C9
VDD = 16V, RL = 8Ω,
BTL operation, fIN = 1kHz, BTLAV = 20
VDD = 16V, RL = 4Ω, AV = 10
SE operation, fIN = 1kHz,
both channels driven and loaded (average shown)
Channel-to-Channel Crosstalk vs Frequency
Channel-to-Channel Crosstalk vs Frequency
20047097
200470A2
VDD = 16V, RL = 4Ω, POUT = 1W, SE operation
at (from top to bottom at 1kHz): VINB driven, VOUTA
measured;
VINA driven, VOUTB measured
VDD = 16V, RL = 8Ω, POUT = 1W, SE operation
at (from top to bottom at 1kHz): VINB driven, VOUTA
measured;
VINA driven, VOUTB measured
Power Supply Current vs Power Supply Voltage
Power Supply Current vs Power Supply Voltage
200470A6
200470A7
RL = 8Ω, BTL operation
VIN = 0V, RSOURCE = 50Ω
RL = 4Ω, SE operation
VIN = 0V, RSOURCE = 50Ω
13
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LM4950
Typical Performance Characteristics
(Continued)
Clipping Voltage vs Power Supply Voltage
Clipping Voltage vs Power Supply Voltage
20047088
20047086
RL = 8Ω, BTL operation, fIN = 1kHz
at (from top to bottom at 12V):
positive signal swing, negative signal swing
RL = 16Ω, BTL operation, fIN = 1kHz
at (from to bottom at 12V):
positive signal swing, negative signal swing
Clipping Voltage vs Power Supply Voltage
Clipping Voltage vs Power Supply Voltage
20047089
20047087
RL = 4Ω, SE operation, fIN = 1kHz
both channels driven and loaded, at (from top to bottom
at 13V):
negative signal swing, positive signal swing
RL = 8Ω, SE operation, fIN = 1kHz
both channels driven and loaded, at (from to bottom at
13V):
negative signal swing, positive signal swing
Power Dissipation vs Ambient Temperature
Power Dissipation vs Ambient Temperature
200470E4
200470E6
VDD = 12V, RL = 8Ω (SE), fIN = 1kHz,
(from to bottom at 120˚C): 16in2 copper plane heatsink
area,
8in2 copper plane heatsink area
VDD = 12V, RL = 8Ω (BTL), fIN = 1kHz,
(from to bottom at 80˚C): 16in2 copper plane heatsink
area,
8in2 copper plane heatsink area
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14
LM4950
Application Information
HIGH VOLTAGE BOOMER WITH INCREASED OUTPUT
POWER
Unlike previous 5V Boomer ® amplifiers, the LM4950 is designed to operate over a power supply voltages range of
9.6V to 16V. Operating on a 12V power supply, the LM4950
will deliver 7.5W into an 8Ω BTL load with no more than 10%
THD+N.
20047078
FIGURE 3. Typical LM4950 BTL Application Circuit
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped. To ensure minimum
output signal clipping when choosing an amplifier’s closedloop gain, refer to the AUDIO POWER AMPLIFIER DESIGN
section.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
AMP1’s and AMP2’s outputs at half-supply. This eliminates
the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a
typical single-ended configuration forces a single-supply amplifier’s half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently
damage loads such as speakers.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 3, the LM4950 consists of two operational amplifiers that drive a speaker connected between
their outputs. The value of external input and feedback resistors determine the gain of each amplifier. Resistors RINA
and RFA set the closed-loop gain of AMPA, whereas two
20kΩ resistors set AMPB’s gain to -1. The LM4950 drives a
load, such as a speaker, connected between the two amplifier outputs, VOUTA and VOUTB. Figure 3 shows that
AMPA’s output serves as AMPB’s input. This results in both
amplifiers producing signals identical in magnitude, but 180˚
out of phase. Taking advantage of this phase difference, a
load is placed between AMPA and AMPB and driven differentially (commonly referred to as "bridge mode"). This results in a differential, or BTL, gain of
AVD = 2(Rf / Ri)
(1)
POWER DISSIPATION
Power dissipation is a major concern when
successful single-ended or bridged amplifier.
states the maximum power dissipation point
ended amplifier operating at a given supply
driving a specified output load.
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing
15
designing a
Equation (2)
for a singlevoltage and
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LM4950
Application Information
PDMAX-SE = (VDD)
2
/ (2π2RL):
additional copper area around the package, with connections to the ground pins, supply pin and amplifier output pins.
Refer to the Typical Performance Characteristics curves
for power dissipation information at lower output power levels.
(Continued)
Single Ended
(2)
The LM4950’s dissipation is twice the value given by Equation (2) when driving two SE loads. For a 12V supply and two
8Ω SE loads, the LM4950’s dissipation is 1.82W.
The LM4950’s dissipation when driving a BTL load is given
by Equation (3). For a 12V supply and a single 8Ω BTL load,
the dissipation is 3.65W.
PDMAX-MONOBTL = 4(VDD)
2
/ 2π2RL:
POWER SUPPLY VOLTAGE LIMITS
Continuous proper operation is ensured by never exceeding
the voltage applied to any pin, with respect to ground, as
listed in the Absolute Maximum Ratings section.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a voltage regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator’s output, reduce noise on the supply
line, and improve the supply’s transient response. However,
their presence does not eliminate the need for a local 1.0µF
tantalum bypass capacitance connected between the
LM4950’s supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so may cause oscillation. Keep the length of leads and traces that connect
capacitors between the LM4950’s power supply pin and
ground as short as possible. Connecting a 10µF capacitor,
CBYPASS, between the BYPASS pin and ground improves
the internal bias voltage’s stability and improves the amplifier’s PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however,
increases turn-on time and can compromise the amplifier’s
click and pop performance. The selection of bypass capacitor values, especially CBYPASS, depends on desired PSRR
requirements, click and pop performance (as explained in
the section, SELECTING EXTERNAL COMPONENTS),
system cost, and size constraints.
Bridge Mode (3)
The maximum power dissipation point given by Equation (3)
must not exceed the power dissipation given by Equation
(4):
PDMAX’ = (TJMAX - TA) / θJA
(4)
The LM4950’s TJMAX = 150˚C. In the TS package, the
LM4950’s θJA is 20˚C/W when the metal tab is soldered to a
copper plane of at least 16in2. This plane can be split between the top and bottom layers of a two-sided PCB. Connect the two layers together under the tab with a 5x5 array of
vias. For the TA package, use an external heatsink with a
thermal impedance that is less than 20˚C/W. At any given
ambient temperature TA, use Equation (4) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (4) and substituting PDMAX for
PDMAX’ results in Equation (5). This equation gives the maximum ambient temperature that still allows maximum stereo
power dissipation without violating the LM4950’s maximum
junction temperature.
TA = TJMAX - PDMAX-MONOBTLθJA
MICRO-POWER SHUTDOWN
The LM4950 features an active-low micro-power shutdown
mode. When active, the LM4950’s micro-power shutdown
feature turns off the amplifier’s bias circuitry, reducing the
supply current. The low 40µA typical shutdown current is
achieved by applying a voltage to the SHUTDOWN pin that
is as near to GND as possible. A voltage that is greater than
GND may increase the shutdown current.
There are a few methods to control the micro-power shutdown. These include using a single-pole, single-throw switch
(SPST), a microprocessor, or a microcontroller. When using
a switch, connect a 100kΩ pull-up resistor between the
SHUTDOWN pin and VDD and a second 100kΩ resistor in
parallel with the SPST switch connected between the SHUTDOWN pin and GND. The two resistors form a voltage
divider that ensures that the voltage applied to the SHUTDOWN pin does not exceed VDD/2. Select normal amplifier
operation by opening the switch. Closing the switch applies
GND to the SHUTDOWN pin, activating micro-power shutdown. The switch and resistor guarantee that the SHUTDOWN pin will not float. This prevents unwanted state
changes. In a system with a microprocessor or a microcontroller, use a digital output to apply the active-state voltage to
the SHUTDOWN pin. Again, ensure that the microcontroller
or microprocessor logic-high signal does not exceed the
LM4950’s VDD/2 SHUTDOWN signal limit.
(5)
For a typical application with a 12V power supply and a BTL
8Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the
maximum junction temperature is approximately 77˚C for the
TS package.
TJMAX = PDMAX-MONOBTLθJA + TA
(6)
Equation (6) gives the maximum junction temperature
TJMAX. If the result violates the LM4950’s 150˚C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is operating
around the maximum power dissipation point. Since internal
power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty
cycle decreases.
If the result of Equation (3) is greater than that of Equation
(4), then decrease the supply voltage, increase the load
impedance, or reduce the ambient temperature. Further,
ensure that speakers rated at a nominal 4Ω (SE operation)
or 8Ω (BTL operation) do not fall below 3Ω or 6Ω, respectively. If these measures are insufficient, a heat sink can be
added to reduce θJA. The heat sink can be created using
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16
controlled manner. Ideally, the input and outputs track the
voltage applied to the BYPASS pin. The gain of the internal
amplifiers remains unity until the voltage applied to the BYPASS pin.
The gain of the internal amplifiers remains unity until the
voltage on the bypass pin reaches VDD/2. As soon as the
voltage on the bypass pin is stable, the device becomes fully
operational and the amplifier outputs are reconnected to
their respective output pins. Although the BYPASS pin current cannot be modified, changing the size of CBYPASS alters
the device’s turn-on time. Here are some typical turn-on
times for various values of CBYPASS:
(Continued)
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Two quantities determine the value of the input coupling
capacitor: the lowest audio frequency that requires amplification and desired output transient suppression.
As shown in Figure 3, the input resistor (RIN) and the input
capacitor (CIN) produce a high pass filter cutoff frequency
that is found using Equation (7).
(7)
fc = 1/2πRiCi
As an example when using a speaker with a low frequency
limit of 50Hz, Ci, using Equation (7) is 0.159µF. The 0.39µF
CINA shown in Figure 3 allows the LM4950 to drive high
efficiency, full range speaker whose response extends below
30Hz.
Bypass Capacitor Value
Besides minimizing the input capacitor size, careful consideration should be paid to value of CBYPASS, the capacitor
connected to the BYPASS pin. Since CBYPASS determines
how fast the LM4950 settles to quiescent operation, its value
is critical when minimizing turn-on pops. The slower the
LM4950’s outputs ramp to their quiescent DC voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CBYPASS
equal to 10µF along with a small value of CIN (in the range of
0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing CIN no larger
than necessary for the desired bandwidth helps minimize
clicks and pops.
CB (µF)
TON (ms)
1.0
120
2.2
120
4.7
200
10
440
In order eliminate "clicks and pops", all capacitors must be
discharged before turn-on. Rapidly switching VDD may not
allow the capacitors to fully discharge, which may cause
"clicks and pops".
There is a relationship between the value of CIN and
CBYPASS that ensures minimum output transient when power
is applied or the shutdown mode is deactivated. Best performance is achieved by setting the time constant created by
CIN and Ri + Rf to a value less than the turn-on time for a
given value of CBYPASS as shown in the table above.
DRIVING PIEZO-ELECTRIC SPEAKER TRANSDUCERS
The LM4950 is able to drive capacitive piezo-electric transducer loads that are less than equal to 200nF. Stable operation is assured by placing 33pF capacitors in parallel with the
20kΩ feedback resistors. The additional capacitors are
shown in Figure 4.
When driving piezo-electric tranducers, sound quality and
accoustic power is entirely dependent upon a transducer’s
frequency response and efficiency. In this application, power
dissipated by the LM4950 is very low, typically less than
250mW when driving a 200nF piezo-electric transduce
(VDD = 12V).
OPTIMIZING CLICK AND POP REDUCTION
PERFORMANCE
The LM4950 contains circuitry that eliminates turn-on and
shutdown transients ("clicks and pops"). For this discussion,
turn-on refers to either applying the power supply voltage or
when the micro-power shutdown mode is deactivated.
As the VDD/2 voltage present at the BYPASS pin ramps to its
final value, the LM4950’s internal amplifiers are configured
as unity gain buffers and are disconnected from the AMPA
and AMPB pins. An internal current source charges the capacitor connected between the BYPASS pin and GND in a
17
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LM4950
Application Information
LM4950
Application Information
(Continued)
20047079
FIGURE 4. Piezo-electric Transducer Capacitance ≤ 200nF
supply voltage must also not create a situation that violates
of maximum power dissipation as explained above in the
Power Dissipation section. After satisfying the LM4950’s
power dissipation requirements, the minimum differential
gain needed to achieve 4W dissipation in an 8Ω BTL load is
found using Equation (10).
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 4W into an 8Ω BTL
The following are the desired operational parameters:
Power Output
4WRMS
Load Impedance
Input Level
8Ω
0.3VRMS (max)
Input Impedance
20kΩ
(10)
Bandwidth
50Hz–20kHz ± 0.25dB
The design begins by specifying the minimum supply voltage
necessary to obtain the specified output power. One way to
find the minimum supply voltage is to use the Output Power
vs Power Supply Voltage curve in the Typical Performance
Characteristics section. Another way, using Equation (8), is
to calculate the peak output voltage necessary to achieve
the desired output power for a given load impedance. To
account for the amplifier’s dropout voltage, two additional
voltages, based on the Clipping Dropout Voltage vs Power
Supply Voltage in the Typical Performance Characteristics curves, must be added to the result obtained by Equation (8). The result is Equation (9).
Thus, a minimum gain of 18.9 allows the LM4950’s to reach
full output swing and maintain low noise and THD+N performance. For this example, let AV-BTL = 19. The amplifier’s
overall BTL gain is set using the input (RINA) and feedback
(R) resistors of the first amplifier in the series BTL configuration. Additionaly, AV-BTL is twice the gain set by the first
amplifier’s RIN and Rf. With the desired input impedance set
at 20kΩ, the feedback resistor is found using Equation (11).
Rf / RIN = AV-BTL / 2
(11)
The value of Rf is 190kΩ (choose 191kΩ, the closest value).
The nominal output power is 4W.
(8)
VDD = VOUTPEAK + VODTOP + VODBOT
The last step in this design example is setting the amplifier’s
-3dB frequency bandwidth. To achieve the desired ± 0.25dB
pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the lower bandwidth
limit and the high frequency response must extend to at least
five times the upper bandwidth limit. The gain variation for
both response limits is 0.17dB, well within the ± 0.25dBdesired limit. The results are an
(9)
The Output Power vs. Power Supply Voltage graph for an 8Ω
load indicates a minimum supply voltage of 10.2V. The commonly used 12V supply voltage easily meets this. The additional voltage creates the benefit of headroom, allowing the
LM4950 to produce peak output power in excess of 4W
without clipping or other audible distortion. The choice of
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fL = 50Hz / 5 = 10Hz
18
(12)
upper passband response limit. With AVD = 7 and fH =
100kHz, the closed-loop gain bandwidth product (GBWP) is
700kHz. This is less than the LM4950’s 3.5MHz GBWP. With
this margin, the amplifier can be used in designs that require
more differential gain while avoiding performance restricting
bandwidth limitations.
(Continued)
and an
fL = 20kHz x 5 = 100kHz
(13)
RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT
Figure 5 through Figure 7 show the recommended two-layer
PC board layout that is optimized for the TO263-packaged,
SE-configured LM4950 and associated external components. Figure 8 through Figure 10 show the recommended
two-layer PC board layout that is optimized for the TO263packaged, BTL-configured LM4950 and associated external
components. These circuits are designed for use with an
external 12V supply and 4Ω(min)(SE) or 8Ω(min)(BTL)
speakers.
As mentioned in the SELECTING EXTERNAL COMPONENTS section, RINA and CINA create a highpass filter that
sets the amplifier’s lower bandpass frequency limit. Find the
coupling capacitor’s value using Equation (14).
Ci = 1 / 2πRINfL
(14)
The result is
These circuit boards are easy to use. Apply 12V and ground
to the board’s VDD and GND pads, respectively. Connect a
speaker between the board’s OUTA and OUTBoutputs.
1 / (2πx20kΩx10Hz) = 0.795µF
Use a 0.82µF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in
this example) and the differential gain AVD, determines the
Demonstration Board Layout
20047063
FIGURE 5. Recommended TS SE PCB Layout:
Top Silkscreen
19
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LM4950
Application Information
LM4950
Demonstration Board Layout
(Continued)
20047064
FIGURE 6. Recommended TS SE PCB Layout:
Top Layer
20047065
FIGURE 7. Recommended TS SE PCB Layout:
Bottom Layer
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20
LM4950
Demonstration Board Layout
(Continued)
20047066
FIGURE 8. Recommended TS BTL PCB Layout:
Top Silkscreen
20047067
FIGURE 9. Recommended TS BTL PCB Layout:
Top Layer
21
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LM4950
Demonstration Board Layout
(Continued)
20047068
FIGURE 10. Recommended TS BTL PCB Layout:
Bottom Layer
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22
LM4950
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number LM4950TS
NS Package Number TS9A
23
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LM4950
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
For Staggered Lead Non-Isolated Package
Order Number LM4950TA
NS Package Number TA09A
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24
LM4950 7.5W Mono-BTL or 3.1W Stereo Audio Power Amplifier
Notes
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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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whose failure to perform when properly used in
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2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
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