LM2524D/LM3524D Regulating Pulse Width Modulator General Description The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version. The LM3524D has a ± 1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference. In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies (.300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s. In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs. Features n n n n n n n n n Fully interchangeable with standard LM3524 family ± 1% precision 5V reference with thermal shut-down Output current to 200 mA DC 60V output capability Wide common mode input range for error-amp One pulse per period (noise suppression) Improved max. duty cycle at high frequencies Double pulse suppression Synchronize through pin 3 Connection Diagram 00865002 Top View Order Number LM2524DN or LM3524DN See NS Package Number N16E Order Number LM3524DM See NS Package Number M16A © 2005 National Semiconductor Corporation DS008650 www.national.com LM2524D/LM3524D Regulating Pulse Width Modulator March 2005 LM2524D/LM3524D Block Diagram 00865001 www.national.com 2 Internal Power Dissipation If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Junction Temperature Supply Voltage 1W Range (Note 2) 40V Collector Supply Voltage LM2524D −40˚C to +125˚C LM3524D 0˚C to +125˚C Maximum Junction Temperature (LM2524D) (LM3524D) Output Current DC (each) Storage Temperature Range 40V Lead Temperature (Soldering 4 sec.) 200 mA Oscillator Charging Current (Pin 7) 150˚ 55V −65˚C to +150˚C M, N Pkg. 260˚C 5 mA Electrical Characteristics (Note 1) LM2524D Symbol Parameter Conditions Typ LM3524D Tested Design Limit Limit (Note 3) (Note 4) Typ Tested Design Limit Limit (Note 3) (Note 4) Units REFERENCE SECTION VREF Output Voltage 5 4.85 4.80 5.15 5.20 5 4.75 VMin 5.25 VMax VRLine Line Regulation VIN = 8V to 40V 10 15 30 10 25 50 mVMax VRLoad Load Regulation IL = 0 mA to 20 mA 10 15 25 10 25 50 mVMax Ripple Rejection f = 120 Hz 66 Short Circuit VREF = 0 IOS Current 66 25 25 50 Output Noise 10 Hz ≤ f ≤ 10 kHz 40 Long Term TA = 125˚C 20 550 mA Min 50 180 NO dB 200 100 40 mA Max 100 µVrms Max 20 mV/kHr 350 kHzMin Stability OSCILLATOR SECTION fOSC Max. Freq. RT = 1k, CT = 0.001 µF fOSC Initial RT = 5.6k, CT = 0.01 µF Accuracy (Note 7) 500 (Note 7) 17.5 20 22.5 RT = 2.7k, CT = 0.01 µF (Note 7) 34 38 Freq. Change VIN = 8 to 40V 0.5 kHzMin 22.5 kHzMax 30 kHzMin 46 kHzMax 1.0 %Max 38 42 ∆fOSC 17.5 20 1 0.5 with VIN ∆fOSC Freq. Change TA = −55˚C to +125˚C with Temp. at 20 kHz RT = 5.6k, Output Amplitude RT = 5.6k, CT = 0.01 µF 3 2.4 3 2.4 VMin RT = 5.6k, CT = 0.01 µF 0.5 1.5 0.5 1.5 µsMax RT = 5.6k, CT = 0.01 µF 3.4 3.6 3.8 VMax 5 5 % CT = 0.01 µF VOSC (Pin 3) (Note 8) tPW Output Pulse Width (Pin 3) Sawtooth Peak 3.8 Voltage 3 www.national.com LM2524D/LM3524D Absolute Maximum Ratings (Note 5) LM2524D/LM3524D Electrical Characteristics (Continued) (Note 1) LM2524D Symbol Parameter Conditions Design Tested Limit Limit Design Limit Limit (Note 3) (Note 4) (Note 3) (Note 4) 1.1 0.8 0.6 0.6 VMin VCM = 2.5V 2 8 10 2 10 mVMax VCM = 2.5V 1 8 10 1 10 µAMax VCM = 2.5V 0.5 1.0 1 0.5 1 µAMax 65 µAMin 125 125 µAMax −125 −125 µAMin Typ Sawtooth Valley LM3524D Tested RT = 5.6k, CT = 0.01 µF Typ Units Voltage ERROR-AMP SECTION VIO Input Offset Voltage IIB Input Bias Current IIO Input Offset Current ICOSI Compensation VIN(I) − VIN(NI) = 150 mV Current (Sink) ICOSO Compensation 65 95 VIN(NI) − VIN(I) = 150 mV Current (Source) 95 −95 −95 −65 AVOL Open Loop Gain VCMR CMRR RL = ∞, VCM = 2.5 V −65 60 Common Mode 1.5 1.4 1.5 VMin Input Voltage Range 5.5 5.4 5.5 VMax 80 dBMin 90 80 80 90 70 µAMax 74 Common Mode 80 60 dBMin Rejection Ratio GBW Unity Gain AVOL = 0 dB, VCM = 2.5V 3 2 MHz Bandwidth VO Output Voltage RL = ∞ 0.5 Swing PSRR Power Supply 0.5 5.5 VMin 5.5 VMax 80 65 dbMin 0 0 0 %Max 49 45 49 45 %Min 44 35 44 35 %Min VIN = 8 to 40V 80 Minimum Duty Pin 9 = 0.8V, 0 Cycle [RT = 5.6k, CT = 0.01 µF] Maximum Duty Pin 9 = 3.9V, Cycle [RT = 5.6k, CT = 0.01 µF] Maximum Duty Pin 9 = 3.9V, Cycle [RT = 1k, CT = 0.001 µF] Input Threshold Zero Duty Cycle 70 Rejection Ratio COMPARATOR SECTION VCOMPZ 1 1 V 3.5 3.5 V −1 −1 µA (Pin 9) VCOMPM Input Threshold Maximum Duty Cycle (Pin 9) IIB Input Bias Current CURRENT LIMIT SECTION VSEN Sense Voltage V(Pin 2) − V(Pin 150 mV 1) ≥ 180 200 4 mVMin 220 mVMax 200 220 www.national.com 180 (Continued) (Note 1) LM2524D Symbol Parameter Conditions Typ TC-Vsense LM3524D Tested Design Limit Limit (Note 3) (Note 4) Typ Tested Design Limit Limit (Note 3) (Note 4) Units Sense Voltage T.C. 0.2 0.2 Common Mode −0.7 −0.7 VMin V5 − V4 = 300 mV 1 1 VMax ≥ 1 Voltage Range mV/˚C SHUT DOWN SECTION VSD ISD High Input V(Pin Voltage 150 mV High Input I(pin 10) 2) − V(Pin 1) 0.5 1 1.5 1 0.5 VMin 1.5 VMax 1 mA Current OUTPUT SECTION (EACH OUTPUT) VCES Collector Emitter IC ≤ 100 µA 55 40 VMin Voltage Breakdown ICES Collector Leakage VCE = 60V Current VCE = 55V Saturation 0.1 50 0.1 50 IE = 20 mA 0.2 0.5 0.2 0.7 Voltage IE = 200 mA 1.5 2.2 1.5 2.5 Emitter Output IE = 50 mA 18 17 18 17 VCE = 40V VCESAT VEO µAMax VMax VMin Voltage tR Rise Time VIN = 20V, IE = −250 µA 200 200 ns 100 100 ns RC = 2k tF Fall Time RC = 2k SUPPLY CHARACTERISTICS SECTION VIN Input Voltage After Turn-on Range T Thermal Shutdown (Note 2) 8 8 VMin 40 40 VMax 160 160 ˚C Temp. IIN Stand By Current VIN = 40V (Note 6) 5 10 5 10 mA Note 1: Unless otherwise stated, these specifications apply for TA = TJ = 25˚C. Boldface numbers apply over the rated temperature range: LM2524D is −40˚ to 85˚C and LM3524D is 0˚C to 70˚C. VIN = 20V and fOSC = 20 kHz. Note 2: For operation at elevated temperatures, devices in the N package must be derated based on a thermal resistance of 86˚C/W, junction to ambient. Devices in the M package must be derated at 125˚C/W, junction to ambient. Note 3: Tested limits are guaranteed and 100% tested in production. Note 4: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to calculate outgoing quality level. Note 5: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open. Note 7: The value of a Ct capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used in this test. NPO ceramic or polypropylene can also be used. Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast pulses. 5 www.national.com LM2524D/LM3524D Electrical Characteristics LM2524D/LM3524D Typical Performance Characteristics Switching Transistor Peak Output Current vs Temperature Maximum Average Power Dissipation (N, M Packages) 00865029 00865028 Maximum & Minimum Duty Cycle Threshold Voltage Output Transistor Saturation Voltage 00865030 00865031 Output Transistor Emitter Voltage Reference Transistor Peak Output Current 00865032 www.national.com 00865033 6 LM2524D/LM3524D Typical Performance Characteristics (Continued) Standby Current vs Voltage Standby Current vs Temperature 00865034 00865035 Current Limit Sense Voltage 00865036 Test Circuit 00865004 7 www.national.com LM2524D/LM3524D Functional Description INTERNAL VOLTAGE REGULATOR The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator provides a supply for all internal circuitry of the device and can be used as an external reference. For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V regulator. With these pins shorted the input voltage must be limited to a maximum of 6V. If input voltages of 6V–8V are to be used, a pre-regulator, as shown in Figure 1, must be added. 00865005 FIGURE 2. 00865010 *Minimum CO of 10 µF required for stability. FIGURE 1. OSCILLATOR The LM3524D provides a stable on-board oscillator. Its frequency is set by an external resistor, RT and capacitor, CT. A graph of RT, CT vs oscillator frequency is shown is Figure 2. The oscillator’s output provides the signals for triggering an internal flip-flop, which directs the PWM information to the outputs, and a blanking pulse to turn off both outputs during transitions to ensure that cross conduction does not occur. The width of the blanking pulse, or dead time, is controlled by the value of CT, as shown in Figure 3. The recommended values of RT are 1.8 kΩ to 100 kΩ, and for CT, 0.001 µF to 0.1 µF. If two or more LM3524D’s must be synchronized together, the easiest method is to interconnect all pin 3 terminals, tie all pin 7’s (together) to a single CT, and leave all pin 6’s open except one which is connected to a single RT. This method works well unless the LM3524D’s are more than 6" apart. 00865006 FIGURE 3. ERROR AMPLIFIER The error amplifier is a differential input, transconductance amplifier. Its gain, nominally 86 dB, is set by either feedback or output loading. This output loading can be done with either purely resistive or a combination of resistive and reactive components. A graph of the amplifier’s gain vs output load resistance is shown in Figure 4. A second synchronization method is appropriate for any circuit layout. One LM3524D, designated as master, must have its RTCT set for the correct period. The other slave LM3524D(s) should each have an RTCT set for a 10% longer period. All pin 3’s must then be interconnected to allow the master to properly reset the slave units. The oscillator may be synchronized to an external clock source by setting the internal free-running oscillator frequency 10% slower than the external clock and driving pin 3 with a pulse train (approx. 3V) from the clock. Pulse width should be greater than 50 ns to insure full synchronization. 00865007 FIGURE 4. www.national.com 8 CURRENT LIMITING The function of the current limit amplifier is to override the error amplifier’s output and take control of the pulse width. The output duty cycle drops to about 25% when a current limit sense voltage of 200 mV is applied between the +CL and −CLsense terminals. Increasing the sense voltage approximately 5% results in a 0% output duty cycle. Care should be taken to ensure the −0.7V to +1.0V input commonmode range is not exceeded. In most applications, the current limit sense voltage is produced by a current through a sense resistor. The accuracy of this measurement is limited by the accuracy of the sense resistor, and by a small offset current, typically 100 µA, flowing from +CL to −CL. (Continued) The output of the amplifier, or input to the pulse width modulator, can be overridden easily as its output impedance is very high (ZO . 5 MΩ). For this reason a DC voltage can be applied to pin 9 which will override the error amplifier and force a particular duty cycle to the outputs. An example of this could be a non-regulating motor speed control where a variable voltage was applied to pin 9 to control motor speed. A graph of the output duty cycle vs the voltage on pin 9 is shown in Figure 5. The duty cycle is calculated as the percentage ratio of each output’s ON-time to the oscillator period. Paralleling the outputs doubles the observed duty cycle. OUTPUT STAGES The outputs of the LM3524D are NPN transistors, capable of a maximum current of 200 mA. These transistors are driven 180˚ out of phase and have non-committed open collectors and emitters as shown in Figure 6. 00865009 00865008 FIGURE 6. FIGURE 5. The amplifier’s inputs have a common-mode input range of 1.5V–5.5V. The on board regulator is useful for biasing the inputs to within this range. 9 www.national.com LM2524D/LM3524D Functional Description LM2524D/LM3524D Typical Applications 00865011 FIGURE 7. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA) 00865012 FIGURE 8. Positive Regulator, Step-Up Boosted Current Configuration www.national.com 10 LM2524D/LM3524D Typical Applications (Continued) 00865013 FIGURE 9. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA) 11 www.national.com LM2524D/LM3524D Typical Applications (Continued) 00865014 FIGURE 10. Positive Regulator, Step-Down Boosted Current Configuration 00865015 FIGURE 11. Boosted Current Polarity Inverter www.national.com 12 (Continued) The circuit works as follows: Q1 is used as a switch, which has ON and OFF times controlled by the pulse width modulator. When Q1 is ON, power is drawn from VIN and supplied to the load through L1; VA is at approximately VIN, D1 is reverse biased, and Co is charging. When Q1 turns OFF the inductor L1 will force VA negative to keep the current flowing in it, D1 will start conducting and the load current will flow through D1 and L1. The voltage at VAis smoothed by the L1, Co filter giving a clean DC output. The current flowing through L1 is equal to the nominal DC load current plus some ∆IL which is due to the changing voltage across it. A good rule of thumb is to set ∆ILP-P . 40% x Io. BASIC SWITCHING REGULATOR THEORY AND APPLICATIONS The basic circuit of a step-down switching regulator circuit is shown in Figure 12, along with a practical circuit design using the LM3524D in Figure 15. 00865016 FIGURE 12. Basic Step-Down Switching Regulator 00865017 FIGURE 13. Relation of Switch Timing to Inductor Current in Step-Down Regulator Neglecting VSAT, VD, and settling ∆IL+ = ∆IL−; ηMAX will be further decreased due to switching losses in Q1. For this reason Q1 should be selected to have the maximum possible fT, which implies very fast rise and fall times. where T = Total Period The above shows the relation between VIN, Vo and duty cycle. CALCULATING INDUCTOR L1 as Q1 only conducts during tON. Since ∆IL+ = ∆IL− = 0.4Io Solving the above for L1 The efficiency, η, of the circuit is: 13 www.national.com LM2524D/LM3524D Typical Applications LM2524D/LM3524D Typical Applications (Continued) where: L1 is in Henrys f is switching frequency in Hz Also, see LM1578 data sheet for graphical methods of inductor selection. CALCULATING OUTPUT FILTER CAPACITOR Co: 00865019 Figure 13 shows L1’s current with respect to Q1’s tON and tOFF times (VA is at the collector of Q1). This curent must flow to the load and Co. Co’s current will then be the difference between IL, and Io. Ico = IL − Io From Figure 13 it can be seen that current will be flowing into Co for the second half of tON through the first half of tOFF, or a time, tON/2 + tOFF/2. The current flowing for this time is ∆IL/4. The resulting ∆Vc or ∆Vo is described by: FIGURE 14. Inductor Current Slope in Step-Down Regulator A complete step-down switching regulator schematic, using the LM3524D, is illustrated in Figure 15. Transistors Q1 and Q2 have been added to boost the output to 1A. The 5V regulator of the LM3524D has been divided in half to bias the error amplifier’s non-inverting input to within its commonmode range. Since each output transistor is on for half the period, actually 45%, they have been paralleled to allow longer possible duty cycle, up to 90%. This makes a lower possible input voltage. The output voltage is set by: where VNI is the voltage at the error amplifier’s non-inverting input. Resistor R3 sets the current limit to: Figures 16, 17 and show a PC board layout and stuffing diagram for the 5V, 1A regulator of Figure 15. The regulator’s performance is listed in Table 1. For best regulation, the inductor’s current cannot be allowed to fall to zero. Some minimum load current Io, and thus inductor current, is required as shown below: www.national.com 14 LM2524D/LM3524D Typical Applications (Continued) 00865020 *Mounted to Staver Heatsink No. V5-1. Q1 = BD344 Q2 = 2N5023 L1 = > 40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core. FIGURE 15. 5V, 1 Amp Step-Down Switching Regulator 15 www.national.com LM2524D/LM3524D Typical Applications (Continued) TABLE 1. Parameter Conditions Typical Characteristics Output Voltage VIN = 10V, Io = 1A Switching Frequency VIN = 10V, Io = 1A 20 kHz Short Circuit VIN = 10V 1.3A VIN = 10V 3 mV 5V Current Limit Load Regulation Io = 0.2 − 1A Line Regulation ∆VIN = 10 − 20V, 6 mV Io = 1A Efficiency VIN = 10V, Io = 1A 80% Output Ripple VIN = 10V, Io = 1A 10 mVp-p 00865021 FIGURE 16. 5V, 1 Amp Switching Regulator, Foil Side 00865022 FIGURE 17. Stuffing Diagram, Component Side www.national.com 16 LM2524D/LM3524D Typical Applications (Continued) THE STEP-UP SWITCHING REGULATOR Figure 18 shows the basic circuit for a step-up switching regulator. In this circuit Q1 is used as a switch to alternately apply VIN across inductor L1. During the time, tON, Q1 is ON and energy is drawn from VIN and stored in L1; D1 is reverse biased and Io is supplied from the charge stored in Co. When Q1 opens, tOFF, voltage V1 will rise positively to the point where D1 turns ON. The output current is now supplied through L1, D1 to the load and any charge lost from Co during tON is replenished. Here also, as in the step-down regulator, the current through L1 has a DC component plus some ∆IL. ∆IL is again selected to be approximately 40% of IL. Figure 19 shows the inductor’s current in relation to Q1’s ON and OFF times. 00865023 FIGURE 18. Basic Step-Up Switching Regulator 00865024 FIGURE 19. Relation of Switch Timing to Inductor Current in Step-Up Regulator In calculating input current IIN(DC), which equals the inductor’s DC current, assume first 100% efficiency: Since ∆IL+ = ∆IL−, VINtON = VotOFF − VINtOFF, and neglecting VSAT and VD1 for η = 100%, POUT = PIN The above equation shows the relationship between VIN, Vo and duty cycle. 17 www.national.com LM2524D/LM3524D Typical Applications (Continued) This equation shows that the input, or inductor, current is larger than the output current by the factor (1 + tON/tOFF). Since this factor is the same as the relation between Vo and VIN, IIN(DC) can also be expressed as: So far it is assumed η = 100%, where the actual efficiency or ηMAX will be somewhat less due to the saturation voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average IL current flowing, or IIN, through either VSAT or VD1. For VSAT = VD1 = 1V this power loss becomes IIN(DC) (1V). ηMAX is then: www.national.com This equation assumes only DC losses, however ηMAX is further decreased because of the switching time of Q1 and D1. 18 The network D1, C1 forms a slow start circuit. (Continued) This holds the output of the error amplifier initially low thus reducing the duty-cycle to a minimum. Without the slow start circuit the inductor may saturate at turn-on because it has to supply high peak currents to charge the output capacitor from 0V. It should also be noted that this circuit has no supply rejection. By adding a reference voltage at the noninverting input to the error amplifier, see Figure 21, the input voltage variations are rejected. In calculating the output capacitor Co it can be seen that Co supplies Io during tON. The voltage change on Co during this time will be some ∆Vc = ∆Vo or the output ripple of the regulator. Calculation of Co is: The LM3524D can also be used in inductorless switching regulators. Figure 22 shows a polarity inverter which if connected to Figure 20 provides a −15V unregulated output. where: Co is in farads, f is the switching frequency, ∆Vo is the p-p output ripple Calculation of inductor L1 is as follows: VIN is applied across L1 where: L1 is in henrys, f is the switching frequency in Hz To apply the above theory, a complete step-up switching regulator is shown in Figure 20. Since VIN is 5V, VREF is tied to VIN. The input voltage is divided by 2 to bias the error amplifier’s inverting input. The output voltage is: 19 www.national.com LM2524D/LM3524D Typical Applications LM2524D/LM3524D Typical Applications (Continued) 00865025 L1 = > 25 turns No. 24 wire on Ferroxcube No. K300502 Toroid core. FIGURE 20. 15V, 0.5A Step-Up Switching Regulator 00865026 FIGURE 21. Replacing R3/R4 Divider in Figure 20 with Reference Circuit Improves Line Regulation 00865027 FIGURE 22. Polarity Inverter Provides Auxiliary −15V Unregulated Output from Circuit of Figure 20 www.national.com 20 LM2524D/LM3524D Physical Dimensions inches (millimeters) unless otherwise noted Molded Surface-Mount Package (M) Order Number LM3524DM NS Package Number M16A 21 www.national.com LM2524D/LM3524D Regulating Pulse Width Modulator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number LM2524DN or LM3524DN NS Package Number N16E National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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