Philips Semiconductors Product specification SMPS control circuit SG3524 DESCRIPTION PIN CONFIGURATION This monolithic integrated circuit contains all the control circuitry for a regulating power supply inverter or switching regulator. Included in a 16-pin dual-in-line package is the voltage reference, error amplifier, oscillator, pulse-width modulator, pulse steering flip-flop, dual alternating output switches and current-limiting and shut-down circuitry. This device can be used for switching regulators of either polarity, transformer-coupled DC-to-DC converters, transformerless voltage doublers and polarity converters, as well as other power control applications. The SG3524 is designed for commercial applications of 0°C to +70°C. D, F, N Packages INVERT INPUT 1 16 VREF NON-INV INPUT 2 15 VIN OSC OUTPUT 3 14 EMITTER B (+)CL SENSE 4 13 COLLECTOR B (–)CL SENSE 5 12 COLLECTOR A RT 6 11 EMITTER A CT 7 10 SHUTDOWN GROUND 8 FEATURES • Complete PWM power control circuitry • Single ended or push-pull outputs • Line and load regulation of 0.2% • 1% maximum temperature variation • Total supply current is less than 10mA • Operation beyond 100kHz 9 COMPENSATION TOP VIEW SL00174 Figure 1. Pin Configuration ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG # 16-Pin Plastic Dual In-Line Package (DIP) DESCRIPTION 0 to +70°C SG3524N SOT38-4 16-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C SG3524F 0582B 16-Pin Small Outline (SO) Package 0 to +70°C SG3524D SOT109-1 BLOCK DIAGRAM VREF 16 VIN 15 REF REG +5V TO ALL INTERNAL CIRCUITRY +5V OSCILLATOR 3 OUTPUT FLIP FLOP +5V RT 6 CT 7 (RAMP) 12 OSC 11 13 +5V + 14 E B – INV INPUT 1 +5V ERROR – AMP N.I. INPUT 2 + CB NOR COMPARATOR GROUND 8 (SUBSTRATE) CA NOR +5V + CL – 9 1k 4 +SENSE 5 –SENSE COMPENSATION 10 SHUTDOWN 10k SL00175 Figure 2. Block Diagram 1994 Aug 31 1 853-0891 13721 Philips Semiconductors Product specification SMPS control circuit SG3524 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT VIN Input voltage 40 V IOUT Output current (each output) 100 mA IREF Reference output current 50 mA Oscillator charging current 5 mA PD Power dissipation Package limitation 1000 mW Derate above 25°C 8 mW/°C 0 to +70 °C -65 to +150 °C TA Operating temperature range TSTG Storage temperature range DC ELECTRICAL CHARACTERISTICS TA=0°C to +70°C, VIN=20V, and f=20kHz, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT Min Typ Max 4.6 5.0 5.4 V Reference section VOUT ISC Output voltage Line regulation VIN=8 to 40V 10 30 mV Load regulation IL=0 to 20mA 20 50 mV Ripple rejection f=120Hz, TA=25°C 66 dB Short circuit current limit VREF=0, TA=25°C 100 mA Over operating temperature range 0.3 TA=25°C 20 mV/kHz kHz Temperature stability Long-term stability 1 % Oscillator section fMAX CT=0.001 µF, RT=2kΩ 300 Initial accuracy RT and CT constant 5 Voltage stability VIN=8 to 40V, TA=25°C 1 Over operating temperature range 2 Maximum frequency Temperature stability Output amplitude Output pulse width % % % Pin 3, TA=25°C 3.5 VP CT=0.01 µF, TA=25°C 0.5 µs Error amplifier section VOS Input offset voltage VCM=2.5V 2 10 mV IBIAS Input bias current VCM=2.5V 2 10 µA Open-loop voltage gain 68 VCM Common-mode voltage TA=25°C CMRR Common-mode rejection ratio TA=25°C BW Small-signal bandwidth VOUT Output voltage 80 1.8 dB 3.4 70 AV=0dB, TA=25°C 3 TA=25°C 0.5 % each output “ON” 0 V dB MHz 3.8 V 45 % Comparator section Duty cycle IBIAS Input threshold Zero duty cycle 1 Input threshold Maximum duty cycle 3.5 V 1 µA Input bias current V Current limiting section Sense voltage Pin 9=2V with error amplifier set for maximum out, TA=25°C 180 Sense voltage T.C. VCM 1994 Aug 31 200 220 0.2 Common-mode voltage -1 2 mV mV/°C +1 V Philips Semiconductors Product specification SMPS control circuit SG3524 DC ELECTRICAL CHARACTERISTICS (Continued) TA = 0°C to +70°C, VIN = 20V, and f = 20kHz, unless otherwise specified. SYMBOL PARAMETER LIMITS TEST CONDITIONS Min Typ Max UNIT Output section (each output) Collector-emitter voltage (breakdown) 40 V Collector-leakage current VCE=40V 0.1 50 µA Saturation voltage IC=50mA 1 2 V Emitter output voltage VIN=20V 17 18 V tR Rise time RC=2kΩ, TA=25°C 0.2 µs tF Fall time RC=2kΩ, TA=25°C 0.1 µs VIN=40V 8 Total standby current (excluding oscillator charging current, error and current limit dividers, and with outputs open) 10 mA connecting Pins 15 and 16 together to the input voltage. In this configuration, the maximum input voltage is 6.0V. THEORY OF OPERATION Voltage Reference This reference regulator may be used as a 5V source for other circuitry. It will provide up to 50mA of current itself and can easily be expanded to higher currents with an external PNP as shown in Figure 3. An internal series regulator provides a nominal 5V output which is used both to generate a reference voltage and is the regulated source for all the internal timing and controlling circuitry. This regulator may be bypassed for operation from a fixed 5V supply by Q1 SG3524 REFERENCE SECTION 100Ω 15 +VIN VREF 16 IL to 1.0A DEPENDING ON CHOICE FOR Q1 + 8 10µF GND SL00176 Figure 3. Expanded Reference Current Capability TEST CIRCUIT IS 2k 1W VIN OSC OUT 15 3 VREF 16 SG3524 8 6 7 2 RAMP 1 N.I. INPUT 9 INV. INPUT 10 VIN 8–40V 0.1 RT CT 4 COMP SHUT DOWN 2k 10k 10k 1k 12 13 11 5 14 2k 1W OUTPUTS CURRENT LIMIT 2k SL00177 Figure 4. Test Circuit 1994 Aug 31 3 Philips Semiconductors Product specification SMPS control circuit SG3524 OUTPUT DEAD TIME – microseconds 3.6 V ÷ RT and should be kept within the approximate range of 30µA to 2mA; i.e., 1.8k<RT<100k. The range of values for CT also has limits as the discharge time of CT determines the pulse-width of the oscillator output pulse. This pulse is used (among other things) as a blanking pulse to both outputs to insure that there is no possibility of having both outputs on simultaneously during transitions. This output dead time relationship is shown in Figure 5. A pulse width below approximately 0.5µs may allow false triggering of one output by removing the blanking pulse prior to the flip-flop’s reaching a stable state. If small values of CT must be used, the pulse-width may still be expanded by adding a shunt capacitance (≅100pF) to ground at the oscillator output. [(Note: Although the oscillator output is a convenient oscilloscope sync input, the cable and input capacitance may increase the blanking pulse-width slightly.)] Obviously, the upper limit to the pulse width is determined by the maximum duty cycle acceptable. Practical values of CT fall between 0.001 and 0.1 µF. 10 5 3 2 1.0 0.5 0.3 .001 .002 .005 .01 .02 .05 1 TIMING CAPACITOR VALUE (C–)–(µF) SL00178 TIMING RESISTOR (R T ) kohms Figure 5. Output Stage Dead Time as a Function of the Timing Capacitor Value The oscillator period is approximately t=RTCT where t is in microseconds when RT=Ω and CT=µF. The use of Figure 6 will allow selection of RT and CT for a wide range of operating frequencies. Note that for series regulator applications, the two outputs can be connected in parallel for an effective 0-90% duty cycle and the frequency of the oscillator is the frequency of the output. For push-pull applications, the outputs are separated and the flip-flop divides the frequency such that each output’s duty cycle is 0-45% and the overall frequency is one-half that of the oscillator. 100 50 20 10 5 External Synchronization 2 If it is desired to synchronize the SG3524 to an external clock, a pulse of ≅+3V may be applied to the oscillator output terminal with RTCT set slightly greater than the clock period. The same considerations of pulse-width apply. The impedance to ground at this point is approximately 2kΩ. 1 5 10 20 50 100 200 5001ms2ms OSCILLATOR PERIOD (µs) SL00179 If two or more SG3524s must be synchronized together, one must be designated as master with its RTCT set for the correct period. The slaves should each have an RTCT set for approximately 10% longer period than the master with the added requirement that CT(slave)=one-half CT (master). Then connecting Pin 3 on all units together will insure that the master output pulse—which occurs first and has a wider pulse width—will reset the slave units. Figure 6. Oscillator Period as a Function of RT and CT VOLTAGE GAIN - dB RL = 30MΩ Error Amplifier 80 60 RL = 1MΩ 40 RL = 300kΩ RL = 100kΩ This circuit is a simple differential input transconductance amplifier. The output is the compensation terminal, Pin 9, which is a high-impedance node (RL≅ 5MΩ). The gain is RL = 30kΩ A V g MR L 20 RL = RESISTANCE FROM PIN 9 TO GND 0 10 100 1k 10k 100k 1M FREQUENCY - (Hz) 2kT 0.002R L and can easily be reduced from a nominal of 10,000 by an external shunt resistance from Pin 9 to ground, as shown in Figure 7. 10M SL00180 In addition to DC gain control, the compensation terminal is also the place for AC phase compensation. The frequency response curves of Figure 7 show the uncompensated amplifier with a single pole at approximately 200Hz and a unity gain crossover at 5MHz. Figure 7. Amplifiers Open-Loop Gain as a Function of Frequency and Loading on Pin 9 Typically, most output filter designs will introduce one or more additional poles at a significantly lower frequency. Therefore, the best stabilizing network is a series RC combination between Pin 9 and ground which introduces a zero to cancel one of the output filter poles. A good starting point is 50kΩ plus 0.001µF. Oscillator The oscillator in the SG3524 uses an external resistor (RT) to establish a constant charging current into an external capacitor (CT). While this uses more current than a series-connected RC, it provides a linear ramp voltage on the capacitor which is also used as a reference for the comparator. The charging current is equal to 1994 Aug 31 8 IC RL 4 Philips Semiconductors Product specification SMPS control circuit SG3524 One final point on the compensation terminal is that this is also a convenient place to insert any programming signal which is to override the error amplifier. Internal shutdown and current limit circuits are connected here, but any other circuit which can sink 200µA can pull this point to ground, thus shutting off both outputs. VREF R2 5k While feedback is normally applied around the entire regulator, the error amplifier can be used with conventional operational amplifier feedback and is stable in either the inverting or non-inverting mode. Regardless of the connections, however, input common-mode limits must be observed or output signal inversions may result. For conventional regulator applications, the 5V reference voltage must be divided down as shown in Figure 8. The error amplifier may also be used in fixed duty cycle applications by using the unity gain configuration shown in the open-loop test circuit. 5k POSITIVE OUTPUT VOLTAGES 2 + 1 – R1 GND VREF R1 5k Current Limiting 2 + 1 – NEGATIVE OUTPUT VOLTAGES 5k The current limiting circuitry of the SG3524 is shown in Figure 9. R2 GND By matching the base-emitter voltages of Q1 and Q2, and assuming a negligible voltage drop across R1: SL00181 Threshold=VBE(Q1)+I1R2-VBE(Q2) Figure 8. Error Amplifier Biasing Circuits =I1R2 ≅ 200mV 9 Although this circuit provides a relatively small threshold with a negligible temperature coefficient, there are some limitations to its use, the most important of which is the ±1V common-mode range which requires sensing in the ground line. Another factor to consider is that the frequency compensation provided by R1C1 and Q1 provides a roll-off pole at approximately 300Hz. RAMP ERROR AMPLIFIER t1 C1 COMPARATOR R1 R1 Q1 Since the gain of this circuit is relatively low, there is a transition region as the current limit amplifier takes over pulse width control from the error amplifier. For testing purposes, threshold is defined as the input voltage required to get 25% duty cycle with the error amplifier signaling maximum duty cycle. Q2 5 SENSE – + 4 SL00182 In addition to constant current limiting, Pins 4 and 5 may also be used in transformer-coupled circuits to sense primary current and to shorten an output pulse, should transformer saturation occur. Another application is to ground Pin 5 and use Pin 4 as an additional shutdown terminal: i.e., the output will be off with Pin 4 open and on when it is grounded. Finally, foldback current limiting can be provided with the network of Figure 10. This circuit can reduce the short-circuit current (ISC) to approximately one-third the maximum available output current (IMAX). Figure 9. Current Limiting Circuitry of the SG3524 VO = 5V SA/SB R1 R2 RS – SENSE 5 4 + I MAX + I NOTE: SC + 1 R S V TH ) V 0R 2 R1 ) R2 V TH R S where VTH = 200mV Foldback current limiting can be used to reduce power dissipation under shorted output conditions. Figure 10. Foldback Current Limiting 1994 Aug 31 5 SL00183