NSC LM2724ALD

LM2724A
High Speed 3A Synchronous MOSFET Driver
General Description
The LM2724A is a dual N-channel MOSFET driver which
can drive both the top and bottom MOSFETs in a push-pull
structure simultaneously. The LM2724A takes a logic input
and splits it into two complimentary signals with a typical
20ns dead time in between. The built-in cross-conduction
protection circuitry prevents the top and bottom MOSFETs
from turning on simultaneously. With a bias voltage of 5V, the
peak sourcing and sinking current for each driver of the
LM2724A is about 3A. Input UVLO (Under-Voltage-LockOut) ensures that all the driver outputs stay low until the
supply rail exceeds the power-on threshold during system
power on, or after the supply rail drops below power-on
threshold by a specified hysteresis during system power
down. The cross-conduction protection circuitry detects both
driver outputs and will not turn on a driver until the other
driver output is low. The top gate voltage needed by the top
MOSFET is obtained through an external boot-strap structure. When not switching, the LM2724A only draws up to
195µA from the 5V rail. The synchronization operation of the
bottom MOSFET can be disabled by pulling the SYNC pin to
ground.
Features
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Shoot-through protection
Input Under-Voltage-Lock-Out
3A peak driving current
195µA quiescent current
28V input voltage in buck configuration
SO-8 and LLP packages
Applications
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High Current DC/DC Power Supplies
High Input Voltage Switching Regulators
Fast Transient Microprocessors
Notebook Computers
Typical Application
20073501
© 2003 National Semiconductor Corporation
DS200735
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LM2724A High Speed 3A Synchronous MOSFET Driver
June 2003
LM2724A
Connection Diagram
20073502
8-Lead SO (NS Package # M08A)
θJA = 172˚C/W
20073506
8-Lead LLP (NS Package # LDC08A)
θJA = 39˚C/W
Ordering Information
Order Number
Size
NSC Package
Drawing
LM2724AM
SO-8
M08A
Supplied As
95 Units/Rail
LM2724AMX
LM2724ALD
2500 Units/Reel
LDC08A
LDC08A
1000 Units/Rail
LM2724ALDX
4500 Units/Reel
Pin Descriptions
Pin
Name
Function
1
SW
Top driver return. Should be connected to the common node of top
and bottom FETs
2
HG
Top gate drive output. Should be connected to the top FET gate.
3
BOOT
Bootstrap. Accepts a bootstrap voltage for powering the high-side
driver
4
IN
5
SYNC
6
VCC
Connect to +5V supply
7
LG
Bottom gate drive output. Should be connected to the bottom FET
gate.
8
GND
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Accepts a logic control signal
Bottom gate enable
Ground
2
LM2724A
Block Diagram
20073503
3
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LM2724A
Absolute Maximum Ratings
Storage Temperature
(Note 1)
ESD Susceptibility
Human Body Model (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC
7V
BOOT to SW
7V
BOOT to GND (Note 2)
35V
SW to GND
30V
Junction Temperature
Soldering Time, Temperature
2.0 kV
10sec., 300˚C
Operating Ratings (Note 1)
VCC
4.3V to 6.8V
Junction Temperature Range
+150˚C
Power Dissipation
(Note 3)
−65˚C to 150˚C
-40˚C to 125˚C
720mW (SO-8)
3.2W (LLP-8)
Electrical Characteristics
LM2724A
VCC = BOOT = SYNC = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for
TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
145
195
µA
POWER SUPPLY
Iq_op
Operating Quiescent
Current
IN = 0V
TOP DRIVER
Peak Pull-Up Current
Pull-Up Rds_on
IBOOT = IHG = 0.3A
Peak Pull-down Current
3.0
A
1.2
Ω
−3.2
A
Pull-down Rds_on
ISW = IHG = 0.3A
0.5
Ω
t4
Rise Time
17
ns
t6
Fall Time
Timing Diagram, CLOAD =
3.3nF
12
ns
t3
Pull-Up Dead Time
Timing Diagram
19
ns
t5
Pull-Down Delay
Timing Diagram, from IN
Falling Edge
27
ns
3.2
A
1.1
Ω
BOTTOM DRIVER
Peak Pull-Up Current
Pull-up Rds_on
IVCC = ILG = 0.3A
Peak Pull-down Current
3.2
A
Ω
Pull-down Rds_on
IGND = ILG = 0.3A
0.6
t8
Rise Time
ns
Fall Time
Timing Diagram, CLOAD =
3.3nF
17
t2
14
ns
t7
Pull-up Dead Time
Timing Diagram
22
ns
t1
Pull-down Delay
Timing Diagram
13
ns
VCC
Under-Voltage-Lock-Out
Upper Threshold
VCC rises from 0V toward
5V
VCC
Under-Voltage-Lock-Out
Lower Threshold
VCC falls from 5V toward
0V
VCC
Under-Voltage-Lock-Out
Hysteresis
VCC falls from 5V toward 0V
LOGIC
Vuvlo_up
Vuvlo_dn
Vuvlo_hys
VIH_SYNC
SYNC Pin High Input
VIL_SYNC
SYNC Pin Low Input
Ileak_SYNC
SYNC Pin Leakage
Current
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4
2.5
V
0.8
V
55%
25%
SYNC = 5V, Sink Current
2
SYNC = 0V, Source Current
10
4
V
VCC
µA
VCC = BOOT = SYNC = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for
TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Ileak_IN
ton_min1
ton_min2
ton_min3
toff_min1
toff_min2
Parameter
IN Pin Leakage Current
Max
Units
IN = 0V, Source Current
Condition
Min
Typ
2
µA
IN = 5V, Sink Current
10
Minimum Positive Pulse
Width at IN Pin
(Note 5)
160
Minimum Positive Pulse
Width at IN Pin for HG to
Respond
(Note 6)
45
Minimum Positive Pulse
Width at IN Pin for LG to
Respond
(Note 7)
10
Minimum Negative Pulse
Width at IN Pin for LG to
Respond
(Note 8)
40
Minimum Negative Pulse
Width at IN Pin for HG to
Respond
(Note 9)
5
VIH_IN
IN High Level Input
Voltage
When IN pin goes high from
0V
VIL_IN
IN Low Level Input
Voltage
When IN pin goes low from
5V
ns
55%
25%
VCC
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates
correctly. The gaurnteed specifications apply only for the listed test conditions. Some performance characteristics may degrade when the part is not operated under
listed conditions.
Note 2: If BOOT voltage exceeds this value, the ESD structure will degrade.
Note 3: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the
ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-toambient thermal resistance, θJA, for LM2724A is 172˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 0.7W. The θJA, for
LM2724A LLP package is 39˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 3.2W.
Note 4: ESD machine model susceptibility is 200V.
Note 5: If the positive pulse width at IN pin is below this value but above ton_min2, the pulse is internally stretched to ton_min1, so the HG width will be a constant
value.
Note 6: If the positive pulse width at IN pin is below this value but above ton_min3, then HG stops responding while LG still responds to the pulse.
Note 7: If the positive pulse width at IN pin is below this value, the pulse will be completely ignored. Neither HG or LG will respond to it.
Note 8: If the negative pulse width at IN pin is below this value but above toff_min2, then LG stops responding while HG still responds.
Note 9: If the negative pulse width at IN pin is below this value, the pulse will be completely ignored. Neither HG or LG will respond to it.
5
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LM2724A
Electrical Characteristics
LM2724A (Continued)
LM2724A
Timing Diagram
20073504
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6
LM2724A
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Small Outline Package
Order Number LM2724AM, LM2724AMX
NS Package Number M08A
7
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LM2724A High Speed 3A Synchronous MOSFET Driver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead LLP Package
Order Number LM2724ALD, LM2724ALDX
NS Package Number LDC08A
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