LM2722 High Speed Synchronous/Asynchronous MOSFET Driver General Description The LM2722, part of the LM2726 family, is designed to be used with multi-phase controllers. This part differs from the LM2726 by changing the functionality of the SYNC_EN pin from a whole chip enable to a low side MOSFET enable. As a result, the SYNC_EN pin now provides control between Synchronous and Asynchronous operations. Having this control can be advantageous in portable systems since Asynchronous operations can be more efficient at very light loads. The LM2722 drives both top and bottom MOSFETs in a push-pull structure simultaneously. It takes a logic level PWM input and splits it into two complimentary signals with a typical 20ns dead time in between. The built-in cross-conduction protection circuitry prevents the top and bottom FETs from turning on simultaneously. The cross-conduction protection circuitry detects both the driver outputs and will not turn on a driver until the other driver output is low. With a bias voltage of 5V, the peak sourcing and sinking current for each driver of the LM2722 is typically 3A. In an SO-8 package, each driver is able to handle 50mA average current. Input UVLO (Under-Voltage-Lock-Out) forces both driver outputs low to ensure proper power-up and power-down operation. The gate drive bias voltage needed by the high side MOSFET is obtained through an external bootstrap. Minimum pulse width is as low as 55ns. Features n n n n n Synchronous or Asynchronous Operation Adaptive shoot-through protection Input Under-Voltage-Lock-Out Typical 20ns internal delay Plastic 8-pin SO package Applications n Driver for LM2723 Intel Mobile Northwood CPU core power supply. n High Current DC/DC Power Supplies n High Input Voltage Switching Regulators n Fast Transient Microprocessors Typical Application 20028901 Note: National is an Intel Mobile Voltage Positioning (IMVP) licensee. © 2001 National Semiconductor Corporation DS200289 www.national.com LM2722 High Speed Synchronous/Asynchronous MOSFET Driver December 2001 LM2722 Connection Diagram 8-Lead Small Outline Package 20028902 Top View Ordering Information Order Number LM2722 Package Type NSC Package Drawing LM2722M M08A LM2722MX Supplied As 95 Units/Rail 2500 Units/Reel Pin Description Pin Name Function 1 SW Top driver return. Should be connected to the common node of top and bottom FETs 2 HG Top gate drive output 3 CBOOT Bootstrap. Accepts a bootstrap voltage for powering the high-side driver 4 PWM_IN Accepts a 5V-logic control signal 5 SYNC_EN 6 VCC 7 LG 8 GND www.national.com Low gate Enable Connect to +5V supply Bottom gate drive output Ground 2 LM2722 Block Diagram 20028904 3 www.national.com LM2722 Absolute Maximum Ratings Storage Temperature (Note 1) ESD Susceptibility Human Body Model (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC 7.5V CBOOT 42V CBOOT to SW −65˚ to 150˚C Soldering Time, Temperature 1kV 10sec., 300˚C Operating Ratings (Note 1) 8V SW to PGND VCC 36V Junction Temperature +150˚C Power Dissipation (Note 2) 720mW 4V to 7V Junction Temperature Range −40˚ to 125˚C Electrical Characteristics VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max 190 300 Units POWER SUPPLY Iq_op Operating Quiescent Current PWM_IN = 0V µA Peak Pull-Up Current Test Circuit 1, Vbias = 5V, R = 0.1Ω 3.0 A Pull-Up Rds_on ICBOOT = IHG = 0.7A 1.0 Ω Peak Pull-down Current Test Circuit 2, Vbias = 5V, R = 0.1Ω −3.2 A TOP DRIVER Pull-down Rds_on ISW = IHG = 0.7A 0.5 Ω t4 Rise Time 17 ns t6 Fall Time Timing Diagram, CLOAD = 3.3nF 12 ns t3 Pull-Up Dead Time Timing Diagram 23 ns t5 Pull-Down Delay Timing Diagram, from PWM_IN Falling Edge 27 ns Peak Pull-Up Current Test Circuit 3, Vbias = 5V, R = 0.1Ω 3.2 A Pull-up Rds_on IVCC = ILG = 0.7A 1.0 Ω Peak Pull-down Current Test Circuit 4, Vbias = 5V, R = 0.1Ω 3.2 A BOTTOM DRIVER Pull-down Rds_on IGND = ILG = 0.7A 0.5 Ω t8 Rise Time 17 ns t2 Fall Time Timing Diagram, CLOAD = 3.3nF 14 ns t7 Pull-up Dead Time Timing Diagram 28 ns t1 Pull-down Delay Timing Diagram, from PWM_IN Rising Edge 13 ns Vuvlo_up Power On Threshold VCC rises from 0V toward 5V 3.7 V Vuvlo_dn Under-Voltage-Lock-Out Threshold 3.0 Vuvlo_hys Under-Voltage-Lock-Out Hysteresis 0.7 VIH_EN SYNC_EN Pin High Input VIL_EN SYNC_EN Pin Low Input LOGIC www.national.com 4 2.5 V 2.4 V 0.8 4 V V (Continued) VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Ileak_EN ton_min toff_min Parameter SYNC_EN Pin Leakage Current Condition Min EN = 5V −2 Typ 2 EN = 0V −2 2 Minimum Positive Input Pulse Width (Note 4) 55 Minimum Negative Input Pulse Width (Note 5) 55 Max Units µA ns VIH_PWM PWM_IN High Level Input Voltage When PWM_IN pin goes high from 0V VIL_PWM PWM_IN Low Level Input Voltage When PWM_IN pin goes low from 5V 2.4 0.8 V Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. Operating Ratings do not imply guaranteed performance limits. Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-toambient thermal resistance, θJA, for the LM2722, it is 172˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 0.7W. Note 3: ESD machine model susceptibility is 100V. Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. Timing Diagram 20028903 5 www.national.com LM2722 Electrical Characteristics LM2722 Test Circuits 20028906 20028905 Test Circuit 2 Test Circuit 1 20028907 20028908 Test Circuit 3 www.national.com Test Circuit 4 6 LM2722 Typical Waveforms 20028915 20028913 FIGURE 3. When Input Goes Low FIGURE 1. Switching Waveforms of Test Circuit 20028916 20028914 FIGURE 4. Minimum Positive Pulse FIGURE 2. When Input Goes High Application Information Minimum Pulse Width In order for the shoot-through prevention circuitry in the LM2722 to work properly, the pulses into the PWM_IN pin must be longer than 55ns. The internal logic waits until the first FET is off plus 20ns before turning on the opposite FET. If, after a falling edge, a rising edge occurs sooner than the specified time, toff_min, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. This condition results in the PWM_IN pin in a high state and neither FET turned on. To get out of this state, the PWM_IN pin must see a low signal for greater than 55ns, before the rising edge. This will also assure that the gate drive bias voltage has been restored by forcing the top FET source and Cboot to ground first. Then the internal circuitry is reset and normal operation will resume. Conversely, if, after a rising edge, a falling edge occurs sooner than the specified miniumum pulse width, ton_min, the IC may intermittently fail to turn on the bottom FET. As the falling edge occurs sooner and sooner, the driver will start to ignore the pulse and produce no output. This will result in the toff inductor current taking a path through a diode provided for non-synchronous operation. The circuit will resume synchronous operation when the rising PWM pulses exceed 55ns in duration. High Input Voltages or High Output Currents At input voltages above twice the output voltage and at higher power levels, the designer may find snubber networks and gate drive limiting useful in reducing EMI and preventing injurious transients. A small resistor, 1Ω to 5Ω, between the driver outputs and the MOSFET gates will slightly increase the rise time and fall time of the output stage and reduce switching noise. The trade-off is 1% to 2% in efficiency. A series R-C snubber across in parallel with the bottom FET can also be used to reduce ringing. Values of 10nF and 10Ω to 100Ω are a good starting point. 7 www.national.com LM2722 High Speed Synchronous/Asynchronous MOSFET Driver Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Package NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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