LM2725/LM2726 High Speed Synchronous MOSFET Drivers General Description The LM2725/LM2726 is a family of dual MOSFET drivers that can drive both the top MOSFET and bottom MOSFET in a push-pull structure simultaneously. It takes a logic level PWM input and splits it into two complimentary signals with a typical 20ns dead time in between. The built-in shoot-through protection circuitry prevents the top and bottom FETs from turning on simultaneously. With a bias voltage of 5V, the peak sourcing and sinking current for each driver of the LM2725 is about 1.2A and that of the LM2726 is about 3A. In an SO-8 package, each driver is able to handle 50mA average current. Input UVLO (Under-Voltage-Lock-Out) ensures that all the driver outputs stay low until the supply rail exceeds the power-on threshold during system power on, or after the supply rail drops below power-on threshold by a specified hysteresis during system power down. The cross-conduction protection circuitry detects both the driver outputs and will not turn on a driver until the other driver output is low. The top gate bias voltage needed by the top MOSFET can be obtained through an external bootstrap structure. Minimum pulse width is as low as 55ns. Features n n n n n n High peak output current Adaptive shoot-through protection 36V SW pin absolute maximum voltage Input Under-Voltage-Lock-Out Typical 20ns internal delay Plastic 8-pin SO package Applications n High Current DC/DC Power Supplies n High Input Voltage Switching Regulators n Microprocessors Typical Application DS200072-1 Connection Diagram 8-Lead Small Outline Package DS200072-2 Top View © 2000 National Semiconductor Corporation DS200072 www.national.com LM2725/LM2726 High Speed Synchronous MOSFET Drivers November 2000 LM2725/LM2726 Ordering Information Order Number Package Type LM2725 LM2726 NSC Package Drawing Supplied As LM2725M 95 Units/Rail LM2725MX 2500 Units/Reel M08A LM2726M 95 Units/Rail LM2726MX 2500 Units/Reel Pin Description Pin Name 1 SW Function Top driver return. Should be connected to the common node of top and bottom FETs 2 HG 3 CBOOT Bootstrap. Accepts a bootstrap voltage for powering the high-side driver 4 PWM_IN Accepts a 5V-logic control signal 5 EN 6 VCC 7 LG 8 GND Top gate drive output Chip Enable Connect to +5V supply Bottom gate drive output Ground Block Diagram DS200072-4 www.national.com 2 Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Susceptibility Human Body Model (Note 3) VCC 7.5V CBOOT 42V CBOOT to SW Soldering Time, Temperature +150˚C Power Dissipation (Note 2) 720mW 10sec., 300˚C VCC 36V Junction Temperature 1 kV Operating Ratings (Note 1) 8V SW to PGND −65˚ to 150˚C 4V to 7V Junction Temperature Range 0˚ to 125˚C Electrical Characteristics LM2725 VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max 180 250 0.5 15 Units POWER SUPPLY Iq_op Operating Quiescent Current PWM_IN = 0V Iq_sd Shutdown Quiescent Current EN = 0V, PWM_IN = 0V Peak Pull-Up Current Test Circuit 1, Vbias = 5V, R = 0.1Ω 1.2 A Pull-Up Rds_on ICBOOT = IHG = 0.7A 2.4 Ω Peak Pull-down Current Test Circuit 2, Vbias = 5V, R = 0.1Ω −1.0 A µA µA TOP DRIVER Pull-down Rds_on ISW = IHG = 0.7A 1.4 Ω t4 Rise Time 17 ns t6 Fall Time Timing Diagram, CLOAD = 3.3nF 10 ns t3 Pull-Up Dead Time Timing Diagram 23 ns t5 Pull-Down Delay Timing Diagram, from PWM_IN Falling Edge 21 ns Peak Pull-Up Current Test Circuit 3, Vbias = 5V, R = 0.1Ω 1.2 A Pull-up Rds_on IVCC = ILG = 0.7A 2.6 Ω Peak Pull-down Current Test Circuit 4, Vbias = 5V, R = 0.1Ω −2 A BOTTOM DRIVER Pull-down Rds_on IGND = ILG = 0.7A 0.65 Ω t8 Rise Time 18 ns t2 Fall Time Timing Diagram, CLOAD = 3.3nF 6 ns t7 Pull-up Dead Time Timing Diagram 28 ns t1 Pull-down Delay Timing Diagram, from PWM_IN Rising Edge 15 ns Vuvlo_up Power On Threshold VCC rises from 0V toward 5V 3.0 V Vuvlo_dn Under-Voltage-Lock-Out Threshold 2.5 V Vuvlo_hys Under-Voltage-Lock-Out Hysteresis 0.5 V LOGIC 3 www.national.com LM2725/LM2726 Absolute Maximum Ratings (Note 1) LM2725/LM2726 Electrical Characteristics LM2725 (Continued) VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max Units LOGIC VIH_EN EN Pin High Input VIL_EN EN Pin Low Input Ileak_EN EN Pin Leakage Current ton_min toff_min 2.4 V 0.8 EN = VCC = 5V −2 2 VCC = 5V, EN = 0V −2 2 Minimum Positive Input Pulse Width (Note 4) 55 Minimum Negative Input Pulse Width (Note 5) 55 V µA ns VIH_PWM PWM_IN High Level Input Voltage When PWM_IN pin goes high from 0V VIL_PWM PWM_IN Low Level Input Voltage When PWM_IN pin goes low from 5V 2.4 0.8 V Electrical Characteristics LM2726 VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max 185 250 0.5 15 Units POWER SUPPLY Iq_op Operating Quiescent Current PWM_IN = 0V Iq_sd Shutdown Quiescent Current EN = 0V, PWM_IN = 0V Peak Pull-Up Current Test Circuit 1, Vbias = 5V, R = 0.1Ω 3.0 A Pull-Up Rds_on ICBOOT = IHG = 1.0A 1.2 Ω Peak Pull-down Current Test Circuit 2, Vbias = 5V, R = 0.1Ω −3.2 A µA µA TOP DRIVER Pull-down Rds_on ISW = IHG = 1.0A 0.5 Ω t4 Rise Time 17 ns t6 Fall Time Timing Diagram, CLOAD = 3.3nF 12 ns t3 Pull-Up Dead Time Timing Diagram 19 ns t5 Pull-Down Delay Timing Diagram, from PWM_IN from Falling Edge 27 ns Peak Pull-Up Current Test Circuit 3, Vbias = 5V, R = 0.1Ω 3.2 A Pull-up Rds_on IVCC = ILG = 1.0A 1.1 Ω Peak Pull-down Current Test Circuit 4, Vbias = 5V, R = 0.1Ω −3.2 A BOTTOM DRIVER Pull-down Rds_on IGND = ILG = 1.0A 0.6 Ω t8 Rise Time 17 ns t2 Fall Time Timing Diagram, CLOAD = 3.3nF 14 ns t7 Pull-up Dead Time Timing Diagram 12 ns www.national.com 4 VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max Units BOTTOM DRIVER t1 Pull-down Delay Timing Diagram, from PWM_IN Rising Edge 13 ns Vuvlo_up Power On Threshold VCC rises from 0V toward 5V 2.8 V Vuvlo_dn Under-Voltage-Lock-Out Threshold 2.5 V Vuvlo_hys Under-Voltage-Lock-Out Hysteresis 0.3 V LOGIC VIH_EN EN Pin High Input VIL_EN EN Pin Low Input Ileak_EN EN Pin Leakage Current ton_min toff_min 2.4 V 0.25 EN = VCC = 5V −2 2 VCC = 5V, EN = 0V −2 2 Minimum Positive Input Pulse Width (Note 4) 55 Minimum Negative Input Pulse Width (Note 5) 55 V µA ns VIH_PWM PWM_IN High Level Input Voltage When PWM_IN pin goes high from 0V VIL_PWM PWM_IN Low Level Input Voltage When PWM_IN pin goes low from 5V 2.4 0.25 V Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. Operating Ratings do not imply guaranteed performance limits. Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-toambient thermal resistance, θJA, for LM2725/LM2726 is 172˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 0.7W. Note 3: ESD machine model susceptibility is 100V. Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. 5 www.national.com LM2725/LM2726 Electrical Characteristics LM2726 (Continued) LM2725/LM2726 Timing Diagram DS200072-3 www.national.com 6 LM2725/LM2726 Test Circuits DS200072-5 DS200072-6 Test Circuit 1 Test Circuit 2 DS200072-7 DS200072-8 Test Circuit 3 Test Circuit 4 7 www.national.com LM2725/LM2726 Typical Waveforms DS200072-13 DS200072-15 FIGURE 1. Switching Waveforms of Test Circuit FIGURE 3. When Input Goes Low DS200072-14 DS200072-16 FIGURE 2. When Input Goes High www.national.com FIGURE 4. Minimum Positive Pulse 8 LM2725/LM2726 High Speed Synchronous MOSFET Drivers Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Package NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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