LP5527 Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization General Description Features The LP5527 is a lighting management unit for handheld devices with I2C compatible control interface. The LP5527 has a step-up DC/DC converter with high current output and it drives display and keypad backlights and powers the camera flash LED. In addition the DC/DC converter has the output current to power for example an audio amplifier simultaneously. The chip has four 8-bit programmable high efficiency constant current LED drivers and a FLASH LED driver. Built-in audio synchronization feature allows the user to synchronize one of the LEDs to audio input. The LP5527 has an integrated 400 mA flash driver with a safety stop feature and 50 mA torch mode. An external enable pin is provided for the synchronizing the flash with the camera action. An external software independent test interface provides a fast way to find a broken path or short on LED circuits. Very small microSMD package together with minimum number of external components is a best fit for handheld devices. n High current boost DC-DC converter (up to 1A output current) n Programmable boost output voltage n 400 mA flash LED constant current driver with low tolerance and a safety circuit n Synchronization pin for the flash timing n Two single-ended audio inputs with gain control n Four constant current 15 mA LED drivers with 8-bit programmable brightness control n Audio synchronization feature n I2C compatible control interface n Built-in LED connectivity test to maximize manufacturing yield n Small microSMD-30 package (2.5 mm x 3.0 mm x 0.6 mm) Applications n Camera FLASH, funlight and backlight driving in battery powered devices Typical Application 20184001 © 2006 National Semiconductor Corporation DS201840 www.national.com LP5527 Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization May 2006 LP5527 Connection Diagrams and Package Mark Information Connection Diagrams microSMD-30 package, 2.466 x 2.974 x 0.60 mm body size, 0.5 mm pitch NS Package Number TLA3011A 20184002 20184003 Top View Top View PACKAGE MARK 20184004 Top View XY — Date Code TT — Die Traceability 5527 — Product Identification ORDERING INFORMATION www.national.com Order Number Package Marking Supplied As Spec/Flow LP5527TL LP5527TLX 5527 TNR 250 NoPB 5527 TNR 3000 NoPB 2 Pin Descriptions Pin Name Type Description D3 VDD1 P Supply Voltage A1 VDD2 P Supply Voltage F5 SW1 A Boost Converter Switch Boost Converter Switch E5 SW2 A D5 FB A Boost Converter Feedback B5 LED1 O LED1 Driver Output A5 LED2 O LED2 Driver Output B4 LED3 O LED3 Driver Output A4 LED4 O LED4 Driver Output F2 FLASH O Flash LED Driver Output F3 GNDC G Ground for Core Circuitry D2 RT A Oscillator Frequency Setting C1 VREF A Reference Voltage B1 VDDA P Internal LDO F4 GND_SW1 G Boost Converter Ground E4 GND_SW2 G Boost Converter Ground C5 GND_LED G LEDs 1 to 4 Driver Ground Connection F1 GND_FLASH G Flash Driver Ground Connection A2 IFLASH A Resistor for Flash Current Setting D1 GNDA G Analog Ground Connection C3 GND G Ground E1 VDD_IO P Supply Voltage for Digital Interface A3 NRST DI Low Active Reset B3 SCL DI I2C Compatible Interface Clock Signal E2 SDA OD I2C Compatible Interface Data Signal E3 FLASH_SYNC DI FLASH LED Control D4 T2 DO Test Pin (Result) C4 T1 DI Test Pin (Clock) C2 ASE1 AI Audio Input B2 ASE2 AI Audio Input A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin OD: Open Drain Pin 3 www.national.com LP5527 Connection Diagrams and Package Mark Information microSMD-30 package, 2.466 x 2.974 x 0.60 mm body size, 0.5 mm pitch NS Package Number TLA3011A (Continued) LP5527 Absolute Maximum Ratings (Notes 1, 2) ESD Rating (Note 5) Human Body Model If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltage on power pins (VDD1,2) Voltage on analog pins Operating Ratings (Note 1), (Note 2) -0.3V to +6.0V Voltage on power pins (VDD1,2) -0.3V to VDD1,2+0.3V with 6.0V max Voltage on input/output pins 10 µA I(FLASH) 500 mA Continuous Power Dissipation (Note 3) 125 C -65oC to +150oC Maximum Lead Temperature (Reflow soldering, 3 times) (Note 4) 260oC Junction Temperature (TJ) Range -30oC to +125oC Ambient Temperature (TA) Range (Note 6) -30oC to +85oC 60 - 100oC/W Junction-to-Ambient Thermal Resistance (θJA), TLA3011A Package (Note 7) o Junction Temperature (TJ-MAX) 1.65V to VDD1 Thermal Properties Internally Limited Storage Temperature Range 0V to 1.6V VDD_IO -0.3V to 6.0V I(VREF) 3.0 to 5.5V Voltage on ASE1, ASE2 -0.3V to VDD1,2+0.3V with 6.0V max V(all other pins): Voltage to GND 2 kV Electrical Characteristics (Notes 2, 8) Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP5527 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDD_IO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (Note 9) Symbol Parameter Condition ISHUT DOWN Current of VDD1 + VDD2 pins + Leakage Current of SW1, SW2, LED1 to 4 and FLASH IDD Typ Max Units Voltage on VDD_IO = 0V, NRST = L, NSTBY(bit) = L 1 5 µA Active Mode Supply Current (VDD1 + VDD2 current) NRST = H, NSTBY(bit) = H, no load, EN_BOOST(bit) = L, SCL, SDA = H 350 µA IDD No load supply current (VDD1 + VDD2 current) NSTBY(bit) = H, EN_BOOST(bit) = H, SCL, SDA, NRST = H, AUTOLOAD_EN(bit) = L 850 µA IVDDIO VDD_IO Standby Supply current NSTBY(bit) = L VDDA IVDDA = 1 mA Min -4% 2,8V 1 µA +4% V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=160oC (typ.) and disengages at TJ=140oC (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale Package. Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. MIL-STD-883 3015.7 Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125oC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. www.national.com 4 LP5527 LP5527 Block Diagram 20184005 5 www.national.com LP5527 Modes of Operation 20184006 RESET: In the reset mode all the internal registers are reset to the default values. Reset is entered always if input NRST is LOW or internal Power On Reset (POR) is active. Power on reset will activate during the chip startup or when the supply voltage VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after POR by default. STANDBY: The standby mode is entered if the register bit NSTBY is LOW and reset is not active. This is the low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after start up. STARTUP: When NSTBY bit is written high, the internal startup sequence powers up all the needed internal blocks (VREF, Oscillator, etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. If the chip temperature rises too high, the thermal shutdown (TSD) disables the chip operation and startup mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft-start for boost output is generated in the boost startup mode. The boost output is raised in a low current PWM mode during the 10 ms delay generated by the state-machine. The boost startup is entered from internal startup sequence if EN_BOOST is HIGH or from normal mode when EN_BOOST is written HIGH. NORMAL: During normal mode the user controls the chip using the Control Registers. The registers can be written in any sequence and any number of bits can be altered in a register in one write. www.national.com 6 The LP5527 boost DC/DC converter generates a 4.55 – 5.00V output voltage to drive the LEDs from a single Li-Ion battery (3.0V to 4.5V). The output voltage is controlled with a 4-bit register in 4 steps. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The converter has 2.0 MHz / 1.0 MHz selectable switching frequency operation, when the timing resistor RT is 82 kΩ. — Keeps the output below breakdown voltage. — Prevents boost operation if battery voltage is much higher than desired output. 2. Over current protection, limits the maximum inductor current The LP5527 boost converter uses pulse-skipping elimination method to stabilize the noise spectrum. Even with light load or no load a minimum length current pulse is fed to the inductor. An internal active load is used to remove the excess charge from the output capacitor when needed. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The output voltage control changes the resistor divider in the feedback loop. — Voltage over switching NMOS is monitored; too high voltages turn the switch off. 3. 4. Feedback (FB) protection for no connection. Duty cycle limiting, done with digital control. 20184077 Boost Converter Topology 7 www.national.com LP5527 The following figure shows the boost topology with the protection circuitry. Four different protection schemes are implemented: 1. Over voltage protection, limits the maximum output voltage Magnetic Boost DC/DC Converter LP5527 Magnetic Boost DC/DC Converter (Continued) MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP5527 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (Note 9) Symbol Parameter Conditions ILOAD Load Current (Note 10) 3.2V ≤ VIN ≤ 4.5V VOUT = 5.0V Min Typ VOUT Output Voltage Accuracy (FB pin) 3.2V ≤ VIN ≤ 4.5V VOUT (target value) = 5.0V, active load off Output Voltage (FB Pin) 3.0V ≤ VIN ≤ (5.0V+VSCHOTTKY) active load off 5.0 VIN > (5.0V + VSCHOTTKY) VIN - VSCHOTTKY RDSON Switch ON Resistance VIN = 3.6V, ISW = 1.0A 0.20 fPWF PWM Mode Switching Frequency RT = 82 kΩ FREQ_SEL (bit) = 1 FREQ_SEL (bit) = 0 Frequency Accuracy 3.2V ≤ VDD1,2 ≤ 4.5V RT = 82 kΩ tPULSE Switch Pulse Minimum Width no load tSTARTUP ICL_OUT −3 Max Units 670 mA +3 % V 0.4 Ω MHz 2.0 1.0 −6 -9 ±3 +6 +9 % 25 ns Startup Time 10 ms SW1+ SW2 current limit 1.7 A Note 10: Specified currents are the worst case currents. If input voltage is larger or output voltage is smaller, current can be increased according to graph "Boost Maximum Output Current". BOOST STANDBY MODE User can set the boost converter to STANDBY mode by writing the register bit EN_BOOST low when there is no load to avoid idle current consumption. When EN_BOOST is written high, the converter starts in low current PWM (Pulse Width Modulation) mode for 10 ms and then goes to normal PWM mode. BOOST CONTROL REGISTERS User can control the boost output voltage and the switching frequency according to the following tables. Boost Output Voltage [3:0] Register Boost Output Voltage (Typical) 0000 4.55V www.national.com 0001 4.70V 0011 4.85V 0111 5.00V 8 FREQ_SEL Bit Boost Switching Frequency (Typical) 0 1.0 MHz default 1 2.0 MHz TJ = 25oC. Unless otherwise noted, typical performance characteristics apply to the LP5527 Block Diagram with: VIN = 3.6V, VOUT = 5.0V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDD_IO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH (Note 9). Boost Converter Efficiency Boost Typical Waveforms at 100 mA Load 20184079 20184080 Battery Current vs Voltage Boost Frequency vs RT Resistor 20184081 20184082 Boost Line Regulation 3.0V - 3.6V, no load Boost Startup Time with No Load 20184083 20184084 9 www.national.com LP5527 Boost Converter Typical Performance Characteristics LP5527 Boost Converter Typical Performance Characteristics Boost Load Transient Response, 50 mA to 100 mA Boost Maximum Output Current 20184085 www.national.com (Continued) 20184098 10 LP5527 has an internal constant current driver that is capable for sinking low (50 mA) and high (400 mA) current mainly targeted for torch and flash LED in camera phone applications. 400 mA flash driver can be hardware or software enabled. Flash safety function prevents hardware damages due to possible overheating when the flash has been stuck on because of a hardware, software, or user error. Flash LED Control (X = don’t care) EN_TORCH bit EN_FLASH bit FLASH_SYNC bit or pin SAFETY_TIME bit Flash LED Action 0 0 X X Off 1 0 X X Torch X 1 Change from LOW to HIGH to engage; from HIGH to LOW to disengage 0 for 2.0 seconds; 1 for 1.0 second Flash Flash Programming Example Address Data Function 00H 8FH Sets safety time to 1.0s. In this example LED1 to LED4 are enabled. 00H 9FH Enables torch. 00H FFH Activates FLASH. EN_FLASH bit and FLASH_SYNC bit are written simultaneously because EN_FLASH disables torch. 00H BFH Disables FLASH. If FLASH is disabled by safety time, FLASH_SYNC bit needs to be written to 0 before next FLASH. FLASH DRIVER ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP5527 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH, RF = 1200Ω Symbol Parameter Condition Min Typ Max Units IMAX Maximum Sink Current 3.0V ≤ VIN ≤ 5.5V, VFLASH = 1.0V 370 (-7,5%) 400 430 (+7,5%) mA ITORCH Torch Mode Sink Current 3.0V ≤ VIN ≤ 5.5V 50 mA ILEAKAGE Flash Driver Leakage Current 0.1 µA tFLASH Flash Turn-On Time (Note 11) 20 µs VSAT Saturation Voltage 550 mV tSAFETY Safety Time Accuracy VFB = 5.0V 3.0V ≤VIN ≤ 5.5V, Current Decreased to 95% of the Maximum Sink Current -9 +9 % Note 11: Flash turn-on time is measured from the moment the flash is activated until the flash current crosses 90% of its target value. 11 www.national.com LP5527 Flash safety counter starts counting when the flash is activated, and disables the flash automatically when the predefined 1.0s or 2.0s time limit is reached. Flash is activated with FLASH_SYNC bit or FLASH_SYNC pin, as defined in the table below. Safety time limit is defined by SAFETY_TIME bit. (Time limit is 2.0s if SAFETY_TIME bit is low and 1.0s if the bit is high.) Flash Driver LP5527 Constant Current Sink Outputs LED1, LED2, LED3, LED4 LP5527 has four independent backlight/keypad LED drivers. All the drivers are regulated constant current sinks. LED currents are controlled by 8-bit current mode DACs. Every driver can be controlled in two ways: 1. Brightness control with constant current drivers LED Control Register (00 hex) has control bits for direct on/off control of all the LEDs. Note that the LEDs have to be turned on in order to control them with audio synchronization (LED1 only) or brightness control. The brightness is programmed as described in the following. ILED = n x (15 mA / 255) 2. Direct ON/OFF control. The current is pre-set by 8-bit current mode DAC. In addition, LED1 driver can be synchronized to audio input signal amplitude. By using brightness control user can set brightness of every single LED by using 8-bit brightness control registers. If analog audio is available on system the user can use audio synchronization for synchronizing LED1 to the music. Direct ON/OFF control is mainly for switching LEDs on and off. where: n = LED[7:0] (8-bit) step = 15 mA / 255 ≈ 0.05882 mA For example if 13.2 mA is required for driver current: n = 13.2 mA / (15 mA / 255) ≈ 224 224 = 1110 0000, E0 hex LED1 to LED4 Brightness Control LED1[7:0], LED2[7:0] LED3[7:0], LED4[7:0] Register Driver Current, mA (typical) 0000 0000 0 0000 0001 0.059 0000 0010 0.118 • 1110 0000 13.176 • • • 1111 1110 14.941 1111 1111 15 LED1 TO LED4 DRIVERS ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP5527 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (Note 9) Symbol Parameter IMAX Maximum Sink Current Condition Min ILEAKAGE Leakage Current VFB = 5.0V ILED Current Tolerance ISINK =13.2 mA (target value) IMATCH Sink Current Matching Between LED 1 to 4 ISINK =13.2 mA VSAT Saturation Voltage 3.0V ≤ VIN ≤ 5.5V, Current Decreased to 95% of the Maximum Sink Current Max 15 11.9 -10 13.2 µA 14.5 +10 1 12 150 Units mA 0.03 Note: Sink current matching is the maximum difference from the average. www.national.com Typical mA % % 230 mV The LED1 output can be synchronized to incoming audio signal with Audio Synchronization feature. Audio Synchronization synchronizes LED1 based on input signal’s peak amplitude. Programmable gain and automatic gain control function are also available for adjustment of input signal amplitude to light response. Control of LED1 brightness refreshing frequency is done with four different frequency configurations. The digitized input signal has a DC component that is removed by a digital DC-remover. The DCremover is a high-pass filter where corner frequency is user selectable by using DC_FREQ bit. LP5527 has 2-channel audio (stereo) input for audio synchronization, as shown in the figure below. The inputs accept signals in the range of 0V to 1.6V peak-to-peak and these signals are mixed into a single wave so that they can be filtered simultaneously. Automatic Gain Control (AGC) adjusts the input signal to suitable range automatically. User can disable AGC and the gain can be set manually with programmable gain. Audio synchronization is based on peak detection method. 20184016 Audio Synchronization Input Electrical Parameters Symbol Parameter ZIN Input Impedance of ASE1, ASE2 AIN ASE1, ASE2 Audio Input Level Range (peak-to-peak) Conditions Min 10 Min input level needs maximum gain; Max input level for minimum gain. 0 Typ Max Units 15 kΩ 1600 mV CONTROL OF AUDIO SYNCHRONIZATION The following table describes the controls required for audio synchronization. LED1 brightness control through serial interface is not available when audio synchronization is enabled. Audio Synchronization Control EN_SYNC Audio synchronization enabled. Set EN_SYNC = 1 to enable audio synchronization or 0 to disable. EN_AGC Automatic gain control. Set EN_AGC = 1 to enable automatic control or 0 to disable. When EN_AGC is disabled, the audio input signal gain value is defined by GAIN_SEL. GAIN_SEL[2:0] Input signal gain control. Gain has a range from 0 dB to -46 dB. SPEED_CTRL[1:0] Control for refreshing frequency. Sets the typical refreshing rate for the LED1 output. THRESHOLD[3:0] Control for the audio input threshold. Sets the typical threshold for the audio inputs signals. May be needed if there is noise on the audio lines. DC_FREQ Control for the high-pass filter corner frequency. 0 = 80 Hz 1 = 510 Hz 13 www.national.com LP5527 LP5527 audio synchronization is mainly done digitally and it consists following signal path blocks (see figure below). • Input buffer • AD converter • Automatic Gain Control (AGC) and manually programmable gain • Peak detector Audio Synchronization LP5527 Audio Synchronization Input Signal Gain Control (Continued) Audio Input Threshold Setting Threshold[3:0] Threshold Level, mV (typical) 0000 Disabled 0001 0.2 0010 0.4 * * * * 1110 2.5 1111 2.7 Gain Value dB 0 to 10 0 0 to 20 -6 0 to 40 -12 1 to 85 -18 3 to 170 -24 5 to 400 -31 10 to 800 -37 20 to 1600 -46 Gain dB 000 0 001 -6 010 -12 011 -18 100 -24 101 -31 110 -37 111 -46 Refreshing Frequency Typical Gain Values vs. Audio Input Amplitude Audio Input Amplitude mVP-P GAIN_SEL[2:0] SPEED_CTRL[1:0] Refreshing Rate Hz 00 FASTEST 01 15 10 7.6 11 3.8 Logic Interface Characteristics Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP5527 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH (Note 9) Symbol Parameter Condition Min Typical Max Unit Logic Inputs SCL and FLASH_SYNC VIL Input Low Level VIH Input High Level II Input Current fSCL SCL Pin Clock Frequency VDD_IO = 1.65V to VDD1,2 0.2xVDD_IO V 1.0 µA 0.8xVDD_IO V -1.0 400 kHz Logic Input NRST VIL Input Low Level VIH Input High Level 1.2 II Input Current -1.0 tNRST Reset Pulse Width VDD_IO = 1.65V to VDD1,2 0.5 V 1.0 µA V 10 µs Logic Input/Output SDA VOL Output Low Level IOUT = 3 mA IL Output leakage current VOUT = 2.8V www.national.com 0.3 14 0.5 V 1.0 µA TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP5527 address is 4C hex. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. I2C SIGNALS The SCL pin is used for the I2C clock and the SDA pin is used for bidirectional data transfer. Both these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are determined by the capacitance of the bus (typ. ~1.8 kΩ). Signal timing specifications are shown in table I2C Timing Parameters. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the I2C Read Cycle waveform. 20184049 I2C Signals: Data Validity 20184051 I2C Chip Address 4C hex for LP5527 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 20184050 I2C Start and Stop Conditions 15 www.national.com LP5527 I2C Compatible Interface LP5527 I2C Compatible Interface (Continued) 20184017 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = chip address, 4C hex for LP5527. I2C Write Cycle 20184018 I2C Read Cycle 20184054 I2C Timing Diagram I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.65V to VDD1,2) Symbol Limit Parameter Min Max Units 1 Hold Time (repeated) START Condition 0.6 2 Clock Low Time 1.3 µs µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 5 Data Hold Time (Output direction, delay generated by LP5527) 300 900 ns 5 Data Hold Time (Input direction) 0 900 ns 6 Data Setup Time ns 100 ns 7 Rise Time of SDA and SCL 20+0.1Cb 300 8 Fall Time of SDA and SCL 15+0.1Cb 300 9 Set-up Time for STOP condition www.national.com 600 16 ns ns ns (Continued) 10 Bus Free Time between a STOP and a START Condition 1.3 Cb Capacitive Load for Each Bus Line 10 µs 200 pF NOTE: Data guaranteed by design pull-down resistor. T2 is an output line for the test result with an internal 200 kΩ pull-down resistor. When T1 is low, T2 is always pulled down; when T1 is high, T2 is indicating the result of the test. Test Interface The test bus can be controlled externally or internally. For the external control, the LP5527 pins VDD1,2 only need to be powered. External control is independent on status of NRST and VDDIO pins. T1 is an input and it has an internal 6 kΩ 20184019 High Level Schematic Representation of the Test Interface The device is capable of detecting a defective unit in three cases: • Production test 1: The LP5527 is assembled on a printed wiring board (PWB), but there is no LEDs connected on current sink outputs. An external 4.2V test voltage is supplied on the VDD1 and VDD2 pins, from which follows that the reset operating mode is entered with POR. Test pin T1 is pulled high. The chip will send an acknowledge “1” onto the T2 pin if the chip is in working order; otherwise T2 stays low (0). Refer to Test Interface Timing Diagram. • Production test 2: The LP5527 is assembled on a PWB with the external components shown in LP5527 Block Diagram. 4.2V voltage is connected to VDD1, VDD2 and FB pins (see the figure above), from which follows that the reset operating mode is entered with POR. Test pin T1 is pulled high. The chip will send an acknowledge “1” • 17 onto the T2 pin if the chip is in working order; otherwise T2 stays low (0). If the ACK is “1”, a repetitive test pattern “0-1-0-1-0-1-0-1-0-1-0-1” is applied to T1 pin and if the LED corresponding the pattern (see Test Interface Timing Diagram) is connected properly T2 gives “1”, otherwise T2 stays low. The last “1” disengages the test. Field test: Build-in self-test through the I2C compatible control interface. The LP5527 is enabled (NSTBY(bit) = 1, EN_BOOST(bit) = 1) and external test pins T1 and T2 are disconnected. The result can be read through the I2C compatible control interface. LED test is enabled by writing to address 0Ch hex data 01h. Result can be read from the same address during the next I2C cycle. Note: I2C compatible interface clock signal controls the timing of the test procedure. For that reason the clock signal frequency should be 50 kHz or less during the build-in self-test. www.national.com LP5527 I2C Compatible Interface LP5527 Test Interface (Continued) 20184020 Test Interface Timing Diagram Test Interface Timing Parameters Limit Symbol Condition Parameter 1 VDD1,2 = 4.2V Min Max Units Setup Time after VDD1,2 = 4.2V 1 ms 2 Clock High Time 200 µs 3 Clock Low Time 200 4 Test Result Settling Time 5 Data Hold Time 0 µs 10 µs 10 ns NOTE: Data guaranteed by design Test Interface Characteristics Limits in standard typeface are for TJ = 25oC. Symbol Parameter Condition Min Typ Max Units 0.5 V Logic Input T1 VIL Input Low Level VIH Input High Level VDD1,2 = 4.2V 1.2 V Logic Output T2 VOL Output Low Level VDD1,2 = 4.2V, IOUT = 3 mA (pull-up current) VOH Output High Level VDD1,2 =4.2V, IOUT = -3 mA (pull-down current) 0.3 VDD1,2 - 0,5 0.5 V 3.9 V 500 µA Internal Current Sink ISINK Sink Current VDD1,2 = 4.2V Connectivity Test Pass Range VPASS1 Voltage Over the Internal Current Sink; Low Level VPASS2 Voltage Over the Internal Current Sink; High Level VPASS3 Voltage Over the Internal Current Sink; Low Level VPASS4 Voltage Over the Internal Current Sink; High Level Production test cases VDD1,2 = 4.2V VOUT = 3.9V to 4.2V 0.05 -50 0.10 0.16 +60 V % 2.03 -30 2.90 3.77 +30 V % Field test cases VDD1,2 = 3.0V...4.2V VOUT = 5.0V ± 5% -30% 0.40 +30% V -10% 3.95 +10% V NOTE: Data guaranteed by design www.national.com 18 OUTPUT CAPACITOR, COUT1, COUT2 The output capacitors COUT1, COUT2 directly affect the magnitude of the output ripple voltage. In general, the higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple that the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower that the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V is recommended Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied voltage. The capacitance value can fall to below half of the nominal capacitance. Too low output capacitance can make the boost converter unstable. INDUCTOR, L1 The LP5527 high switching frequency enables the use of the small surface mount inductor. A 4.7 µH shielded inductor is suggested for 2 MHz switching frequency. The inductor should have a saturation current rating higher than the peak current it will experience during circuit operation (~1.7A at maximum load). Less than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the SW1 and SW2 pins as close to the IC as possible. Example of a suitable inductor is TDK type VLCF5020T-4R7N1R7-1. INPUT CAPACITOR, CIN The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is recommended. OUTPUT DIODE, D1 The output diode for a boost converter must be chosen correctly depending on the output voltage and the output current. The diode must be rated for a reverse voltage Table List of Recommended External Components Symbol Symbol Explanation Value Unit Type CVDD1 VDD1 Bypass Capacitor 100 nF Ceramic, X5R CVDD2 VDD2 Bypass Capacitor 100 nF Ceramic, X5R COUT1,2 Output Capacitors from FB to GND 2 x 10 µF ± 10% µF Ceramic, X5R, 10V CIN Input Capacitor from Battery Voltage to GND 10 ± 10% µF Ceramic, X5R, 10V CVDDIO VDD_IO Bypass Capacitor 100 nF Ceramic, X5R CVDDA VDDA Bypass Capacitor 4.7 µF Ceramic, X5R, 6.3V C1,2 Audio Input Capacitors 47 nF Ceramic, X5R RT Oscillator Frequency Bias Resistor 82 kΩ 1% RF Flash Current Set Resistor for 400 mA Sink Current 1200 Ω 1% CVREF Reference Voltage Capacitor, between VREF and GND 100 nF Ceramic, X5R L1 Boost Converter Inductor 4.7 µH Shielded, low ESR, ISAT ~1.7A D1 Rectifying Diode, VF @ maxload 0.35 V Schottky diode Flash LED User defined LED1 to LED4 19 www.national.com LP5527 greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current (~1.6A at maximum load). A Schottky diode should be used for the output diode. Schottky diodes with a low forward voltage drop (VF) and fast switching speeds are ideal for increasing efficiency in portable applications. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. In Schottky barrier diodes reverse leakage current increases quickly with the junction temperature. Therefore, reverse power dissipation and the possibility of thermal runaway has to be considered when operating under high temperature conditions. Examples of suitable diodes are Diodes Incorporated type DFLS220L, ON Semiconductor type MBRA210LT3 and Philips type PMEG1020. Recommended External Components www.national.com 20 LED Control Register LED1 LED2 LED3 LED4 ENABLES LED Test Control Boost Output Audio Sync Control1 Audio Sync Control2 00 01 02 03 04 0B 0C 0D 2A 2B r/o = Read Only REGISTER ADDR (HEX) threshold[2] 0 0 0 0 threshold[3] gain_sel[1] gain_sel[2] 1 threshold[1] 0 gain_sel[0] r/o r/o 0 led2_ok led1_ok 0 0 led4[5] en_boost 0 0 led3[5] 0 led2[5] 0 led1[5] 0 en_flash D5 nstby led4[6] 0 0 0 led4[7] led3[6] 0 0 led3[7] led2[6] led2[7] 0 0 0 led1[6] 0 led1[7] flash_sync D6 safety_time D7 1 threshold[0] 0 dc_freq r/o led3_ok 0 led4[4] 0 led3[4] 0 led2[4] 0 led1[4] 0 en_torch D4 0 led4[3] 0 led3[3] 0 led2[3] 0 led1[3] 0 en_led1 D3 0 0 en_sync 1 en_agc boost[2] 0 r/o flashled_ok 0 freq_sel 0 led4[2] 0 led3[2] 0 led2[2] 0 led1[2] 0 en_led2 D2 boost[3] r/o led4_ok 1 en_autoload LP5527 Control Registers and Default Values 0 speed_ctrl[1] 1 boost[1] 0 led4[1] 0 led3[1] 0 led2[1] 0 led1[1] 0 en_led3 D1 0 speed_ctrl[2] 1 boost[0] 0 en_test 0 led4[0] 0 led3[0] 0 led2[0] 0 led1[0] 0 en_led4 D0 LP5527 inches (millimeters) unless otherwise noted The dimension for X1, X2 and X3 are as given: • X1 = 2.466 mm ± 0.03 mm • X2 = 2.974 mm ± 0.03 mm • X3 = 0.60 mm ± 0.075 mm microSMD-30 NS Package Number TLA3011A See National Semiconductor Application Note 1112 Micro SMD Wafer Level Chip Scale Package for PCB design and assembly instructions. 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